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comparison gcc/config/s390/s390-modes.def @ 55:77e2b8dfacca gcc-4.4.5

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update it from 4.4.3 to 4.5.0
author ryoma <e075725@ie.u-ryukyu.ac.jp>
date Fri, 12 Feb 2010 23:39:51 +0900
parents a06113de4d67
children 04ced10e8804
comparison
equal deleted inserted replaced
52:c156f1bd5cd9 55:77e2b8dfacca
43 43
44 Signed compares 44 Signed compares
45 45
46 CCS: EQ LT GT UNORDERED (LTGFR, LTGR, LTR, ICM/Y, 46 CCS: EQ LT GT UNORDERED (LTGFR, LTGR, LTR, ICM/Y,
47 LTDBR, LTDR, LTEBR, LTER, 47 LTDBR, LTDR, LTEBR, LTER,
48 CG/R, C/R/Y, CGHI, CHI, 48 CG/R, C/R/Y, CGHI, CHI,
49 CDB/R, CD/R, CEB/R, CE/R, 49 CDB/R, CD/R, CEB/R, CE/R,
50 ADB/R, AEB/R, SDB/R, SEB/R, 50 ADB/R, AEB/R, SDB/R, SEB/R,
51 SRAG, SRA, SRDA) 51 SRAG, SRA, SRDA)
52 CCSR: EQ GT LT UNORDERED (CGF/R, CH/Y) 52 CCSR: EQ GT LT UNORDERED (CGF/R, CH/Y)
53 53
54 Condition codes resulting from add with overflow 54 Condition codes resulting from add with overflow
58 CCAN: EQ LT GT GT (AGHI, AHI) 58 CCAN: EQ LT GT GT (AGHI, AHI)
59 59
60 Condition codes of unsigned adds and subs 60 Condition codes of unsigned adds and subs
61 61
62 CCL: EQ NE EQ NE (ALGF/R, ALG/R, AL/R/Y, 62 CCL: EQ NE EQ NE (ALGF/R, ALG/R, AL/R/Y,
63 ALCG/R, ALC/R, 63 ALCG/R, ALC/R,
64 SLGF/R, SLG/R, SL/R/Y, 64 SLGF/R, SLG/R, SL/R/Y,
65 SLBG/R, SLB/R) 65 SLBG/R, SLB/R)
66 CCL1: GEU GEU LTU LTU (ALG/R, AL/R/Y) 66 CCL1: GEU GEU LTU LTU (ALG/R, AL/R/Y)
67 CCL2: GTU GTU LEU LEU (SLG/R, SL/R/Y) 67 CCL2: GTU GTU LEU LEU (SLG/R, SL/R/Y)
68 CCL3: EQ LTU EQ GTU (SLG/R, SL/R/Y) 68 CCL3: EQ LTU EQ GTU (SLG/R, SL/R/Y)
69 69
70 Test under mask checks 70 Test under mask checks
71 71
72 CCT: EQ NE NE NE (ICM/Y, TML, CG/R, CGHI, 72 CCT: EQ NE NE NE (ICM/Y, TML, CG/R, CGHI,
73 C/R/Y, CHI, NG/R, N/R/Y, 73 C/R/Y, CHI, NG/R, N/R/Y,
74 OG/R, O/R/Y, XG/R, X/R/Y) 74 OG/R, O/R/Y, XG/R, X/R/Y)
75 CCT1: NE EQ NE NE (TMH, TML) 75 CCT1: NE EQ NE NE (TMH, TML)
76 CCT2: NE NE EQ NE (TMH, TML) 76 CCT2: NE NE EQ NE (TMH, TML)
77 CCT3: NE NE NE EQ (TMH, TML) 77 CCT3: NE NE NE EQ (TMH, TML)
78 78
79 CCA and CCT modes are request only modes. These modes are never returned by 79 CCA and CCT modes are request only modes. These modes are never returned by
80 s390_select_cc_mode. They are only intended to match other modes. 80 s390_select_cc_mode. They are only intended to match other modes.
81 81
82 Requested mode -> Destination CC register mode 82 Requested mode -> Destination CC register mode
83 83
84 CCS, CCU, CCT, CCSR, CCUR -> CCZ 84 CCS, CCU, CCT, CCSR, CCUR -> CCZ
87 87
88 *** Comments *** 88 *** Comments ***
89 89
90 CCAP, CCAN 90 CCAP, CCAN
91 91
92 The CC obtained from add instruction usually can't be used for comparisons 92 The CC obtained from add instruction usually can't be used for comparisons
93 because its coupling with overflow flag. In case of an overflow the 93 because its coupling with overflow flag. In case of an overflow the
94 less than/greater than data are lost. Nevertheless a comparison can be done 94 less than/greater than data are lost. Nevertheless a comparison can be done
95 whenever immediate values are involved because they are known at compile time. 95 whenever immediate values are involved because they are known at compile time.
96 If you know whether the used constant is positive or negative you can predict 96 If you know whether the used constant is positive or negative you can predict
97 the sign of the result even in case of an overflow. 97 the sign of the result even in case of an overflow.
98 98
99 99
100 CCT, CCT1, CCT2, CCT3 100 CCT, CCT1, CCT2, CCT3
101 101
102 If bits of an integer masked with an AND instruction are checked, the test under 102 If bits of an integer masked with an AND instruction are checked, the test under
103 mask instructions turn out to be very handy for a set of special cases. 103 mask instructions turn out to be very handy for a set of special cases.
104 The simple cases are checks whether all masked bits are zero or ones: 104 The simple cases are checks whether all masked bits are zero or ones:
105 105
106 int a; 106 int a;
107 if ((a & (16 + 128)) == 0) -> CCT/CCZ 107 if ((a & (16 + 128)) == 0) -> CCT/CCZ
108 if ((a & (16 + 128)) == 16 + 128) -> CCT3 108 if ((a & (16 + 128)) == 16 + 128) -> CCT3
109 109
110 Using two extra modes makes it possible to do complete checks on two bits of an 110 Using two extra modes makes it possible to do complete checks on two bits of an
111 integer (This is possible on register operands only. TM does not provide the 111 integer (This is possible on register operands only. TM does not provide the
118 118
119 CCSR, CCUR 119 CCSR, CCUR
120 120
121 There are several instructions comparing 32 bit with 64-bit unsigned/signed 121 There are several instructions comparing 32 bit with 64-bit unsigned/signed
122 values. Such instructions can be considered to have a builtin zero/sign_extend. 122 values. Such instructions can be considered to have a builtin zero/sign_extend.
123 The problem is that in the RTL (to be canonical) the zero/sign extended operand 123 The problem is that in the RTL (to be canonical) the zero/sign extended operand
124 has to be the first one but the machine instructions like it the other way 124 has to be the first one but the machine instructions like it the other way
125 around. The following both modes can be considered as CCS and CCU modes with 125 around. The following both modes can be considered as CCS and CCU modes with
126 exchanged operands. 126 exchanged operands.
127 127
128 128
129 CCL1, CCL2 129 CCL1, CCL2
130 130
131 These modes represent the result of overflow checks. 131 These modes represent the result of overflow checks.
132 132
133 if (a + b < a) -> CCL1 state of the carry bit (CC2 | CC3) 133 if (a + b < a) -> CCL1 state of the carry bit (CC2 | CC3)
134 if (a - b > a) -> CCL2 state of the borrow bit (CC0 | CC1) 134 if (a - b > a) -> CCL2 state of the borrow bit (CC0 | CC1)
135 135
136 They are used when multi word numbers are computed dealing one SImode part after 136 They are used when multi word numbers are computed dealing one SImode part after
140 140
141 CCL3 141 CCL3
142 142
143 A logical subtract instruction sets the borrow bit in case of an overflow. 143 A logical subtract instruction sets the borrow bit in case of an overflow.
144 The resulting condition code of those instructions is represented by the 144 The resulting condition code of those instructions is represented by the
145 CCL3 mode. Together with the CCU mode this mode is used for jumpless 145 CCL3 mode. Together with the CCU mode this mode is used for jumpless
146 implementations of several if-constructs - see s390_expand_addcc for more 146 implementations of several if-constructs - see s390_expand_addcc for more
147 details. 147 details.
148 148
149 CCZ1 149 CCZ1
150 150
151 The compare and swap instructions sets the condition code to 0/1 if the 151 The compare and swap instructions sets the condition code to 0/1 if the
152 operands were equal/unequal. The CCZ1 mode ensures the result can be 152 operands were equal/unequal. The CCZ1 mode ensures the result can be
153 effectively placed into a register. 153 effectively placed into a register.
154 154
155 */ 155 */
156 156
157 157
158 CC_MODE (CCZ); 158 CC_MODE (CCZ);
159 CC_MODE (CCZ1); 159 CC_MODE (CCZ1);
160 CC_MODE (CCA); 160 CC_MODE (CCA);