Mercurial > hg > CbC > CbC_gcc
annotate gcc/config/s390/s390-modes.def @ 55:77e2b8dfacca gcc-4.4.5
update it from 4.4.3 to 4.5.0
| author | ryoma <e075725@ie.u-ryukyu.ac.jp> |
|---|---|
| date | Fri, 12 Feb 2010 23:39:51 +0900 |
| parents | a06113de4d67 |
| children | 04ced10e8804 |
| rev | line source |
|---|---|
| 0 | 1 /* Definitions of target machine for GNU compiler, for IBM S/390 |
| 2 Copyright (C) 2002, 2003, 2004, 2005, 2007 Free Software Foundation, Inc. | |
| 3 Contributed by Hartmut Penner (hpenner@de.ibm.com) and | |
| 4 Ulrich Weigand (uweigand@de.ibm.com). | |
| 5 | |
| 6 This file is part of GCC. | |
| 7 | |
| 8 GCC is free software; you can redistribute it and/or modify it under | |
| 9 the terms of the GNU General Public License as published by the Free | |
| 10 Software Foundation; either version 3, or (at your option) any later | |
| 11 version. | |
| 12 | |
| 13 GCC is distributed in the hope that it will be useful, but WITHOUT ANY | |
| 14 WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
| 15 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
| 16 for more details. | |
| 17 | |
| 18 You should have received a copy of the GNU General Public License | |
| 19 along with GCC; see the file COPYING3. If not see | |
| 20 <http://www.gnu.org/licenses/>. */ | |
| 21 | |
| 22 /* 256-bit integer mode is needed for STACK_SAVEAREA_MODE. */ | |
| 23 INT_MODE (OI, 32); | |
| 24 | |
| 25 /* Define TFmode to work around reload problem PR 20927. */ | |
| 26 FLOAT_MODE (TF, 16, ieee_quad_format); | |
| 27 | |
| 28 /* Add any extra modes needed to represent the condition code. */ | |
| 29 | |
| 30 /* | |
| 31 | |
| 32 Condition Codes | |
| 33 | |
| 34 Check for zero | |
| 35 | |
| 36 CCZ: EQ NE NE NE | |
| 37 CCZ1: EQ NE (CS) | |
| 38 | |
| 39 Unsigned compares | |
| 40 | |
| 41 CCU: EQ LTU GTU NE (CLG/R, CL/R/Y, CLM/Y, CLI/Y) | |
| 42 CCUR: EQ GTU LTU NE (CLGF/R) | |
| 43 | |
| 44 Signed compares | |
| 45 | |
| 46 CCS: EQ LT GT UNORDERED (LTGFR, LTGR, LTR, ICM/Y, | |
| 47 LTDBR, LTDR, LTEBR, LTER, | |
|
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48 CG/R, C/R/Y, CGHI, CHI, |
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49 CDB/R, CD/R, CEB/R, CE/R, |
| 0 | 50 ADB/R, AEB/R, SDB/R, SEB/R, |
| 51 SRAG, SRA, SRDA) | |
| 52 CCSR: EQ GT LT UNORDERED (CGF/R, CH/Y) | |
| 53 | |
| 54 Condition codes resulting from add with overflow | |
| 55 | |
| 56 CCA: EQ LT GT Overflow | |
| 57 CCAP: EQ LT GT LT (AGHI, AHI) | |
| 58 CCAN: EQ LT GT GT (AGHI, AHI) | |
| 59 | |
| 60 Condition codes of unsigned adds and subs | |
| 61 | |
| 62 CCL: EQ NE EQ NE (ALGF/R, ALG/R, AL/R/Y, | |
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63 ALCG/R, ALC/R, |
| 0 | 64 SLGF/R, SLG/R, SL/R/Y, |
| 65 SLBG/R, SLB/R) | |
| 66 CCL1: GEU GEU LTU LTU (ALG/R, AL/R/Y) | |
| 67 CCL2: GTU GTU LEU LEU (SLG/R, SL/R/Y) | |
| 68 CCL3: EQ LTU EQ GTU (SLG/R, SL/R/Y) | |
| 69 | |
| 70 Test under mask checks | |
| 71 | |
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72 CCT: EQ NE NE NE (ICM/Y, TML, CG/R, CGHI, |
| 0 | 73 C/R/Y, CHI, NG/R, N/R/Y, |
| 74 OG/R, O/R/Y, XG/R, X/R/Y) | |
| 75 CCT1: NE EQ NE NE (TMH, TML) | |
| 76 CCT2: NE NE EQ NE (TMH, TML) | |
| 77 CCT3: NE NE NE EQ (TMH, TML) | |
| 78 | |
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79 CCA and CCT modes are request only modes. These modes are never returned by |
| 0 | 80 s390_select_cc_mode. They are only intended to match other modes. |
| 81 | |
| 82 Requested mode -> Destination CC register mode | |
| 83 | |
| 84 CCS, CCU, CCT, CCSR, CCUR -> CCZ | |
| 85 CCA -> CCAP, CCAN | |
| 86 | |
| 87 | |
| 88 *** Comments *** | |
| 89 | |
| 90 CCAP, CCAN | |
| 91 | |
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92 The CC obtained from add instruction usually can't be used for comparisons |
| 0 | 93 because its coupling with overflow flag. In case of an overflow the |
| 94 less than/greater than data are lost. Nevertheless a comparison can be done | |
| 95 whenever immediate values are involved because they are known at compile time. | |
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96 If you know whether the used constant is positive or negative you can predict |
| 0 | 97 the sign of the result even in case of an overflow. |
| 98 | |
| 99 | |
| 100 CCT, CCT1, CCT2, CCT3 | |
| 101 | |
| 102 If bits of an integer masked with an AND instruction are checked, the test under | |
| 103 mask instructions turn out to be very handy for a set of special cases. | |
| 104 The simple cases are checks whether all masked bits are zero or ones: | |
| 105 | |
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106 int a; |
| 0 | 107 if ((a & (16 + 128)) == 0) -> CCT/CCZ |
| 108 if ((a & (16 + 128)) == 16 + 128) -> CCT3 | |
| 109 | |
| 110 Using two extra modes makes it possible to do complete checks on two bits of an | |
| 111 integer (This is possible on register operands only. TM does not provide the | |
| 112 information necessary for CCT1 and CCT2 modes.): | |
| 113 | |
| 114 int a; | |
| 115 if ((a & (16 + 128)) == 16) -> CCT1 | |
| 116 if ((a & (16 + 128)) == 128) -> CCT2 | |
| 117 | |
| 118 | |
| 119 CCSR, CCUR | |
| 120 | |
| 121 There are several instructions comparing 32 bit with 64-bit unsigned/signed | |
| 122 values. Such instructions can be considered to have a builtin zero/sign_extend. | |
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123 The problem is that in the RTL (to be canonical) the zero/sign extended operand |
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124 has to be the first one but the machine instructions like it the other way |
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125 around. The following both modes can be considered as CCS and CCU modes with |
| 0 | 126 exchanged operands. |
| 127 | |
| 128 | |
| 129 CCL1, CCL2 | |
| 130 | |
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131 These modes represent the result of overflow checks. |
| 0 | 132 |
| 133 if (a + b < a) -> CCL1 state of the carry bit (CC2 | CC3) | |
| 134 if (a - b > a) -> CCL2 state of the borrow bit (CC0 | CC1) | |
| 135 | |
| 136 They are used when multi word numbers are computed dealing one SImode part after | |
| 137 another or whenever manual overflow checks like the examples above are | |
| 138 compiled. | |
| 139 | |
| 140 | |
| 141 CCL3 | |
| 142 | |
| 143 A logical subtract instruction sets the borrow bit in case of an overflow. | |
| 144 The resulting condition code of those instructions is represented by the | |
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145 CCL3 mode. Together with the CCU mode this mode is used for jumpless |
| 0 | 146 implementations of several if-constructs - see s390_expand_addcc for more |
| 147 details. | |
| 148 | |
| 149 CCZ1 | |
| 150 | |
| 151 The compare and swap instructions sets the condition code to 0/1 if the | |
| 152 operands were equal/unequal. The CCZ1 mode ensures the result can be | |
| 153 effectively placed into a register. | |
| 154 | |
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ryoma <e075725@ie.u-ryukyu.ac.jp>
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155 */ |
| 0 | 156 |
| 157 | |
| 158 CC_MODE (CCZ); | |
| 159 CC_MODE (CCZ1); | |
| 160 CC_MODE (CCA); | |
| 161 CC_MODE (CCAP); | |
| 162 CC_MODE (CCAN); | |
| 163 CC_MODE (CCL); | |
| 164 CC_MODE (CCL1); | |
| 165 CC_MODE (CCL2); | |
| 166 CC_MODE (CCL3); | |
| 167 CC_MODE (CCU); | |
| 168 CC_MODE (CCUR); | |
| 169 CC_MODE (CCS); | |
| 170 CC_MODE (CCSR); | |
| 171 CC_MODE (CCT); | |
| 172 CC_MODE (CCT1); | |
| 173 CC_MODE (CCT2); | |
| 174 CC_MODE (CCT3); |