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comparison gcc/config/sh/sh.h @ 55:77e2b8dfacca gcc-4.4.5

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update it from 4.4.3 to 4.5.0
author ryoma <e075725@ie.u-ryukyu.ac.jp>
date Fri, 12 Feb 2010 23:39:51 +0900
parents a06113de4d67
children b7f97abdc517
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52:c156f1bd5cd9 55:77e2b8dfacca
1 /* Definitions of target machine for GNU compiler for Renesas / SuperH SH. 1 /* Definitions of target machine for GNU compiler for Renesas / SuperH SH.
2 Copyright (C) 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2 Copyright (C) 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002,
3 2003, 2004, 2005, 2006, 2007, 2008 Free Software Foundation, Inc. 3 2003, 2004, 2005, 2006, 2007, 2008, 2009 Free Software Foundation, Inc.
4 Contributed by Steve Chamberlain (sac@cygnus.com). 4 Contributed by Steve Chamberlain (sac@cygnus.com).
5 Improved by Jim Wilson (wilson@cygnus.com). 5 Improved by Jim Wilson (wilson@cygnus.com).
6 6
7 This file is part of GCC. 7 This file is part of GCC.
8 8
89 builtin_define ("__SH_FPU_ANY__"); \ 89 builtin_define ("__SH_FPU_ANY__"); \
90 if (TARGET_FPU_DOUBLE) \ 90 if (TARGET_FPU_DOUBLE) \
91 builtin_define ("__SH_FPU_DOUBLE__"); \ 91 builtin_define ("__SH_FPU_DOUBLE__"); \
92 if (TARGET_HITACHI) \ 92 if (TARGET_HITACHI) \
93 builtin_define ("__HITACHI__"); \ 93 builtin_define ("__HITACHI__"); \
94 if (TARGET_FMOVD) \
95 builtin_define ("__FMOVD_ENABLED__"); \
94 builtin_define (TARGET_LITTLE_ENDIAN \ 96 builtin_define (TARGET_LITTLE_ENDIAN \
95 ? "__LITTLE_ENDIAN__" : "__BIG_ENDIAN__"); \ 97 ? "__LITTLE_ENDIAN__" : "__BIG_ENDIAN__"); \
96 } while (0) 98 } while (0)
97 99
98 /* We can not debug without a frame pointer. */ 100 /* We can not debug without a frame pointer. */
457 #ifndef SH_DIV_STR_FOR_SIZE 459 #ifndef SH_DIV_STR_FOR_SIZE
458 #define SH_DIV_STR_FOR_SIZE "call" 460 #define SH_DIV_STR_FOR_SIZE "call"
459 #endif 461 #endif
460 462
461 #define DRIVER_SELF_SPECS "%{m2a:%{ml:%eSH2a does not support little-endian}}" 463 #define DRIVER_SELF_SPECS "%{m2a:%{ml:%eSH2a does not support little-endian}}"
462 #define OPTIMIZATION_OPTIONS(LEVEL,SIZE) \ 464
463 do { \ 465 #define OPTIMIZATION_OPTIONS(LEVEL,SIZE) sh_optimization_options (LEVEL, SIZE)
464 if (LEVEL) \
465 { \
466 flag_omit_frame_pointer = 2; \
467 if (! SIZE) \
468 sh_div_str = "inv:minlat"; \
469 } \
470 if (SIZE) \
471 { \
472 target_flags |= MASK_SMALLCODE; \
473 sh_div_str = SH_DIV_STR_FOR_SIZE ; \
474 } \
475 else \
476 { \
477 TARGET_CBRANCHDI4 = 1; \
478 TARGET_EXPAND_CBRANCHDI4 = 1; \
479 } \
480 /* We can't meaningfully test TARGET_SHMEDIA here, because -m options \
481 haven't been parsed yet, hence we'd read only the default. \
482 sh_target_reg_class will return NO_REGS if this is not SHMEDIA, so \
483 it's OK to always set flag_branch_target_load_optimize. */ \
484 if (LEVEL > 1) \
485 { \
486 flag_branch_target_load_optimize = 1; \
487 if (! (SIZE)) \
488 target_flags |= MASK_SAVE_ALL_TARGET_REGS; \
489 } \
490 /* Likewise, we can't meaningfully test TARGET_SH2E / TARGET_IEEE \
491 here, so leave it to OVERRIDE_OPTIONS to set \
492 flag_finite_math_only. We set it to 2 here so we know if the user \
493 explicitly requested this to be on or off. */ \
494 flag_finite_math_only = 2; \
495 /* If flag_schedule_insns is 1, we set it to 2 here so we know if \
496 the user explicitly requested this to be on or off. */ \
497 if (flag_schedule_insns > 0) \
498 flag_schedule_insns = 2; \
499 \
500 set_param_value ("simultaneous-prefetches", 2); \
501 } while (0)
502 466
503 #define ASSEMBLER_DIALECT assembler_dialect 467 #define ASSEMBLER_DIALECT assembler_dialect
504 468
505 extern int assembler_dialect; 469 extern int assembler_dialect;
506 470
533 497
534 #define SUBTARGET_OVERRIDE_OPTIONS (void) 0 498 #define SUBTARGET_OVERRIDE_OPTIONS (void) 0
535 499
536 extern const char *sh_fixed_range_str; 500 extern const char *sh_fixed_range_str;
537 501
538 #define OVERRIDE_OPTIONS \ 502 #define OVERRIDE_OPTIONS sh_override_options ()
539 do { \ 503
540 int regno; \
541 \
542 SUBTARGET_OVERRIDE_OPTIONS; \
543 if (flag_finite_math_only == 2) \
544 flag_finite_math_only \
545 = !flag_signaling_nans && TARGET_SH2E && ! TARGET_IEEE; \
546 if (TARGET_SH2E && !flag_finite_math_only) \
547 target_flags |= MASK_IEEE; \
548 sh_cpu = CPU_SH1; \
549 assembler_dialect = 0; \
550 if (TARGET_SH2) \
551 sh_cpu = CPU_SH2; \
552 if (TARGET_SH2E) \
553 sh_cpu = CPU_SH2E; \
554 if (TARGET_SH2A) \
555 { \
556 sh_cpu = CPU_SH2A; \
557 if (TARGET_SH2A_DOUBLE) \
558 target_flags |= MASK_FMOVD; \
559 } \
560 if (TARGET_SH3) \
561 sh_cpu = CPU_SH3; \
562 if (TARGET_SH3E) \
563 sh_cpu = CPU_SH3E; \
564 if (TARGET_SH4) \
565 { \
566 assembler_dialect = 1; \
567 sh_cpu = CPU_SH4; \
568 } \
569 if (TARGET_SH4A_ARCH) \
570 { \
571 assembler_dialect = 1; \
572 sh_cpu = CPU_SH4A; \
573 } \
574 if (TARGET_SH5) \
575 { \
576 sh_cpu = CPU_SH5; \
577 target_flags |= MASK_ALIGN_DOUBLE; \
578 if (TARGET_SHMEDIA_FPU) \
579 target_flags |= MASK_FMOVD; \
580 if (TARGET_SHMEDIA) \
581 { \
582 /* There are no delay slots on SHmedia. */ \
583 flag_delayed_branch = 0; \
584 /* Relaxation isn't yet supported for SHmedia */ \
585 target_flags &= ~MASK_RELAX; \
586 /* After reload, if conversion does little good but can cause \
587 ICEs: \
588 - find_if_block doesn't do anything for SH because we don't\
589 have conditional execution patterns. (We use conditional\
590 move patterns, which are handled differently, and only \
591 before reload). \
592 - find_cond_trap doesn't do anything for the SH because we \
593 don't have conditional traps. \
594 - find_if_case_1 uses redirect_edge_and_branch_force in \
595 the only path that does an optimization, and this causes \
596 an ICE when branch targets are in registers. \
597 - find_if_case_2 doesn't do anything for the SHmedia after \
598 reload except when it can redirect a tablejump - and \
599 that's rather rare. */ \
600 flag_if_conversion2 = 0; \
601 if (! strcmp (sh_div_str, "call")) \
602 sh_div_strategy = SH_DIV_CALL; \
603 else if (! strcmp (sh_div_str, "call2")) \
604 sh_div_strategy = SH_DIV_CALL2; \
605 if (! strcmp (sh_div_str, "fp") && TARGET_FPU_ANY) \
606 sh_div_strategy = SH_DIV_FP; \
607 else if (! strcmp (sh_div_str, "inv")) \
608 sh_div_strategy = SH_DIV_INV; \
609 else if (! strcmp (sh_div_str, "inv:minlat")) \
610 sh_div_strategy = SH_DIV_INV_MINLAT; \
611 else if (! strcmp (sh_div_str, "inv20u")) \
612 sh_div_strategy = SH_DIV_INV20U; \
613 else if (! strcmp (sh_div_str, "inv20l")) \
614 sh_div_strategy = SH_DIV_INV20L; \
615 else if (! strcmp (sh_div_str, "inv:call2")) \
616 sh_div_strategy = SH_DIV_INV_CALL2; \
617 else if (! strcmp (sh_div_str, "inv:call")) \
618 sh_div_strategy = SH_DIV_INV_CALL; \
619 else if (! strcmp (sh_div_str, "inv:fp")) \
620 { \
621 if (TARGET_FPU_ANY) \
622 sh_div_strategy = SH_DIV_INV_FP; \
623 else \
624 sh_div_strategy = SH_DIV_INV; \
625 } \
626 TARGET_CBRANCHDI4 = 0; \
627 /* Assembler CFI isn't yet fully supported for SHmedia. */ \
628 flag_dwarf2_cfi_asm = 0; \
629 } \
630 } \
631 else \
632 { \
633 /* Only the sh64-elf assembler fully supports .quad properly. */\
634 targetm.asm_out.aligned_op.di = NULL; \
635 targetm.asm_out.unaligned_op.di = NULL; \
636 } \
637 if (TARGET_SH1) \
638 { \
639 if (! strcmp (sh_div_str, "call-div1")) \
640 sh_div_strategy = SH_DIV_CALL_DIV1; \
641 else if (! strcmp (sh_div_str, "call-fp") \
642 && (TARGET_FPU_DOUBLE \
643 || (TARGET_HARD_SH4 && TARGET_SH2E) \
644 || (TARGET_SHCOMPACT && TARGET_FPU_ANY))) \
645 sh_div_strategy = SH_DIV_CALL_FP; \
646 else if (! strcmp (sh_div_str, "call-table") && TARGET_SH2) \
647 sh_div_strategy = SH_DIV_CALL_TABLE; \
648 else \
649 /* Pick one that makes most sense for the target in general. \
650 It is not much good to use different functions depending \
651 on -Os, since then we'll end up with two different functions \
652 when some of the code is compiled for size, and some for \
653 speed. */ \
654 \
655 /* SH4 tends to emphasize speed. */ \
656 if (TARGET_HARD_SH4) \
657 sh_div_strategy = SH_DIV_CALL_TABLE; \
658 /* These have their own way of doing things. */ \
659 else if (TARGET_SH2A) \
660 sh_div_strategy = SH_DIV_INTRINSIC; \
661 /* ??? Should we use the integer SHmedia function instead? */ \
662 else if (TARGET_SHCOMPACT && TARGET_FPU_ANY) \
663 sh_div_strategy = SH_DIV_CALL_FP; \
664 /* SH1 .. SH3 cores often go into small-footprint systems, so \
665 default to the smallest implementation available. */ \
666 else if (TARGET_SH2) /* ??? EXPERIMENTAL */ \
667 sh_div_strategy = SH_DIV_CALL_TABLE; \
668 else \
669 sh_div_strategy = SH_DIV_CALL_DIV1; \
670 } \
671 if (!TARGET_SH1) \
672 TARGET_PRETEND_CMOVE = 0; \
673 if (sh_divsi3_libfunc[0]) \
674 ; /* User supplied - leave it alone. */ \
675 else if (TARGET_DIVIDE_CALL_FP) \
676 sh_divsi3_libfunc = "__sdivsi3_i4"; \
677 else if (TARGET_DIVIDE_CALL_TABLE) \
678 sh_divsi3_libfunc = "__sdivsi3_i4i"; \
679 else if (TARGET_SH5) \
680 sh_divsi3_libfunc = "__sdivsi3_1"; \
681 else \
682 sh_divsi3_libfunc = "__sdivsi3"; \
683 if (sh_branch_cost == -1) \
684 sh_branch_cost \
685 = TARGET_SH5 ? 1 : ! TARGET_SH2 || TARGET_HARD_SH4 ? 2 : 1; \
686 \
687 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++) \
688 if (! VALID_REGISTER_P (regno)) \
689 sh_register_names[regno][0] = '\0'; \
690 \
691 for (regno = 0; regno < ADDREGNAMES_SIZE; regno++) \
692 if (! VALID_REGISTER_P (ADDREGNAMES_REGNO (regno))) \
693 sh_additional_register_names[regno][0] = '\0'; \
694 \
695 if (flag_omit_frame_pointer == 2) \
696 { \
697 /* The debugging information is sufficient, \
698 but gdb doesn't implement this yet */ \
699 if (0) \
700 flag_omit_frame_pointer \
701 = (PREFERRED_DEBUGGING_TYPE == DWARF2_DEBUG); \
702 else \
703 flag_omit_frame_pointer = 0; \
704 } \
705 \
706 if ((flag_pic && ! TARGET_PREFERGOT) \
707 || (TARGET_SHMEDIA && !TARGET_PT_FIXED)) \
708 flag_no_function_cse = 1; \
709 \
710 if (SMALL_REGISTER_CLASSES) \
711 { \
712 /* Never run scheduling before reload, since that can \
713 break global alloc, and generates slower code anyway due \
714 to the pressure on R0. */ \
715 /* Enable sched1 for SH4; ready queue will be reordered by \
716 the target hooks when pressure is high. We can not do this for \
717 PIC, SH3 and lower as they give spill failures for R0. */ \
718 if (!TARGET_HARD_SH4 || flag_pic) \
719 flag_schedule_insns = 0; \
720 /* ??? Current exception handling places basic block boundaries \
721 after call_insns. It causes the high pressure on R0 and gives \
722 spill failures for R0 in reload. See PR 22553 and the thread \
723 on gcc-patches \
724 <http://gcc.gnu.org/ml/gcc-patches/2005-10/msg00816.html>. */ \
725 else if (flag_exceptions) \
726 { \
727 if (flag_schedule_insns == 1) \
728 warning (0, "ignoring -fschedule-insns because of exception handling bug"); \
729 flag_schedule_insns = 0; \
730 } \
731 } \
732 \
733 if (align_loops == 0) \
734 align_loops = 1 << (TARGET_SH5 ? 3 : 2); \
735 if (align_jumps == 0) \
736 align_jumps = 1 << CACHE_LOG; \
737 else if (align_jumps < (TARGET_SHMEDIA ? 4 : 2)) \
738 align_jumps = TARGET_SHMEDIA ? 4 : 2; \
739 \
740 /* Allocation boundary (in *bytes*) for the code of a function. \
741 SH1: 32 bit alignment is faster, because instructions are always \
742 fetched as a pair from a longword boundary. \
743 SH2 .. SH5 : align to cache line start. */ \
744 if (align_functions == 0) \
745 align_functions \
746 = TARGET_SMALLCODE ? FUNCTION_BOUNDARY/8 : (1 << CACHE_LOG); \
747 /* The linker relaxation code breaks when a function contains \
748 alignments that are larger than that at the start of a \
749 compilation unit. */ \
750 if (TARGET_RELAX) \
751 { \
752 int min_align \
753 = align_loops > align_jumps ? align_loops : align_jumps; \
754 \
755 /* Also take possible .long constants / mova tables int account. */\
756 if (min_align < 4) \
757 min_align = 4; \
758 if (align_functions < min_align) \
759 align_functions = min_align; \
760 } \
761 \
762 if (sh_fixed_range_str) \
763 sh_fix_range (sh_fixed_range_str); \
764 } while (0)
765 504
766 /* Target machine storage layout. */ 505 /* Target machine storage layout. */
767 506
768 /* Define this if most significant bit is lowest numbered 507 /* Define this if most significant bit is lowest numbered
769 in instructions that operate on numbered bit-fields. */ 508 in instructions that operate on numbered bit-fields. */
886 ? 0 : sh_loop_align (A_LABEL)) 625 ? 0 : sh_loop_align (A_LABEL))
887 626
888 #define LABEL_ALIGN(A_LABEL) \ 627 #define LABEL_ALIGN(A_LABEL) \
889 ( \ 628 ( \
890 (PREV_INSN (A_LABEL) \ 629 (PREV_INSN (A_LABEL) \
891 && GET_CODE (PREV_INSN (A_LABEL)) == INSN \ 630 && NONJUMP_INSN_P (PREV_INSN (A_LABEL)) \
892 && GET_CODE (PATTERN (PREV_INSN (A_LABEL))) == UNSPEC_VOLATILE \ 631 && GET_CODE (PATTERN (PREV_INSN (A_LABEL))) == UNSPEC_VOLATILE \
893 && XINT (PATTERN (PREV_INSN (A_LABEL)), 1) == UNSPECV_ALIGN) \ 632 && XINT (PATTERN (PREV_INSN (A_LABEL)), 1) == UNSPECV_ALIGN) \
894 /* explicit alignment insn in constant tables. */ \ 633 /* explicit alignment insn in constant tables. */ \
895 ? INTVAL (XVECEXP (PATTERN (PREV_INSN (A_LABEL)), 0, 0)) \ 634 ? INTVAL (XVECEXP (PATTERN (PREV_INSN (A_LABEL)), 0, 0)) \
896 : 0) 635 : 0)
898 /* Jump tables must be 32 bit aligned, no matter the size of the element. */ 637 /* Jump tables must be 32 bit aligned, no matter the size of the element. */
899 #define ADDR_VEC_ALIGN(ADDR_VEC) 2 638 #define ADDR_VEC_ALIGN(ADDR_VEC) 2
900 639
901 /* The base two logarithm of the known minimum alignment of an insn length. */ 640 /* The base two logarithm of the known minimum alignment of an insn length. */
902 #define INSN_LENGTH_ALIGNMENT(A_INSN) \ 641 #define INSN_LENGTH_ALIGNMENT(A_INSN) \
903 (GET_CODE (A_INSN) == INSN \ 642 (NONJUMP_INSN_P (A_INSN) \
904 ? 1 << TARGET_SHMEDIA \ 643 ? 1 << TARGET_SHMEDIA \
905 : GET_CODE (A_INSN) == JUMP_INSN || GET_CODE (A_INSN) == CALL_INSN \ 644 : JUMP_P (A_INSN) || CALL_P (A_INSN) \
906 ? 1 << TARGET_SHMEDIA \ 645 ? 1 << TARGET_SHMEDIA \
907 : CACHE_LOG) 646 : CACHE_LOG)
908 647
909 /* Standard register usage. */ 648 /* Standard register usage. */
910 649
1260 code access to data items. */ 999 code access to data items. */
1261 #define PIC_OFFSET_TABLE_REGNUM (flag_pic ? PIC_REG : INVALID_REGNUM) 1000 #define PIC_OFFSET_TABLE_REGNUM (flag_pic ? PIC_REG : INVALID_REGNUM)
1262 1001
1263 #define GOT_SYMBOL_NAME "*_GLOBAL_OFFSET_TABLE_" 1002 #define GOT_SYMBOL_NAME "*_GLOBAL_OFFSET_TABLE_"
1264 1003
1265 /* Value should be nonzero if functions must have frame pointers.
1266 Zero means the frame pointer need not be set up (and parms may be accessed
1267 via the stack pointer) in functions that seem suitable. */
1268
1269 #define FRAME_POINTER_REQUIRED 0
1270
1271 /* Definitions for register eliminations. 1004 /* Definitions for register eliminations.
1272 1005
1273 We have three registers that can be eliminated on the SH. First, the 1006 We have three registers that can be eliminated on the SH. First, the
1274 frame pointer register can often be eliminated in favor of the stack 1007 frame pointer register can often be eliminated in favor of the stack
1275 pointer register. Secondly, the argument pointer register can always be 1008 pointer register. Secondly, the argument pointer register can always be
1297 { FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}, \ 1030 { FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}, \
1298 { RETURN_ADDRESS_POINTER_REGNUM, STACK_POINTER_REGNUM}, \ 1031 { RETURN_ADDRESS_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
1299 { RETURN_ADDRESS_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}, \ 1032 { RETURN_ADDRESS_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}, \
1300 { ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \ 1033 { ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
1301 { ARG_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM},} 1034 { ARG_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM},}
1302
1303 /* Given FROM and TO register numbers, say whether this elimination
1304 is allowed. */
1305 #define CAN_ELIMINATE(FROM, TO) \
1306 (!((FROM) == HARD_FRAME_POINTER_REGNUM && FRAME_POINTER_REQUIRED))
1307 1035
1308 /* Define the offset between two registers, one to be eliminated, and the other 1036 /* Define the offset between two registers, one to be eliminated, and the other
1309 its replacement, at the start of a routine. */ 1037 its replacement, at the start of a routine. */
1310 1038
1311 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \ 1039 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
1551 : (CLASS)) \ 1279 : (CLASS)) \
1552 1280
1553 #if 0 1281 #if 0
1554 #define SECONDARY_INOUT_RELOAD_CLASS(CLASS,MODE,X,ELSE) \ 1282 #define SECONDARY_INOUT_RELOAD_CLASS(CLASS,MODE,X,ELSE) \
1555 ((((REGCLASS_HAS_FP_REG (CLASS) \ 1283 ((((REGCLASS_HAS_FP_REG (CLASS) \
1556 && (GET_CODE (X) == REG \ 1284 && (REG_P (X) \
1557 && (GENERAL_OR_AP_REGISTER_P (REGNO (X)) \ 1285 && (GENERAL_OR_AP_REGISTER_P (REGNO (X)) \
1558 || (FP_REGISTER_P (REGNO (X)) && (MODE) == SImode \ 1286 || (FP_REGISTER_P (REGNO (X)) && (MODE) == SImode \
1559 && TARGET_FMOVD)))) \ 1287 && TARGET_FMOVD)))) \
1560 || (REGCLASS_HAS_GENERAL_REG (CLASS) \ 1288 || (REGCLASS_HAS_GENERAL_REG (CLASS) \
1561 && GET_CODE (X) == REG \ 1289 && REG_P (X) \
1562 && FP_REGISTER_P (REGNO (X)))) \ 1290 && FP_REGISTER_P (REGNO (X)))) \
1563 && ! TARGET_SHMEDIA \ 1291 && ! TARGET_SHMEDIA \
1564 && ((MODE) == SFmode || (MODE) == SImode)) \ 1292 && ((MODE) == SFmode || (MODE) == SImode)) \
1565 ? FPUL_REGS \ 1293 ? FPUL_REGS \
1566 : (((CLASS) == FPUL_REGS \ 1294 : (((CLASS) == FPUL_REGS \
1567 || (REGCLASS_HAS_FP_REG (CLASS) \ 1295 || (REGCLASS_HAS_FP_REG (CLASS) \
1568 && ! TARGET_SHMEDIA && MODE == SImode)) \ 1296 && ! TARGET_SHMEDIA && MODE == SImode)) \
1569 && (GET_CODE (X) == MEM \ 1297 && (MEM_P (X) \
1570 || (GET_CODE (X) == REG \ 1298 || (REG_P (X) \
1571 && (REGNO (X) >= FIRST_PSEUDO_REGISTER \ 1299 && (REGNO (X) >= FIRST_PSEUDO_REGISTER \
1572 || REGNO (X) == T_REG \ 1300 || REGNO (X) == T_REG \
1573 || system_reg_operand (X, VOIDmode))))) \ 1301 || system_reg_operand (X, VOIDmode))))) \
1574 ? GENERAL_REGS \ 1302 ? GENERAL_REGS \
1575 : (((CLASS) == TARGET_REGS \ 1303 : (((CLASS) == TARGET_REGS \
1576 || (TARGET_SHMEDIA && (CLASS) == SIBCALL_REGS)) \ 1304 || (TARGET_SHMEDIA && (CLASS) == SIBCALL_REGS)) \
1577 && !satisfies_constraint_Csy (X) \ 1305 && !satisfies_constraint_Csy (X) \
1578 && (GET_CODE (X) != REG || ! GENERAL_REGISTER_P (REGNO (X)))) \ 1306 && (!REG_P (X) || ! GENERAL_REGISTER_P (REGNO (X)))) \
1579 ? GENERAL_REGS \ 1307 ? GENERAL_REGS \
1580 : (((CLASS) == MAC_REGS || (CLASS) == PR_REGS) \ 1308 : (((CLASS) == MAC_REGS || (CLASS) == PR_REGS) \
1581 && GET_CODE (X) == REG && ! GENERAL_REGISTER_P (REGNO (X)) \ 1309 && REG_P (X) && ! GENERAL_REGISTER_P (REGNO (X)) \
1582 && (CLASS) != REGNO_REG_CLASS (REGNO (X))) \ 1310 && (CLASS) != REGNO_REG_CLASS (REGNO (X))) \
1583 ? GENERAL_REGS \ 1311 ? GENERAL_REGS \
1584 : ((CLASS) != GENERAL_REGS && GET_CODE (X) == REG \ 1312 : ((CLASS) != GENERAL_REGS && REG_P (X) \
1585 && TARGET_REGISTER_P (REGNO (X))) \ 1313 && TARGET_REGISTER_P (REGNO (X))) \
1586 ? GENERAL_REGS : (ELSE)) 1314 ? GENERAL_REGS : (ELSE))
1587 1315
1588 #define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS,MODE,X) \ 1316 #define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS,MODE,X) \
1589 SECONDARY_INOUT_RELOAD_CLASS(CLASS,MODE,X,NO_REGS) 1317 SECONDARY_INOUT_RELOAD_CLASS(CLASS,MODE,X,NO_REGS)
1594 && immediate_operand ((X), (MODE)) \ 1322 && immediate_operand ((X), (MODE)) \
1595 && ! ((fp_zero_operand (X) || fp_one_operand (X)) \ 1323 && ! ((fp_zero_operand (X) || fp_one_operand (X)) \
1596 && (MODE) == SFmode && fldi_ok ())) \ 1324 && (MODE) == SFmode && fldi_ok ())) \
1597 ? R0_REGS \ 1325 ? R0_REGS \
1598 : ((CLASS) == FPUL_REGS \ 1326 : ((CLASS) == FPUL_REGS \
1599 && ((GET_CODE (X) == REG \ 1327 && ((REG_P (X) \
1600 && (REGNO (X) == MACL_REG || REGNO (X) == MACH_REG \ 1328 && (REGNO (X) == MACL_REG || REGNO (X) == MACH_REG \
1601 || REGNO (X) == T_REG)) \ 1329 || REGNO (X) == T_REG)) \
1602 || GET_CODE (X) == PLUS)) \ 1330 || GET_CODE (X) == PLUS)) \
1603 ? GENERAL_REGS \ 1331 ? GENERAL_REGS \
1604 : (CLASS) == FPUL_REGS && immediate_operand ((X), (MODE)) \ 1332 : (CLASS) == FPUL_REGS && immediate_operand ((X), (MODE)) \
1605 ? (satisfies_constraint_I08 (X) \ 1333 ? (satisfies_constraint_I08 (X) \
1606 ? GENERAL_REGS \ 1334 ? GENERAL_REGS \
1607 : R0_REGS) \ 1335 : R0_REGS) \
1608 : ((CLASS) == FPSCR_REGS \ 1336 : ((CLASS) == FPSCR_REGS \
1609 && ((GET_CODE (X) == REG && REGNO (X) >= FIRST_PSEUDO_REGISTER) \ 1337 && ((REG_P (X) && REGNO (X) >= FIRST_PSEUDO_REGISTER) \
1610 || (GET_CODE (X) == MEM && GET_CODE (XEXP ((X), 0)) == PLUS)))\ 1338 || (MEM_P (X) && GET_CODE (XEXP ((X), 0)) == PLUS))) \
1611 ? GENERAL_REGS \ 1339 ? GENERAL_REGS \
1612 : (REGCLASS_HAS_FP_REG (CLASS) \ 1340 : (REGCLASS_HAS_FP_REG (CLASS) \
1613 && TARGET_SHMEDIA \ 1341 && TARGET_SHMEDIA \
1614 && immediate_operand ((X), (MODE)) \ 1342 && immediate_operand ((X), (MODE)) \
1615 && (X) != CONST0_RTX (GET_MODE (X)) \ 1343 && (X) != CONST0_RTX (GET_MODE (X)) \
1723 : (TARGET_SH4 || TARGET_SH2A_DOUBLE) && (GET_MODE_CLASS (MODE) == MODE_FLOAT \ 1451 : (TARGET_SH4 || TARGET_SH2A_DOUBLE) && (GET_MODE_CLASS (MODE) == MODE_FLOAT \
1724 || GET_MODE_CLASS (MODE) == MODE_COMPLEX_FLOAT)\ 1452 || GET_MODE_CLASS (MODE) == MODE_COMPLEX_FLOAT)\
1725 ? FIRST_FP_PARM_REG \ 1453 ? FIRST_FP_PARM_REG \
1726 : FIRST_PARM_REG) 1454 : FIRST_PARM_REG)
1727 1455
1728 /* Define how to find the value returned by a function. 1456 #define FUNCTION_VALUE_REGNO_P(REGNO) sh_function_value_regno_p (REGNO)
1729 VALTYPE is the data type of the value (as a tree).
1730 If the precise function being called is known, FUNC is its FUNCTION_DECL;
1731 otherwise, FUNC is 0.
1732 For the SH, this is like LIBCALL_VALUE, except that we must change the
1733 mode like PROMOTE_MODE does.
1734 ??? PROMOTE_MODE is ignored for non-scalar types. The set of types
1735 tested here has to be kept in sync with the one in explow.c:promote_mode. */
1736
1737 #define FUNCTION_VALUE(VALTYPE, FUNC) \
1738 gen_rtx_REG ( \
1739 ((GET_MODE_CLASS (TYPE_MODE (VALTYPE)) == MODE_INT \
1740 && GET_MODE_SIZE (TYPE_MODE (VALTYPE)) < 4 \
1741 && (TREE_CODE (VALTYPE) == INTEGER_TYPE \
1742 || TREE_CODE (VALTYPE) == ENUMERAL_TYPE \
1743 || TREE_CODE (VALTYPE) == BOOLEAN_TYPE \
1744 || TREE_CODE (VALTYPE) == REAL_TYPE \
1745 || TREE_CODE (VALTYPE) == OFFSET_TYPE)) \
1746 && sh_promote_prototypes (VALTYPE) \
1747 ? (TARGET_SHMEDIA64 ? DImode : SImode) : TYPE_MODE (VALTYPE)), \
1748 BASE_RETURN_VALUE_REG (TYPE_MODE (VALTYPE)))
1749
1750 /* Define how to find the value returned by a library function
1751 assuming the value has mode MODE. */
1752 #define LIBCALL_VALUE(MODE) \
1753 gen_rtx_REG ((MODE), BASE_RETURN_VALUE_REG (MODE));
1754
1755 /* 1 if N is a possible register number for a function value. */
1756 #define FUNCTION_VALUE_REGNO_P(REGNO) \
1757 ((REGNO) == FIRST_RET_REG || (TARGET_SH2E && (REGNO) == FIRST_FP_RET_REG) \
1758 || (TARGET_SHMEDIA_FPU && (REGNO) == FIRST_FP_RET_REG))
1759 1457
1760 /* 1 if N is a possible register number for function argument passing. */ 1458 /* 1 if N is a possible register number for function argument passing. */
1761 /* ??? There are some callers that pass REGNO as int, and others that pass 1459 /* ??? There are some callers that pass REGNO as int, and others that pass
1762 it as unsigned. We get warnings unless we do casts everywhere. */ 1460 it as unsigned. We get warnings unless we do casts everywhere. */
1763 #define FUNCTION_ARG_REGNO_P(REGNO) \ 1461 #define FUNCTION_ARG_REGNO_P(REGNO) \
2099 /* Alignment required for a trampoline in bits . */ 1797 /* Alignment required for a trampoline in bits . */
2100 #define TRAMPOLINE_ALIGNMENT \ 1798 #define TRAMPOLINE_ALIGNMENT \
2101 ((CACHE_LOG < 3 || (TARGET_SMALLCODE && ! TARGET_HARVARD)) ? 32 \ 1799 ((CACHE_LOG < 3 || (TARGET_SMALLCODE && ! TARGET_HARVARD)) ? 32 \
2102 : TARGET_SHMEDIA ? 256 : 64) 1800 : TARGET_SHMEDIA ? 256 : 64)
2103 1801
2104 /* Emit RTL insns to initialize the variable parts of a trampoline.
2105 FNADDR is an RTX for the address of the function's pure code.
2106 CXT is an RTX for the static chain value for the function. */
2107
2108 #define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \
2109 sh_initialize_trampoline ((TRAMP), (FNADDR), (CXT))
2110
2111 /* On SH5, trampolines are SHmedia code, so add 1 to the address. */
2112
2113 #define TRAMPOLINE_ADJUST_ADDRESS(TRAMP) do \
2114 { \
2115 if (TARGET_SHMEDIA) \
2116 (TRAMP) = expand_simple_binop (Pmode, PLUS, (TRAMP), const1_rtx, \
2117 gen_reg_rtx (Pmode), 0, \
2118 OPTAB_LIB_WIDEN); \
2119 } while (0)
2120
2121 /* A C expression whose value is RTL representing the value of the return 1802 /* A C expression whose value is RTL representing the value of the return
2122 address for the frame COUNT steps up from the current frame. 1803 address for the frame COUNT steps up from the current frame.
2123 FRAMEADDR is already the frame pointer of the COUNT frame, so we 1804 FRAMEADDR is already the frame pointer of the COUNT frame, so we
2124 can ignore COUNT. */ 1805 can ignore COUNT. */
2125 1806
2195 || GET_MODE (X) == DFmode || GET_MODE (X) == SFmode \ 1876 || GET_MODE (X) == DFmode || GET_MODE (X) == SFmode \
2196 || GET_MODE (X) == DImode || GET_MODE (X) == VOIDmode)) 1877 || GET_MODE (X) == DImode || GET_MODE (X) == VOIDmode))
2197 1878
2198 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx 1879 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
2199 and check its validity for a certain class. 1880 and check its validity for a certain class.
2200 We have two alternate definitions for each of them. 1881 The suitable hard regs are always accepted and all pseudo regs
2201 The usual definition accepts all pseudo regs; the other rejects 1882 are also accepted if STRICT is not set. */
2202 them unless they have been allocated suitable hard regs. 1883
2203 The symbol REG_OK_STRICT causes the latter definition to be used. */ 1884 /* Nonzero if X is a reg that can be used as a base reg. */
2204 1885 #define REG_OK_FOR_BASE_P(X, STRICT) \
2205 #ifndef REG_OK_STRICT 1886 (GENERAL_OR_AP_REGISTER_P (REGNO (X)) \
2206 1887 || (!STRICT && REGNO (X) >= FIRST_PSEUDO_REGISTER))
2207 /* Nonzero if X is a hard reg that can be used as a base reg 1888
2208 or if it is a pseudo reg. */ 1889 /* Nonzero if X is a reg that can be used as an index. */
2209 #define REG_OK_FOR_BASE_P(X) \ 1890 #define REG_OK_FOR_INDEX_P(X, STRICT) \
2210 (GENERAL_OR_AP_REGISTER_P (REGNO (X)) || REGNO (X) >= FIRST_PSEUDO_REGISTER) 1891 ((TARGET_SHMEDIA ? GENERAL_REGISTER_P (REGNO (X)) \
2211 1892 : REGNO (X) == R0_REG) \
2212 /* Nonzero if X is a hard reg that can be used as an index 1893 || (!STRICT && REGNO (X) >= FIRST_PSEUDO_REGISTER))
2213 or if it is a pseudo reg. */ 1894
2214 #define REG_OK_FOR_INDEX_P(X) \ 1895 /* Nonzero if X/OFFSET is a reg that can be used as an index. */
2215 ((TARGET_SHMEDIA ? GENERAL_REGISTER_P (REGNO (X)) \ 1896 #define SUBREG_OK_FOR_INDEX_P(X, OFFSET, STRICT) \
2216 : REGNO (X) == R0_REG) || REGNO (X) >= FIRST_PSEUDO_REGISTER) 1897 ((TARGET_SHMEDIA ? GENERAL_REGISTER_P (REGNO (X)) \
2217 1898 : REGNO (X) == R0_REG && OFFSET == 0) \
2218 /* Nonzero if X/OFFSET is a hard reg that can be used as an index 1899 || (!STRICT && REGNO (X) >= FIRST_PSEUDO_REGISTER))
2219 or if X is a pseudo reg. */
2220 #define SUBREG_OK_FOR_INDEX_P(X, OFFSET) \
2221 ((TARGET_SHMEDIA ? GENERAL_REGISTER_P (REGNO (X)) \
2222 : REGNO (X) == R0_REG && OFFSET == 0) || REGNO (X) >= FIRST_PSEUDO_REGISTER)
2223
2224 #else
2225
2226 /* Nonzero if X is a hard reg that can be used as a base reg. */
2227 #define REG_OK_FOR_BASE_P(X) \
2228 REGNO_OK_FOR_BASE_P (REGNO (X))
2229
2230 /* Nonzero if X is a hard reg that can be used as an index. */
2231 #define REG_OK_FOR_INDEX_P(X) \
2232 REGNO_OK_FOR_INDEX_P (REGNO (X))
2233
2234 /* Nonzero if X/OFFSET is a hard reg that can be used as an index. */
2235 #define SUBREG_OK_FOR_INDEX_P(X, OFFSET) \
2236 (REGNO_OK_FOR_INDEX_P (REGNO (X)) && (OFFSET) == 0)
2237
2238 #endif
2239 1900
2240 /* Macros for extra constraints. */ 1901 /* Macros for extra constraints. */
2241 1902
2242 #define IS_PC_RELATIVE_LOAD_ADDR_P(OP) \ 1903 #define IS_PC_RELATIVE_LOAD_ADDR_P(OP) \
2243 ((GET_CODE ((OP)) == LABEL_REF) \ 1904 ((GET_CODE ((OP)) == LABEL_REF) \
2244 || (GET_CODE ((OP)) == CONST \ 1905 || (GET_CODE ((OP)) == CONST \
2245 && GET_CODE (XEXP ((OP), 0)) == PLUS \ 1906 && GET_CODE (XEXP ((OP), 0)) == PLUS \
2246 && GET_CODE (XEXP (XEXP ((OP), 0), 0)) == LABEL_REF \ 1907 && GET_CODE (XEXP (XEXP ((OP), 0), 0)) == LABEL_REF \
2247 && GET_CODE (XEXP (XEXP ((OP), 0), 1)) == CONST_INT)) 1908 && CONST_INT_P (XEXP (XEXP ((OP), 0), 1))))
2248 1909
2249 #define IS_NON_EXPLICIT_CONSTANT_P(OP) \ 1910 #define IS_NON_EXPLICIT_CONSTANT_P(OP) \
2250 (CONSTANT_P (OP) \ 1911 (CONSTANT_P (OP) \
2251 && GET_CODE (OP) != CONST_INT \ 1912 && !CONST_INT_P (OP) \
2252 && GET_CODE (OP) != CONST_DOUBLE \ 1913 && GET_CODE (OP) != CONST_DOUBLE \
2253 && (!flag_pic \ 1914 && (!flag_pic \
2254 || (LEGITIMATE_PIC_OPERAND_P (OP) \ 1915 || (LEGITIMATE_PIC_OPERAND_P (OP) \
2255 && !PIC_ADDR_P (OP) \ 1916 && !PIC_ADDR_P (OP) \
2256 && GET_CODE (OP) != LABEL_REF))) 1917 && GET_CODE (OP) != LABEL_REF)))
2276 #define GOTOFF_P(OP) \ 1937 #define GOTOFF_P(OP) \
2277 (GET_CODE (OP) == CONST \ 1938 (GET_CODE (OP) == CONST \
2278 && (UNSPEC_GOTOFF_P (XEXP ((OP), 0)) \ 1939 && (UNSPEC_GOTOFF_P (XEXP ((OP), 0)) \
2279 || (GET_CODE (XEXP ((OP), 0)) == PLUS \ 1940 || (GET_CODE (XEXP ((OP), 0)) == PLUS \
2280 && UNSPEC_GOTOFF_P (XEXP (XEXP ((OP), 0), 0)) \ 1941 && UNSPEC_GOTOFF_P (XEXP (XEXP ((OP), 0), 0)) \
2281 && GET_CODE (XEXP (XEXP ((OP), 0), 1)) == CONST_INT))) 1942 && CONST_INT_P (XEXP (XEXP ((OP), 0), 1)))))
2282 1943
2283 #define PIC_ADDR_P(OP) \ 1944 #define PIC_ADDR_P(OP) \
2284 (GET_CODE (OP) == CONST && GET_CODE (XEXP ((OP), 0)) == UNSPEC \ 1945 (GET_CODE (OP) == CONST && GET_CODE (XEXP ((OP), 0)) == UNSPEC \
2285 && XINT (XEXP ((OP), 0), 1) == UNSPEC_PIC) 1946 && XINT (XEXP ((OP), 0), 1) == UNSPEC_PIC)
2286 1947
2297 || DATALABEL_REF_NO_CONST_P (XEXP ((OP), 0)))) \ 1958 || DATALABEL_REF_NO_CONST_P (XEXP ((OP), 0)))) \
2298 || (GET_CODE (OP) == CONST && GET_CODE (XEXP ((OP), 0)) == PLUS \ 1959 || (GET_CODE (OP) == CONST && GET_CODE (XEXP ((OP), 0)) == PLUS \
2299 && (GET_CODE (XEXP (XEXP ((OP), 0), 0)) == SYMBOL_REF \ 1960 && (GET_CODE (XEXP (XEXP ((OP), 0), 0)) == SYMBOL_REF \
2300 || GET_CODE (XEXP (XEXP ((OP), 0), 0)) == LABEL_REF \ 1961 || GET_CODE (XEXP (XEXP ((OP), 0), 0)) == LABEL_REF \
2301 || DATALABEL_REF_NO_CONST_P (XEXP (XEXP ((OP), 0), 0))) \ 1962 || DATALABEL_REF_NO_CONST_P (XEXP (XEXP ((OP), 0), 0))) \
2302 && GET_CODE (XEXP (XEXP ((OP), 0), 1)) == CONST_INT)) 1963 && CONST_INT_P (XEXP (XEXP ((OP), 0), 1))))
2303 1964
2304 #define PIC_REFERENCE_P(OP) \ 1965 #define PIC_REFERENCE_P(OP) \
2305 (GOT_ENTRY_P (OP) || GOTPLT_ENTRY_P (OP) \ 1966 (GOT_ENTRY_P (OP) || GOTPLT_ENTRY_P (OP) \
2306 || GOTOFF_P (OP) || PIC_ADDR_P (OP)) 1967 || GOTOFF_P (OP) || PIC_ADDR_P (OP))
2307 1968
2309 (flag_pic \ 1970 (flag_pic \
2310 ? (GOT_ENTRY_P (OP) || GOTPLT_ENTRY_P (OP) || GOTOFF_P (OP) \ 1971 ? (GOT_ENTRY_P (OP) || GOTPLT_ENTRY_P (OP) || GOTOFF_P (OP) \
2311 || PCREL_SYMOFF_P (OP)) \ 1972 || PCREL_SYMOFF_P (OP)) \
2312 : NON_PIC_REFERENCE_P (OP)) 1973 : NON_PIC_REFERENCE_P (OP))
2313 1974
2314 /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression 1975 #define MAYBE_BASE_REGISTER_RTX_P(X, STRICT) \
2315 that is a valid memory address for an instruction. 1976 ((REG_P (X) && REG_OK_FOR_BASE_P (X, STRICT)) \
2316 The MODE argument is the machine mode for the MEM expression 1977 || (GET_CODE (X) == SUBREG \
2317 that wants to use this address. */ 1978 && TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (GET_MODE ((X))), \
2318
2319 #define MODE_DISP_OK_4(X,MODE) \
2320 (GET_MODE_SIZE (MODE) == 4 && (unsigned) INTVAL (X) < 64 \
2321 && ! (INTVAL (X) & 3) && ! (TARGET_SH2E && (MODE) == SFmode))
2322
2323 #define MODE_DISP_OK_8(X,MODE) \
2324 ((GET_MODE_SIZE(MODE)==8) && ((unsigned)INTVAL(X)<60) \
2325 && ! (INTVAL(X) & 3) && ! (TARGET_SH4 && (MODE) == DFmode))
2326
2327 #undef MODE_DISP_OK_4
2328 #define MODE_DISP_OK_4(X,MODE) \
2329 ((GET_MODE_SIZE (MODE) == 4 && (unsigned) INTVAL (X) < 64 \
2330 && ! (INTVAL (X) & 3) && ! (TARGET_SH2E && (MODE) == SFmode)) \
2331 || ((GET_MODE_SIZE(MODE)==4) && ((unsigned)INTVAL(X)<16383) \
2332 && ! (INTVAL(X) & 3) && TARGET_SH2A))
2333
2334 #undef MODE_DISP_OK_8
2335 #define MODE_DISP_OK_8(X,MODE) \
2336 (((GET_MODE_SIZE(MODE)==8) && ((unsigned)INTVAL(X)<60) \
2337 && ! (INTVAL(X) & 3) && ! ((TARGET_SH4 || TARGET_SH2A) && (MODE) == DFmode)) \
2338 || ((GET_MODE_SIZE(MODE)==8) && ((unsigned)INTVAL(X)<8192) \
2339 && ! (INTVAL(X) & (TARGET_SH2A_DOUBLE ? 7 : 3)) && (TARGET_SH2A && (MODE) == DFmode)))
2340
2341 #define BASE_REGISTER_RTX_P(X) \
2342 ((GET_CODE (X) == REG && REG_OK_FOR_BASE_P (X)) \
2343 || (GET_CODE (X) == SUBREG \
2344 && TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (GET_MODE ((X))), \
2345 GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (X)))) \ 1979 GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (X)))) \
2346 && GET_CODE (SUBREG_REG (X)) == REG \ 1980 && REG_P (SUBREG_REG (X)) \
2347 && REG_OK_FOR_BASE_P (SUBREG_REG (X)))) 1981 && REG_OK_FOR_BASE_P (SUBREG_REG (X), STRICT)))
2348 1982
2349 /* Since this must be r0, which is a single register class, we must check 1983 /* Since this must be r0, which is a single register class, we must check
2350 SUBREGs more carefully, to be sure that we don't accept one that extends 1984 SUBREGs more carefully, to be sure that we don't accept one that extends
2351 outside the class. */ 1985 outside the class. */
2352 #define INDEX_REGISTER_RTX_P(X) \ 1986 #define MAYBE_INDEX_REGISTER_RTX_P(X, STRICT) \
2353 ((GET_CODE (X) == REG && REG_OK_FOR_INDEX_P (X)) \ 1987 ((REG_P (X) && REG_OK_FOR_INDEX_P (X, STRICT)) \
2354 || (GET_CODE (X) == SUBREG \ 1988 || (GET_CODE (X) == SUBREG \
2355 && TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (GET_MODE ((X))), \ 1989 && TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (GET_MODE ((X))), \
2356 GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (X)))) \ 1990 GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (X)))) \
2357 && GET_CODE (SUBREG_REG (X)) == REG \ 1991 && REG_P (SUBREG_REG (X)) \
2358 && SUBREG_OK_FOR_INDEX_P (SUBREG_REG (X), SUBREG_BYTE (X)))) 1992 && SUBREG_OK_FOR_INDEX_P (SUBREG_REG (X), SUBREG_BYTE (X), STRICT)))
2359 1993
2360 /* Jump to LABEL if X is a valid address RTX. This must also take 1994 #ifdef REG_OK_STRICT
2361 REG_OK_STRICT into account when deciding about valid registers, but it uses 1995 #define BASE_REGISTER_RTX_P(X) MAYBE_BASE_REGISTER_RTX_P(X, true)
2362 the above macros so we are in luck. 1996 #define INDEX_REGISTER_RTX_P(X) MAYBE_INDEX_REGISTER_RTX_P(X, true)
2363 1997 #else
2364 Allow REG 1998 #define BASE_REGISTER_RTX_P(X) MAYBE_BASE_REGISTER_RTX_P(X, false)
2365 REG+disp 1999 #define INDEX_REGISTER_RTX_P(X) MAYBE_INDEX_REGISTER_RTX_P(X, false)
2366 REG+r0 2000 #endif
2367 REG++
2368 --REG */
2369
2370 /* ??? The SH2e does not have the REG+disp addressing mode when loading values
2371 into the FRx registers. We implement this by setting the maximum offset
2372 to zero when the value is SFmode. This also restricts loading of SFmode
2373 values into the integer registers, but that can't be helped. */
2374
2375 /* The SH allows a displacement in a QI or HI amode, but only when the
2376 other operand is R0. GCC doesn't handle this very well, so we forgo
2377 all of that.
2378
2379 A legitimate index for a QI or HI is 0, SI can be any number 0..63,
2380 DI can be any number 0..60. */
2381
2382 #define GO_IF_LEGITIMATE_INDEX(MODE, OP, LABEL) \
2383 do { \
2384 if (GET_CODE (OP) == CONST_INT) \
2385 { \
2386 if (TARGET_SHMEDIA) \
2387 { \
2388 int MODE_SIZE; \
2389 /* Check if this the address of an unaligned load / store. */\
2390 if ((MODE) == VOIDmode) \
2391 { \
2392 if (CONST_OK_FOR_I06 (INTVAL (OP))) \
2393 goto LABEL; \
2394 break; \
2395 } \
2396 MODE_SIZE = GET_MODE_SIZE (MODE); \
2397 if (! (INTVAL (OP) & (MODE_SIZE - 1)) \
2398 && INTVAL (OP) >= -512 * MODE_SIZE \
2399 && INTVAL (OP) < 512 * MODE_SIZE) \
2400 goto LABEL; \
2401 else \
2402 break; \
2403 } \
2404 if (TARGET_SH2A) \
2405 { \
2406 if (GET_MODE_SIZE (MODE) == 1 \
2407 && (unsigned) INTVAL (OP) < 4096) \
2408 goto LABEL; \
2409 } \
2410 if (MODE_DISP_OK_4 ((OP), (MODE))) goto LABEL; \
2411 if (MODE_DISP_OK_8 ((OP), (MODE))) goto LABEL; \
2412 } \
2413 } while(0)
2414 2001
2415 #define ALLOW_INDEXED_ADDRESS \ 2002 #define ALLOW_INDEXED_ADDRESS \
2416 ((!TARGET_SHMEDIA32 && !TARGET_SHCOMPACT) || TARGET_ALLOW_INDEXED_ADDRESS) 2003 ((!TARGET_SHMEDIA32 && !TARGET_SHCOMPACT) || TARGET_ALLOW_INDEXED_ADDRESS)
2417 2004
2418 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, LABEL) \ 2005 #define GO_IF_LEGITIMATE_INDEX(MODE, OP, WIN) \
2419 { \ 2006 do { \
2420 if (BASE_REGISTER_RTX_P (X)) \ 2007 if (sh_legitimate_index_p ((MODE), (OP))) \
2421 goto LABEL; \ 2008 goto WIN; \
2422 else if ((GET_CODE (X) == POST_INC || GET_CODE (X) == PRE_DEC) \ 2009 } while (0)
2423 && ! TARGET_SHMEDIA \
2424 && BASE_REGISTER_RTX_P (XEXP ((X), 0))) \
2425 goto LABEL; \
2426 else if (GET_CODE (X) == PLUS \
2427 && ((MODE) != PSImode || reload_completed)) \
2428 { \
2429 rtx xop0 = XEXP ((X), 0); \
2430 rtx xop1 = XEXP ((X), 1); \
2431 if (GET_MODE_SIZE (MODE) <= 8 && BASE_REGISTER_RTX_P (xop0)) \
2432 GO_IF_LEGITIMATE_INDEX ((MODE), xop1, LABEL); \
2433 if ((ALLOW_INDEXED_ADDRESS || GET_MODE (X) == DImode \
2434 || ((xop0 == stack_pointer_rtx \
2435 || xop0 == hard_frame_pointer_rtx) \
2436 && REG_P (xop1) && REGNO (xop1) == R0_REG) \
2437 || ((xop1 == stack_pointer_rtx \
2438 || xop1 == hard_frame_pointer_rtx) \
2439 && REG_P (xop0) && REGNO (xop0) == R0_REG)) \
2440 && ((!TARGET_SHMEDIA && GET_MODE_SIZE (MODE) <= 4) \
2441 || (TARGET_SHMEDIA && GET_MODE_SIZE (MODE) <= 8) \
2442 || ((TARGET_SH4 || TARGET_SH2A_DOUBLE) \
2443 && TARGET_FMOVD && MODE == DFmode))) \
2444 { \
2445 if (BASE_REGISTER_RTX_P (xop1) && INDEX_REGISTER_RTX_P (xop0))\
2446 goto LABEL; \
2447 if (INDEX_REGISTER_RTX_P (xop1) && BASE_REGISTER_RTX_P (xop0))\
2448 goto LABEL; \
2449 } \
2450 } \
2451 }
2452 2010
2453 /* Try machine-dependent ways of modifying an illegitimate address
2454 to be legitimate. If we find one, return the new, valid address.
2455 This macro is used in only one place: `memory_address' in explow.c.
2456
2457 OLDX is the address as it was before break_out_memory_refs was called.
2458 In some cases it is useful to look at this to decide what needs to be done.
2459
2460 MODE and WIN are passed so that this macro can use
2461 GO_IF_LEGITIMATE_ADDRESS.
2462
2463 It is always safe for this macro to do nothing. It exists to recognize
2464 opportunities to optimize the output.
2465
2466 For the SH, if X is almost suitable for indexing, but the offset is
2467 out of range, convert it into a normal form so that cse has a chance
2468 of reducing the number of address registers used. */
2469
2470 #define LEGITIMIZE_ADDRESS(X,OLDX,MODE,WIN) \
2471 { \
2472 if (flag_pic) \
2473 (X) = legitimize_pic_address (OLDX, MODE, NULL_RTX); \
2474 if (GET_CODE (X) == PLUS \
2475 && (GET_MODE_SIZE (MODE) == 4 \
2476 || GET_MODE_SIZE (MODE) == 8) \
2477 && GET_CODE (XEXP ((X), 1)) == CONST_INT \
2478 && BASE_REGISTER_RTX_P (XEXP ((X), 0)) \
2479 && ! TARGET_SHMEDIA \
2480 && ! ((TARGET_SH4 || TARGET_SH2A_DOUBLE) && (MODE) == DFmode) \
2481 && ! (TARGET_SH2E && (MODE) == SFmode)) \
2482 { \
2483 rtx index_rtx = XEXP ((X), 1); \
2484 HOST_WIDE_INT offset = INTVAL (index_rtx), offset_base; \
2485 rtx sum; \
2486 \
2487 GO_IF_LEGITIMATE_INDEX ((MODE), index_rtx, WIN); \
2488 /* On rare occasions, we might get an unaligned pointer \
2489 that is indexed in a way to give an aligned address. \
2490 Therefore, keep the lower two bits in offset_base. */ \
2491 /* Instead of offset_base 128..131 use 124..127, so that \
2492 simple add suffices. */ \
2493 if (offset > 127) \
2494 { \
2495 offset_base = ((offset + 4) & ~60) - 4; \
2496 } \
2497 else \
2498 offset_base = offset & ~60; \
2499 /* Sometimes the normal form does not suit DImode. We \
2500 could avoid that by using smaller ranges, but that \
2501 would give less optimized code when SImode is \
2502 prevalent. */ \
2503 if (GET_MODE_SIZE (MODE) + offset - offset_base <= 64) \
2504 { \
2505 sum = expand_binop (Pmode, add_optab, XEXP ((X), 0), \
2506 GEN_INT (offset_base), NULL_RTX, 0, \
2507 OPTAB_LIB_WIDEN); \
2508 \
2509 (X) = gen_rtx_PLUS (Pmode, sum, GEN_INT (offset - offset_base)); \
2510 goto WIN; \
2511 } \
2512 } \
2513 }
2514
2515 /* A C compound statement that attempts to replace X, which is an address 2011 /* A C compound statement that attempts to replace X, which is an address
2516 that needs reloading, with a valid memory address for an operand of 2012 that needs reloading, with a valid memory address for an operand of
2517 mode MODE. WIN is a C statement label elsewhere in the code. 2013 mode MODE. WIN is a C statement label elsewhere in the code.
2518 2014
2519 Like for LEGITIMIZE_ADDRESS, for the SH we try to get a normal form 2015 Like for LEGITIMIZE_ADDRESS, for the SH we try to get a normal form
2521 2017
2522 #define LEGITIMIZE_RELOAD_ADDRESS(X,MODE,OPNUM,TYPE,IND_LEVELS,WIN) \ 2018 #define LEGITIMIZE_RELOAD_ADDRESS(X,MODE,OPNUM,TYPE,IND_LEVELS,WIN) \
2523 { \ 2019 { \
2524 if (GET_CODE (X) == PLUS \ 2020 if (GET_CODE (X) == PLUS \
2525 && (GET_MODE_SIZE (MODE) == 4 || GET_MODE_SIZE (MODE) == 8) \ 2021 && (GET_MODE_SIZE (MODE) == 4 || GET_MODE_SIZE (MODE) == 8) \
2526 && GET_CODE (XEXP (X, 1)) == CONST_INT \ 2022 && CONST_INT_P (XEXP (X, 1)) \
2527 && BASE_REGISTER_RTX_P (XEXP (X, 0)) \ 2023 && BASE_REGISTER_RTX_P (XEXP (X, 0)) \
2528 && ! TARGET_SHMEDIA \ 2024 && ! TARGET_SHMEDIA \
2529 && ! (TARGET_SH4 && (MODE) == DFmode) \ 2025 && ! (TARGET_SH4 && (MODE) == DFmode) \
2530 && ! ((MODE) == PSImode && (TYPE) == RELOAD_FOR_INPUT_ADDRESS) \ 2026 && ! ((MODE) == PSImode && (TYPE) == RELOAD_FOR_INPUT_ADDRESS) \
2531 && (ALLOW_INDEXED_ADDRESS \ 2027 && (ALLOW_INDEXED_ADDRESS \
2576 } \ 2072 } \
2577 /* We must re-recognize what we created before. */ \ 2073 /* We must re-recognize what we created before. */ \
2578 else if (GET_CODE (X) == PLUS \ 2074 else if (GET_CODE (X) == PLUS \
2579 && (GET_MODE_SIZE (MODE) == 4 || GET_MODE_SIZE (MODE) == 8) \ 2075 && (GET_MODE_SIZE (MODE) == 4 || GET_MODE_SIZE (MODE) == 8) \
2580 && GET_CODE (XEXP (X, 0)) == PLUS \ 2076 && GET_CODE (XEXP (X, 0)) == PLUS \
2581 && GET_CODE (XEXP (XEXP (X, 0), 1)) == CONST_INT \ 2077 && CONST_INT_P (XEXP (XEXP (X, 0), 1)) \
2582 && BASE_REGISTER_RTX_P (XEXP (XEXP (X, 0), 0)) \ 2078 && BASE_REGISTER_RTX_P (XEXP (XEXP (X, 0), 0)) \
2583 && GET_CODE (XEXP (X, 1)) == CONST_INT \ 2079 && CONST_INT_P (XEXP (X, 1)) \
2584 && ! TARGET_SHMEDIA \ 2080 && ! TARGET_SHMEDIA \
2585 && ! (TARGET_SH2E && MODE == SFmode)) \ 2081 && ! (TARGET_SH2E && MODE == SFmode)) \
2586 { \ 2082 { \
2587 /* Because this address is so complex, we know it must have \ 2083 /* Because this address is so complex, we know it must have \
2588 been created by LEGITIMIZE_RELOAD_ADDRESS before; thus, \ 2084 been created by LEGITIMIZE_RELOAD_ADDRESS before; thus, \
2590 push_reload (XEXP ((X), 0), NULL_RTX, &XEXP ((X), 0), NULL, \ 2086 push_reload (XEXP ((X), 0), NULL_RTX, &XEXP ((X), 0), NULL, \
2591 BASE_REG_CLASS, Pmode, VOIDmode, 0, 0, (OPNUM), (TYPE));\ 2087 BASE_REG_CLASS, Pmode, VOIDmode, 0, 0, (OPNUM), (TYPE));\
2592 goto WIN; \ 2088 goto WIN; \
2593 } \ 2089 } \
2594 } 2090 }
2595
2596 /* Go to LABEL if ADDR (a legitimate address expression)
2597 has an effect that depends on the machine mode it is used for.
2598
2599 ??? Strictly speaking, we should also include all indexed addressing,
2600 because the index scale factor is the length of the operand.
2601 However, the impact of GO_IF_MODE_DEPENDENT_ADDRESS would be to
2602 high if we did that. So we rely on reload to fix things up.
2603
2604 Auto-increment addressing is now treated in recog.c. */
2605
2606 #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL)
2607 2091
2608 /* Specify the machine mode that this machine uses 2092 /* Specify the machine mode that this machine uses
2609 for the index in the tablejump instruction. */ 2093 for the index in the tablejump instruction. */
2610 #define CASE_VECTOR_MODE ((! optimize || TARGET_BIGTABLE) ? SImode : HImode) 2094 #define CASE_VECTOR_MODE ((! optimize || TARGET_BIGTABLE) ? SImode : HImode)
2611 2095
2628 2112
2629 /* Since the SH2e has only `float' support, it is desirable to make all 2113 /* Since the SH2e has only `float' support, it is desirable to make all
2630 floating point types equivalent to `float'. */ 2114 floating point types equivalent to `float'. */
2631 #define DOUBLE_TYPE_SIZE ((TARGET_SH2E && ! TARGET_SH4 && ! TARGET_SH2A_DOUBLE) ? 32 : 64) 2115 #define DOUBLE_TYPE_SIZE ((TARGET_SH2E && ! TARGET_SH4 && ! TARGET_SH2A_DOUBLE) ? 32 : 64)
2632 2116
2633 #if defined(__SH2E__) || defined(__SH3E__) || defined( __SH4_SINGLE_ONLY__) 2117 #if defined(__SH2E__) || defined(__SH3E__) || defined( __SH2A_SINGLE_ONLY__) || defined( __SH4_SINGLE_ONLY__)
2634 #define LIBGCC2_DOUBLE_TYPE_SIZE 32 2118 #define LIBGCC2_DOUBLE_TYPE_SIZE 32
2635 #else 2119 #else
2636 #define LIBGCC2_DOUBLE_TYPE_SIZE 64 2120 #define LIBGCC2_DOUBLE_TYPE_SIZE 64
2637 #endif 2121 #endif
2638 2122
2722 get_attr_is_sfunc will try to recognize the given insn, so make sure to 2206 get_attr_is_sfunc will try to recognize the given insn, so make sure to
2723 filter out things it will not accept -- SEQUENCE, USE and CLOBBER insns 2207 filter out things it will not accept -- SEQUENCE, USE and CLOBBER insns
2724 in particular. */ 2208 in particular. */
2725 2209
2726 #define INSN_SETS_ARE_DELAYED(X) \ 2210 #define INSN_SETS_ARE_DELAYED(X) \
2727 ((GET_CODE (X) == INSN \ 2211 ((NONJUMP_INSN_P (X) \
2728 && GET_CODE (PATTERN (X)) != SEQUENCE \ 2212 && GET_CODE (PATTERN (X)) != SEQUENCE \
2729 && GET_CODE (PATTERN (X)) != USE \ 2213 && GET_CODE (PATTERN (X)) != USE \
2730 && GET_CODE (PATTERN (X)) != CLOBBER \ 2214 && GET_CODE (PATTERN (X)) != CLOBBER \
2731 && get_attr_is_sfunc (X))) 2215 && get_attr_is_sfunc (X)))
2732 2216
2733 #define INSN_REFERENCES_ARE_DELAYED(X) \ 2217 #define INSN_REFERENCES_ARE_DELAYED(X) \
2734 ((GET_CODE (X) == INSN \ 2218 ((NONJUMP_INSN_P (X) \
2735 && GET_CODE (PATTERN (X)) != SEQUENCE \ 2219 && GET_CODE (PATTERN (X)) != SEQUENCE \
2736 && GET_CODE (PATTERN (X)) != USE \ 2220 && GET_CODE (PATTERN (X)) != USE \
2737 && GET_CODE (PATTERN (X)) != CLOBBER \ 2221 && GET_CODE (PATTERN (X)) != CLOBBER \
2738 && get_attr_is_sfunc (X))) 2222 && get_attr_is_sfunc (X)))
2739 2223