Mercurial > hg > CbC > CbC_gcc
annotate gcc/config/sh/sh.h @ 55:77e2b8dfacca gcc-4.4.5
update it from 4.4.3 to 4.5.0
| author | ryoma <e075725@ie.u-ryukyu.ac.jp> |
|---|---|
| date | Fri, 12 Feb 2010 23:39:51 +0900 |
| parents | a06113de4d67 |
| children | b7f97abdc517 |
| rev | line source |
|---|---|
| 0 | 1 /* Definitions of target machine for GNU compiler for Renesas / SuperH SH. |
| 2 Copyright (C) 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, | |
|
55
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
3 2003, 2004, 2005, 2006, 2007, 2008, 2009 Free Software Foundation, Inc. |
| 0 | 4 Contributed by Steve Chamberlain (sac@cygnus.com). |
| 5 Improved by Jim Wilson (wilson@cygnus.com). | |
| 6 | |
| 7 This file is part of GCC. | |
| 8 | |
| 9 GCC is free software; you can redistribute it and/or modify | |
| 10 it under the terms of the GNU General Public License as published by | |
| 11 the Free Software Foundation; either version 3, or (at your option) | |
| 12 any later version. | |
| 13 | |
| 14 GCC is distributed in the hope that it will be useful, | |
| 15 but WITHOUT ANY WARRANTY; without even the implied warranty of | |
| 16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
| 17 GNU General Public License for more details. | |
| 18 | |
| 19 You should have received a copy of the GNU General Public License | |
| 20 along with GCC; see the file COPYING3. If not see | |
| 21 <http://www.gnu.org/licenses/>. */ | |
| 22 | |
| 23 #ifndef GCC_SH_H | |
| 24 #define GCC_SH_H | |
| 25 | |
| 26 #include "config/vxworks-dummy.h" | |
| 27 | |
| 28 #define TARGET_VERSION \ | |
| 29 fputs (" (Hitachi SH)", stderr); | |
| 30 | |
| 31 /* Unfortunately, insn-attrtab.c doesn't include insn-codes.h. We can't | |
| 32 include it here, because bconfig.h is also included by gencodes.c . */ | |
| 33 /* ??? No longer true. */ | |
| 34 extern int code_for_indirect_jump_scratch; | |
| 35 | |
| 36 #define TARGET_CPU_CPP_BUILTINS() \ | |
| 37 do { \ | |
| 38 builtin_define ("__sh__"); \ | |
| 39 builtin_assert ("cpu=sh"); \ | |
| 40 builtin_assert ("machine=sh"); \ | |
| 41 switch ((int) sh_cpu) \ | |
| 42 { \ | |
| 43 case PROCESSOR_SH1: \ | |
| 44 builtin_define ("__sh1__"); \ | |
| 45 break; \ | |
| 46 case PROCESSOR_SH2: \ | |
| 47 builtin_define ("__sh2__"); \ | |
| 48 break; \ | |
| 49 case PROCESSOR_SH2E: \ | |
| 50 builtin_define ("__SH2E__"); \ | |
| 51 break; \ | |
| 52 case PROCESSOR_SH2A: \ | |
| 53 builtin_define ("__SH2A__"); \ | |
| 54 builtin_define (TARGET_SH2A_DOUBLE \ | |
| 55 ? (TARGET_FPU_SINGLE ? "__SH2A_SINGLE__" : "__SH2A_DOUBLE__") \ | |
| 56 : TARGET_FPU_ANY ? "__SH2A_SINGLE_ONLY__" \ | |
| 57 : "__SH2A_NOFPU__"); \ | |
| 58 break; \ | |
| 59 case PROCESSOR_SH3: \ | |
| 60 builtin_define ("__sh3__"); \ | |
| 61 builtin_define ("__SH3__"); \ | |
| 62 if (TARGET_HARD_SH4) \ | |
| 63 builtin_define ("__SH4_NOFPU__"); \ | |
| 64 break; \ | |
| 65 case PROCESSOR_SH3E: \ | |
| 66 builtin_define (TARGET_HARD_SH4 ? "__SH4_SINGLE_ONLY__" : "__SH3E__"); \ | |
| 67 break; \ | |
| 68 case PROCESSOR_SH4: \ | |
| 69 builtin_define (TARGET_FPU_SINGLE ? "__SH4_SINGLE__" : "__SH4__"); \ | |
| 70 break; \ | |
| 71 case PROCESSOR_SH4A: \ | |
| 72 builtin_define ("__SH4A__"); \ | |
| 73 builtin_define (TARGET_SH4 \ | |
| 74 ? (TARGET_FPU_SINGLE ? "__SH4_SINGLE__" : "__SH4__") \ | |
| 75 : TARGET_FPU_ANY ? "__SH4_SINGLE_ONLY__" \ | |
| 76 : "__SH4_NOFPU__"); \ | |
| 77 break; \ | |
| 78 case PROCESSOR_SH5: \ | |
| 79 { \ | |
| 80 builtin_define_with_value ("__SH5__", \ | |
| 81 TARGET_SHMEDIA64 ? "64" : "32", 0); \ | |
| 82 builtin_define_with_value ("__SHMEDIA__", \ | |
| 83 TARGET_SHMEDIA ? "1" : "0", 0); \ | |
| 84 if (! TARGET_FPU_DOUBLE) \ | |
| 85 builtin_define ("__SH4_NOFPU__"); \ | |
| 86 } \ | |
| 87 } \ | |
| 88 if (TARGET_FPU_ANY) \ | |
| 89 builtin_define ("__SH_FPU_ANY__"); \ | |
| 90 if (TARGET_FPU_DOUBLE) \ | |
| 91 builtin_define ("__SH_FPU_DOUBLE__"); \ | |
| 92 if (TARGET_HITACHI) \ | |
| 93 builtin_define ("__HITACHI__"); \ | |
|
55
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
94 if (TARGET_FMOVD) \ |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
95 builtin_define ("__FMOVD_ENABLED__"); \ |
| 0 | 96 builtin_define (TARGET_LITTLE_ENDIAN \ |
| 97 ? "__LITTLE_ENDIAN__" : "__BIG_ENDIAN__"); \ | |
| 98 } while (0) | |
| 99 | |
| 100 /* We can not debug without a frame pointer. */ | |
| 101 /* #define CAN_DEBUG_WITHOUT_FP */ | |
| 102 | |
| 103 #define CONDITIONAL_REGISTER_USAGE do \ | |
| 104 { \ | |
| 105 int regno; \ | |
| 106 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno ++) \ | |
| 107 if (! VALID_REGISTER_P (regno)) \ | |
| 108 fixed_regs[regno] = call_used_regs[regno] = 1; \ | |
| 109 /* R8 and R9 are call-clobbered on SH5, but not on earlier SH ABIs. */ \ | |
| 110 if (TARGET_SH5) \ | |
| 111 { \ | |
| 112 call_used_regs[FIRST_GENERAL_REG + 8] \ | |
| 113 = call_used_regs[FIRST_GENERAL_REG + 9] = 1; \ | |
| 114 call_really_used_regs[FIRST_GENERAL_REG + 8] \ | |
| 115 = call_really_used_regs[FIRST_GENERAL_REG + 9] = 1; \ | |
| 116 } \ | |
| 117 if (TARGET_SHMEDIA) \ | |
| 118 { \ | |
| 119 regno_reg_class[FIRST_GENERAL_REG] = GENERAL_REGS; \ | |
| 120 CLEAR_HARD_REG_SET (reg_class_contents[FP0_REGS]); \ | |
| 121 regno_reg_class[FIRST_FP_REG] = FP_REGS; \ | |
| 122 } \ | |
| 123 if (flag_pic) \ | |
| 124 { \ | |
| 125 fixed_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \ | |
| 126 call_used_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \ | |
| 127 } \ | |
| 128 /* Renesas saves and restores mac registers on call. */ \ | |
| 129 if (TARGET_HITACHI && ! TARGET_NOMACSAVE) \ | |
| 130 { \ | |
| 131 call_really_used_regs[MACH_REG] = 0; \ | |
| 132 call_really_used_regs[MACL_REG] = 0; \ | |
| 133 } \ | |
| 134 for (regno = FIRST_FP_REG + (TARGET_LITTLE_ENDIAN != 0); \ | |
| 135 regno <= LAST_FP_REG; regno += 2) \ | |
| 136 SET_HARD_REG_BIT (reg_class_contents[DF_HI_REGS], regno); \ | |
| 137 if (TARGET_SHMEDIA) \ | |
| 138 { \ | |
| 139 for (regno = FIRST_TARGET_REG; regno <= LAST_TARGET_REG; regno ++)\ | |
| 140 if (! fixed_regs[regno] && call_really_used_regs[regno]) \ | |
| 141 SET_HARD_REG_BIT (reg_class_contents[SIBCALL_REGS], regno); \ | |
| 142 } \ | |
| 143 else \ | |
| 144 for (regno = FIRST_GENERAL_REG; regno <= LAST_GENERAL_REG; regno++) \ | |
| 145 if (! fixed_regs[regno] && call_really_used_regs[regno]) \ | |
| 146 SET_HARD_REG_BIT (reg_class_contents[SIBCALL_REGS], regno); \ | |
| 147 } while (0) | |
| 148 | |
| 149 /* Nonzero if this is an ELF target - compile time only */ | |
| 150 #define TARGET_ELF 0 | |
| 151 | |
| 152 /* Nonzero if we should generate code using type 2E insns. */ | |
| 153 #define TARGET_SH2E (TARGET_SH2 && TARGET_SH_E) | |
| 154 | |
| 155 /* Nonzero if we should generate code using type 2A insns. */ | |
| 156 #define TARGET_SH2A TARGET_HARD_SH2A | |
| 157 /* Nonzero if we should generate code using type 2A SF insns. */ | |
| 158 #define TARGET_SH2A_SINGLE (TARGET_SH2A && TARGET_SH2E) | |
| 159 /* Nonzero if we should generate code using type 2A DF insns. */ | |
| 160 #define TARGET_SH2A_DOUBLE (TARGET_HARD_SH2A_DOUBLE && TARGET_SH2A) | |
| 161 | |
| 162 /* Nonzero if we should generate code using type 3E insns. */ | |
| 163 #define TARGET_SH3E (TARGET_SH3 && TARGET_SH_E) | |
| 164 | |
| 165 /* Nonzero if the cache line size is 32. */ | |
| 166 #define TARGET_CACHE32 (TARGET_HARD_SH4 || TARGET_SH5) | |
| 167 | |
| 168 /* Nonzero if we schedule for a superscalar implementation. */ | |
| 169 #define TARGET_SUPERSCALAR TARGET_HARD_SH4 | |
| 170 | |
| 171 /* Nonzero if the target has separate instruction and data caches. */ | |
| 172 #define TARGET_HARVARD (TARGET_HARD_SH4 || TARGET_SH5) | |
| 173 | |
| 174 /* Nonzero if a double-precision FPU is available. */ | |
| 175 #define TARGET_FPU_DOUBLE \ | |
| 176 ((target_flags & MASK_SH4) != 0 || TARGET_SH2A_DOUBLE) | |
| 177 | |
| 178 /* Nonzero if an FPU is available. */ | |
| 179 #define TARGET_FPU_ANY (TARGET_SH2E || TARGET_FPU_DOUBLE) | |
| 180 | |
| 181 /* Nonzero if we should generate code using type 4 insns. */ | |
| 182 #undef TARGET_SH4 | |
| 183 #define TARGET_SH4 ((target_flags & MASK_SH4) != 0 && TARGET_SH1) | |
| 184 | |
| 185 /* Nonzero if we're generating code for the common subset of | |
| 186 instructions present on both SH4a and SH4al-dsp. */ | |
| 187 #define TARGET_SH4A_ARCH TARGET_SH4A | |
| 188 | |
| 189 /* Nonzero if we're generating code for SH4a, unless the use of the | |
| 190 FPU is disabled (which makes it compatible with SH4al-dsp). */ | |
| 191 #define TARGET_SH4A_FP (TARGET_SH4A_ARCH && TARGET_FPU_ANY) | |
| 192 | |
| 193 /* Nonzero if we should generate code using the SHcompact instruction | |
| 194 set and 32-bit ABI. */ | |
| 195 #define TARGET_SHCOMPACT (TARGET_SH5 && TARGET_SH1) | |
| 196 | |
| 197 /* Nonzero if we should generate code using the SHmedia instruction | |
| 198 set and ABI. */ | |
| 199 #define TARGET_SHMEDIA (TARGET_SH5 && ! TARGET_SH1) | |
| 200 | |
| 201 /* Nonzero if we should generate code using the SHmedia ISA and 32-bit | |
| 202 ABI. */ | |
| 203 #define TARGET_SHMEDIA32 (TARGET_SH5 && ! TARGET_SH1 && TARGET_SH_E) | |
| 204 | |
| 205 /* Nonzero if we should generate code using the SHmedia ISA and 64-bit | |
| 206 ABI. */ | |
| 207 #define TARGET_SHMEDIA64 (TARGET_SH5 && ! TARGET_SH1 && ! TARGET_SH_E) | |
| 208 | |
| 209 /* Nonzero if we should generate code using SHmedia FPU instructions. */ | |
| 210 #define TARGET_SHMEDIA_FPU (TARGET_SHMEDIA && TARGET_FPU_DOUBLE) | |
| 211 | |
| 212 /* This is not used by the SH2E calling convention */ | |
| 213 #define TARGET_VARARGS_PRETEND_ARGS(FUN_DECL) \ | |
| 214 (TARGET_SH1 && ! TARGET_SH2E && ! TARGET_SH5 \ | |
| 215 && ! (TARGET_HITACHI || sh_attr_renesas_p (FUN_DECL))) | |
| 216 | |
| 217 #ifndef TARGET_CPU_DEFAULT | |
| 218 #define TARGET_CPU_DEFAULT SELECT_SH1 | |
| 219 #define SUPPORT_SH1 1 | |
| 220 #define SUPPORT_SH2E 1 | |
| 221 #define SUPPORT_SH4 1 | |
| 222 #define SUPPORT_SH4_SINGLE 1 | |
| 223 #define SUPPORT_SH2A 1 | |
| 224 #define SUPPORT_SH2A_SINGLE 1 | |
| 225 #endif | |
| 226 | |
| 227 #define TARGET_DIVIDE_INV \ | |
| 228 (sh_div_strategy == SH_DIV_INV || sh_div_strategy == SH_DIV_INV_MINLAT \ | |
| 229 || sh_div_strategy == SH_DIV_INV20U || sh_div_strategy == SH_DIV_INV20L \ | |
| 230 || sh_div_strategy == SH_DIV_INV_CALL \ | |
| 231 || sh_div_strategy == SH_DIV_INV_CALL2 || sh_div_strategy == SH_DIV_INV_FP) | |
| 232 #define TARGET_DIVIDE_FP (sh_div_strategy == SH_DIV_FP) | |
| 233 #define TARGET_DIVIDE_INV_FP (sh_div_strategy == SH_DIV_INV_FP) | |
| 234 #define TARGET_DIVIDE_CALL2 (sh_div_strategy == SH_DIV_CALL2) | |
| 235 #define TARGET_DIVIDE_INV_MINLAT (sh_div_strategy == SH_DIV_INV_MINLAT) | |
| 236 #define TARGET_DIVIDE_INV20U (sh_div_strategy == SH_DIV_INV20U) | |
| 237 #define TARGET_DIVIDE_INV20L (sh_div_strategy == SH_DIV_INV20L) | |
| 238 #define TARGET_DIVIDE_INV_CALL (sh_div_strategy == SH_DIV_INV_CALL) | |
| 239 #define TARGET_DIVIDE_INV_CALL2 (sh_div_strategy == SH_DIV_INV_CALL2) | |
| 240 #define TARGET_DIVIDE_CALL_DIV1 (sh_div_strategy == SH_DIV_CALL_DIV1) | |
| 241 #define TARGET_DIVIDE_CALL_FP (sh_div_strategy == SH_DIV_CALL_FP) | |
| 242 #define TARGET_DIVIDE_CALL_TABLE (sh_div_strategy == SH_DIV_CALL_TABLE) | |
| 243 | |
| 244 #define SELECT_SH1 (MASK_SH1) | |
| 245 #define SELECT_SH2 (MASK_SH2 | SELECT_SH1) | |
| 246 #define SELECT_SH2E (MASK_SH_E | MASK_SH2 | MASK_SH1 \ | |
| 247 | MASK_FPU_SINGLE) | |
| 248 #define SELECT_SH2A (MASK_SH_E | MASK_HARD_SH2A \ | |
| 249 | MASK_HARD_SH2A_DOUBLE \ | |
| 250 | MASK_SH2 | MASK_SH1) | |
| 251 #define SELECT_SH2A_NOFPU (MASK_HARD_SH2A | MASK_SH2 | MASK_SH1) | |
| 252 #define SELECT_SH2A_SINGLE_ONLY (MASK_SH_E | MASK_HARD_SH2A | MASK_SH2 \ | |
| 253 | MASK_SH1 | MASK_FPU_SINGLE) | |
| 254 #define SELECT_SH2A_SINGLE (MASK_SH_E | MASK_HARD_SH2A \ | |
| 255 | MASK_FPU_SINGLE | MASK_HARD_SH2A_DOUBLE \ | |
| 256 | MASK_SH2 | MASK_SH1) | |
| 257 #define SELECT_SH3 (MASK_SH3 | SELECT_SH2) | |
| 258 #define SELECT_SH3E (MASK_SH_E | MASK_FPU_SINGLE | SELECT_SH3) | |
| 259 #define SELECT_SH4_NOFPU (MASK_HARD_SH4 | SELECT_SH3) | |
| 260 #define SELECT_SH4_SINGLE_ONLY (MASK_HARD_SH4 | SELECT_SH3E) | |
| 261 #define SELECT_SH4 (MASK_SH4 | MASK_SH_E | MASK_HARD_SH4 \ | |
| 262 | SELECT_SH3) | |
| 263 #define SELECT_SH4_SINGLE (MASK_FPU_SINGLE | SELECT_SH4) | |
| 264 #define SELECT_SH4A_NOFPU (MASK_SH4A | SELECT_SH4_NOFPU) | |
| 265 #define SELECT_SH4A_SINGLE_ONLY (MASK_SH4A | SELECT_SH4_SINGLE_ONLY) | |
| 266 #define SELECT_SH4A (MASK_SH4A | SELECT_SH4) | |
| 267 #define SELECT_SH4A_SINGLE (MASK_SH4A | SELECT_SH4_SINGLE) | |
| 268 #define SELECT_SH5_64MEDIA (MASK_SH5 | MASK_SH4) | |
| 269 #define SELECT_SH5_64MEDIA_NOFPU (MASK_SH5) | |
| 270 #define SELECT_SH5_32MEDIA (MASK_SH5 | MASK_SH4 | MASK_SH_E) | |
| 271 #define SELECT_SH5_32MEDIA_NOFPU (MASK_SH5 | MASK_SH_E) | |
| 272 #define SELECT_SH5_COMPACT (MASK_SH5 | MASK_SH4 | SELECT_SH3E) | |
| 273 #define SELECT_SH5_COMPACT_NOFPU (MASK_SH5 | SELECT_SH3) | |
| 274 | |
| 275 #if SUPPORT_SH1 | |
| 276 #define SUPPORT_SH2 1 | |
| 277 #endif | |
| 278 #if SUPPORT_SH2 | |
| 279 #define SUPPORT_SH3 1 | |
| 280 #define SUPPORT_SH2A_NOFPU 1 | |
| 281 #endif | |
| 282 #if SUPPORT_SH3 | |
| 283 #define SUPPORT_SH4_NOFPU 1 | |
| 284 #endif | |
| 285 #if SUPPORT_SH4_NOFPU | |
| 286 #define SUPPORT_SH4A_NOFPU 1 | |
| 287 #define SUPPORT_SH4AL 1 | |
| 288 #endif | |
| 289 | |
| 290 #if SUPPORT_SH2E | |
| 291 #define SUPPORT_SH3E 1 | |
| 292 #define SUPPORT_SH2A_SINGLE_ONLY 1 | |
| 293 #endif | |
| 294 #if SUPPORT_SH3E | |
| 295 #define SUPPORT_SH4_SINGLE_ONLY 1 | |
| 296 #endif | |
| 297 #if SUPPORT_SH4_SINGLE_ONLY | |
| 298 #define SUPPORT_SH4A_SINGLE_ONLY 1 | |
| 299 #endif | |
| 300 | |
| 301 #if SUPPORT_SH4 | |
| 302 #define SUPPORT_SH4A 1 | |
| 303 #endif | |
| 304 | |
| 305 #if SUPPORT_SH4_SINGLE | |
| 306 #define SUPPORT_SH4A_SINGLE 1 | |
| 307 #endif | |
| 308 | |
| 309 #if SUPPORT_SH5_COMPAT | |
| 310 #define SUPPORT_SH5_32MEDIA 1 | |
| 311 #endif | |
| 312 | |
| 313 #if SUPPORT_SH5_COMPACT_NOFPU | |
| 314 #define SUPPORT_SH5_32MEDIA_NOFPU 1 | |
| 315 #endif | |
| 316 | |
| 317 #define SUPPORT_ANY_SH5_32MEDIA \ | |
| 318 (SUPPORT_SH5_32MEDIA || SUPPORT_SH5_32MEDIA_NOFPU) | |
| 319 #define SUPPORT_ANY_SH5_64MEDIA \ | |
| 320 (SUPPORT_SH5_64MEDIA || SUPPORT_SH5_64MEDIA_NOFPU) | |
| 321 #define SUPPORT_ANY_SH5 \ | |
| 322 (SUPPORT_ANY_SH5_32MEDIA || SUPPORT_ANY_SH5_64MEDIA) | |
| 323 | |
| 324 /* Reset all target-selection flags. */ | |
| 325 #define MASK_ARCH (MASK_SH1 | MASK_SH2 | MASK_SH3 | MASK_SH_E | MASK_SH4 \ | |
| 326 | MASK_HARD_SH2A | MASK_HARD_SH2A_DOUBLE | MASK_SH4A \ | |
| 327 | MASK_HARD_SH4 | MASK_FPU_SINGLE | MASK_SH5) | |
| 328 | |
| 329 /* This defaults us to big-endian. */ | |
| 330 #ifndef TARGET_ENDIAN_DEFAULT | |
| 331 #define TARGET_ENDIAN_DEFAULT 0 | |
| 332 #endif | |
| 333 | |
| 334 #ifndef TARGET_OPT_DEFAULT | |
| 335 #define TARGET_OPT_DEFAULT MASK_ADJUST_UNROLL | |
| 336 #endif | |
| 337 | |
| 338 #define TARGET_DEFAULT \ | |
| 339 (TARGET_CPU_DEFAULT | TARGET_ENDIAN_DEFAULT | TARGET_OPT_DEFAULT) | |
| 340 | |
| 341 #ifndef SH_MULTILIB_CPU_DEFAULT | |
| 342 #define SH_MULTILIB_CPU_DEFAULT "m1" | |
| 343 #endif | |
| 344 | |
| 345 #if TARGET_ENDIAN_DEFAULT | |
| 346 #define MULTILIB_DEFAULTS { "ml", SH_MULTILIB_CPU_DEFAULT } | |
| 347 #else | |
| 348 #define MULTILIB_DEFAULTS { "mb", SH_MULTILIB_CPU_DEFAULT } | |
| 349 #endif | |
| 350 | |
| 351 #define CPP_SPEC " %(subtarget_cpp_spec) " | |
| 352 | |
| 353 #ifndef SUBTARGET_CPP_SPEC | |
| 354 #define SUBTARGET_CPP_SPEC "" | |
| 355 #endif | |
| 356 | |
| 357 #ifndef SUBTARGET_EXTRA_SPECS | |
| 358 #define SUBTARGET_EXTRA_SPECS | |
| 359 #endif | |
| 360 | |
| 361 #define EXTRA_SPECS \ | |
| 362 { "subtarget_cpp_spec", SUBTARGET_CPP_SPEC }, \ | |
| 363 { "link_emul_prefix", LINK_EMUL_PREFIX }, \ | |
| 364 { "link_default_cpu_emul", LINK_DEFAULT_CPU_EMUL }, \ | |
| 365 { "subtarget_link_emul_suffix", SUBTARGET_LINK_EMUL_SUFFIX }, \ | |
| 366 { "subtarget_link_spec", SUBTARGET_LINK_SPEC }, \ | |
| 367 { "subtarget_asm_endian_spec", SUBTARGET_ASM_ENDIAN_SPEC }, \ | |
| 368 { "subtarget_asm_relax_spec", SUBTARGET_ASM_RELAX_SPEC }, \ | |
| 369 { "subtarget_asm_isa_spec", SUBTARGET_ASM_ISA_SPEC }, \ | |
| 370 { "subtarget_asm_spec", SUBTARGET_ASM_SPEC }, \ | |
| 371 SUBTARGET_EXTRA_SPECS | |
| 372 | |
| 373 #if TARGET_CPU_DEFAULT & MASK_HARD_SH4 | |
| 374 #define SUBTARGET_ASM_RELAX_SPEC "%{!m1:%{!m2:%{!m3*:%{!m5*:-isa=sh4-up}}}}" | |
| 375 #else | |
| 376 #define SUBTARGET_ASM_RELAX_SPEC "%{m4*:-isa=sh4-up}" | |
| 377 #endif | |
| 378 | |
| 379 #define SH_ASM_SPEC \ | |
| 380 "%(subtarget_asm_endian_spec) %{mrelax:-relax %(subtarget_asm_relax_spec)}\ | |
| 381 %(subtarget_asm_isa_spec) %(subtarget_asm_spec)\ | |
| 382 %{m2a:--isa=sh2a} \ | |
| 383 %{m2a-single:--isa=sh2a} \ | |
| 384 %{m2a-single-only:--isa=sh2a} \ | |
| 385 %{m2a-nofpu:--isa=sh2a-nofpu} \ | |
| 386 %{m5-compact*:--isa=SHcompact} \ | |
| 387 %{m5-32media*:--isa=SHmedia --abi=32} \ | |
| 388 %{m5-64media*:--isa=SHmedia --abi=64} \ | |
| 389 %{m4al:-dsp} %{mcut2-workaround:-cut2-workaround}" | |
| 390 | |
| 391 #define ASM_SPEC SH_ASM_SPEC | |
| 392 | |
| 393 #ifndef SUBTARGET_ASM_ENDIAN_SPEC | |
| 394 #if TARGET_ENDIAN_DEFAULT == MASK_LITTLE_ENDIAN | |
| 395 #define SUBTARGET_ASM_ENDIAN_SPEC "%{mb:-big} %{!mb:-little}" | |
| 396 #else | |
| 397 #define SUBTARGET_ASM_ENDIAN_SPEC "%{ml:-little} %{!ml:-big}" | |
| 398 #endif | |
| 399 #endif | |
| 400 | |
| 401 #if STRICT_NOFPU == 1 | |
| 402 /* Strict nofpu means that the compiler should tell the assembler | |
| 403 to reject FPU instructions. E.g. from ASM inserts. */ | |
| 404 #if TARGET_CPU_DEFAULT & MASK_HARD_SH4 && !(TARGET_CPU_DEFAULT & MASK_SH_E) | |
| 405 #define SUBTARGET_ASM_ISA_SPEC "%{!m1:%{!m2:%{!m3*:%{m4-nofpu|!m4*:%{!m5:-isa=sh4-nofpu}}}}}" | |
| 406 #else | |
| 407 /* If there were an -isa option for sh5-nofpu then it would also go here. */ | |
| 408 #define SUBTARGET_ASM_ISA_SPEC \ | |
| 409 "%{m4-nofpu:-isa=sh4-nofpu} " ASM_ISA_DEFAULT_SPEC | |
| 410 #endif | |
| 411 #else /* ! STRICT_NOFPU */ | |
| 412 #define SUBTARGET_ASM_ISA_SPEC ASM_ISA_DEFAULT_SPEC | |
| 413 #endif | |
| 414 | |
| 415 #ifndef SUBTARGET_ASM_SPEC | |
| 416 #define SUBTARGET_ASM_SPEC "" | |
| 417 #endif | |
| 418 | |
| 419 #if TARGET_ENDIAN_DEFAULT == MASK_LITTLE_ENDIAN | |
| 420 #define LINK_EMUL_PREFIX "sh%{!mb:l}" | |
| 421 #else | |
| 422 #define LINK_EMUL_PREFIX "sh%{ml:l}" | |
| 423 #endif | |
| 424 | |
| 425 #if TARGET_CPU_DEFAULT & MASK_SH5 | |
| 426 #if TARGET_CPU_DEFAULT & MASK_SH_E | |
| 427 #define LINK_DEFAULT_CPU_EMUL "32" | |
| 428 #if TARGET_CPU_DEFAULT & MASK_SH1 | |
| 429 #define ASM_ISA_SPEC_DEFAULT "--isa=SHcompact" | |
| 430 #else | |
| 431 #define ASM_ISA_SPEC_DEFAULT "--isa=SHmedia --abi=32" | |
| 432 #endif /* MASK_SH1 */ | |
| 433 #else /* !MASK_SH_E */ | |
| 434 #define LINK_DEFAULT_CPU_EMUL "64" | |
| 435 #define ASM_ISA_SPEC_DEFAULT "--isa=SHmedia --abi=64" | |
| 436 #endif /* MASK_SH_E */ | |
| 437 #define ASM_ISA_DEFAULT_SPEC \ | |
| 438 " %{!m1:%{!m2*:%{!m3*:%{!m4*:%{!m5*:" ASM_ISA_SPEC_DEFAULT "}}}}}" | |
| 439 #else /* !MASK_SH5 */ | |
| 440 #define LINK_DEFAULT_CPU_EMUL "" | |
| 441 #define ASM_ISA_DEFAULT_SPEC "" | |
| 442 #endif /* MASK_SH5 */ | |
| 443 | |
| 444 #define SUBTARGET_LINK_EMUL_SUFFIX "" | |
| 445 #define SUBTARGET_LINK_SPEC "" | |
| 446 | |
| 447 /* svr4.h redefines LINK_SPEC inappropriately, so go via SH_LINK_SPEC, | |
| 448 so that we can undo the damage without code replication. */ | |
| 449 #define LINK_SPEC SH_LINK_SPEC | |
| 450 | |
| 451 #define SH_LINK_SPEC "\ | |
| 452 -m %(link_emul_prefix)\ | |
| 453 %{m5-compact*|m5-32media*:32}\ | |
| 454 %{m5-64media*:64}\ | |
| 455 %{!m1:%{!m2:%{!m3*:%{!m4*:%{!m5*:%(link_default_cpu_emul)}}}}}\ | |
| 456 %(subtarget_link_emul_suffix) \ | |
| 457 %{mrelax:-relax} %(subtarget_link_spec)" | |
| 458 | |
| 459 #ifndef SH_DIV_STR_FOR_SIZE | |
| 460 #define SH_DIV_STR_FOR_SIZE "call" | |
| 461 #endif | |
| 462 | |
| 463 #define DRIVER_SELF_SPECS "%{m2a:%{ml:%eSH2a does not support little-endian}}" | |
|
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464 |
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465 #define OPTIMIZATION_OPTIONS(LEVEL,SIZE) sh_optimization_options (LEVEL, SIZE) |
| 0 | 466 |
| 467 #define ASSEMBLER_DIALECT assembler_dialect | |
| 468 | |
| 469 extern int assembler_dialect; | |
| 470 | |
| 471 enum sh_divide_strategy_e { | |
| 472 /* SH5 strategies. */ | |
| 473 SH_DIV_CALL, | |
| 474 SH_DIV_CALL2, | |
| 475 SH_DIV_FP, /* We could do this also for SH4. */ | |
| 476 SH_DIV_INV, | |
| 477 SH_DIV_INV_MINLAT, | |
| 478 SH_DIV_INV20U, | |
| 479 SH_DIV_INV20L, | |
| 480 SH_DIV_INV_CALL, | |
| 481 SH_DIV_INV_CALL2, | |
| 482 SH_DIV_INV_FP, | |
| 483 /* SH1 .. SH4 strategies. Because of the small number of registers | |
| 484 available, the compiler uses knowledge of the actual set of registers | |
| 485 being clobbered by the different functions called. */ | |
| 486 SH_DIV_CALL_DIV1, /* No FPU, medium size, highest latency. */ | |
| 487 SH_DIV_CALL_FP, /* FPU needed, small size, high latency. */ | |
| 488 SH_DIV_CALL_TABLE, /* No FPU, large size, medium latency. */ | |
| 489 SH_DIV_INTRINSIC | |
| 490 }; | |
| 491 | |
| 492 extern enum sh_divide_strategy_e sh_div_strategy; | |
| 493 | |
| 494 #ifndef SH_DIV_STRATEGY_DEFAULT | |
| 495 #define SH_DIV_STRATEGY_DEFAULT SH_DIV_CALL | |
| 496 #endif | |
| 497 | |
| 498 #define SUBTARGET_OVERRIDE_OPTIONS (void) 0 | |
| 499 | |
| 500 extern const char *sh_fixed_range_str; | |
| 501 | |
|
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502 #define OVERRIDE_OPTIONS sh_override_options () |
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503 |
| 0 | 504 |
| 505 /* Target machine storage layout. */ | |
| 506 | |
| 507 /* Define this if most significant bit is lowest numbered | |
| 508 in instructions that operate on numbered bit-fields. */ | |
| 509 | |
| 510 #define BITS_BIG_ENDIAN 0 | |
| 511 | |
| 512 /* Define this if most significant byte of a word is the lowest numbered. */ | |
| 513 #define BYTES_BIG_ENDIAN (TARGET_LITTLE_ENDIAN == 0) | |
| 514 | |
| 515 /* Define this if most significant word of a multiword number is the lowest | |
| 516 numbered. */ | |
| 517 #define WORDS_BIG_ENDIAN (TARGET_LITTLE_ENDIAN == 0) | |
| 518 | |
| 519 /* Define this to set the endianness to use in libgcc2.c, which can | |
| 520 not depend on target_flags. */ | |
| 521 #if defined(__LITTLE_ENDIAN__) | |
| 522 #define LIBGCC2_WORDS_BIG_ENDIAN 0 | |
| 523 #else | |
| 524 #define LIBGCC2_WORDS_BIG_ENDIAN 1 | |
| 525 #endif | |
| 526 | |
| 527 #define MAX_BITS_PER_WORD 64 | |
| 528 | |
| 529 /* Width in bits of an `int'. We want just 32-bits, even if words are | |
| 530 longer. */ | |
| 531 #define INT_TYPE_SIZE 32 | |
| 532 | |
| 533 /* Width in bits of a `long'. */ | |
| 534 #define LONG_TYPE_SIZE (TARGET_SHMEDIA64 ? 64 : 32) | |
| 535 | |
| 536 /* Width in bits of a `long long'. */ | |
| 537 #define LONG_LONG_TYPE_SIZE 64 | |
| 538 | |
| 539 /* Width in bits of a `long double'. */ | |
| 540 #define LONG_DOUBLE_TYPE_SIZE 64 | |
| 541 | |
| 542 /* Width of a word, in units (bytes). */ | |
| 543 #define UNITS_PER_WORD (TARGET_SHMEDIA ? 8 : 4) | |
| 544 #define MIN_UNITS_PER_WORD 4 | |
| 545 | |
| 546 /* Scaling factor for Dwarf data offsets for CFI information. | |
| 547 The dwarf2out.c default would use -UNITS_PER_WORD, which is -8 for | |
| 548 SHmedia; however, since we do partial register saves for the registers | |
| 549 visible to SHcompact, and for target registers for SHMEDIA32, we have | |
| 550 to allow saves that are only 4-byte aligned. */ | |
| 551 #define DWARF_CIE_DATA_ALIGNMENT -4 | |
| 552 | |
| 553 /* Width in bits of a pointer. | |
| 554 See also the macro `Pmode' defined below. */ | |
| 555 #define POINTER_SIZE (TARGET_SHMEDIA64 ? 64 : 32) | |
| 556 | |
| 557 /* Allocation boundary (in *bits*) for storing arguments in argument list. */ | |
| 558 #define PARM_BOUNDARY (TARGET_SH5 ? 64 : 32) | |
| 559 | |
| 560 /* Boundary (in *bits*) on which stack pointer should be aligned. */ | |
| 561 #define STACK_BOUNDARY BIGGEST_ALIGNMENT | |
| 562 | |
| 563 /* The log (base 2) of the cache line size, in bytes. Processors prior to | |
| 564 SH2 have no actual cache, but they fetch code in chunks of 4 bytes. | |
| 565 The SH2/3 have 16 byte cache lines, and the SH4 has a 32 byte cache line */ | |
| 566 #define CACHE_LOG (TARGET_CACHE32 ? 5 : TARGET_SH2 ? 4 : 2) | |
| 567 | |
| 568 /* ABI given & required minimum allocation boundary (in *bits*) for the | |
| 569 code of a function. */ | |
| 570 #define FUNCTION_BOUNDARY (16 << TARGET_SHMEDIA) | |
| 571 | |
| 572 /* On SH5, the lowest bit is used to indicate SHmedia functions, so | |
| 573 the vbit must go into the delta field of | |
| 574 pointers-to-member-functions. */ | |
| 575 #define TARGET_PTRMEMFUNC_VBIT_LOCATION \ | |
| 576 (TARGET_SH5 ? ptrmemfunc_vbit_in_delta : ptrmemfunc_vbit_in_pfn) | |
| 577 | |
| 578 /* Alignment of field after `int : 0' in a structure. */ | |
| 579 #define EMPTY_FIELD_BOUNDARY 32 | |
| 580 | |
| 581 /* No data type wants to be aligned rounder than this. */ | |
| 582 #define BIGGEST_ALIGNMENT (TARGET_ALIGN_DOUBLE ? 64 : 32) | |
| 583 | |
| 584 /* The best alignment to use in cases where we have a choice. */ | |
| 585 #define FASTEST_ALIGNMENT (TARGET_SH5 ? 64 : 32) | |
| 586 | |
| 587 /* Make strings word-aligned so strcpy from constants will be faster. */ | |
| 588 #define CONSTANT_ALIGNMENT(EXP, ALIGN) \ | |
| 589 ((TREE_CODE (EXP) == STRING_CST \ | |
| 590 && (ALIGN) < FASTEST_ALIGNMENT) \ | |
| 591 ? FASTEST_ALIGNMENT : (ALIGN)) | |
| 592 | |
| 593 /* get_mode_alignment assumes complex values are always held in multiple | |
| 594 registers, but that is not the case on the SH; CQImode and CHImode are | |
| 595 held in a single integer register. SH5 also holds CSImode and SCmode | |
| 596 values in integer registers. This is relevant for argument passing on | |
| 597 SHcompact as we use a stack temp in order to pass CSImode by reference. */ | |
| 598 #define LOCAL_ALIGNMENT(TYPE, ALIGN) \ | |
| 599 ((GET_MODE_CLASS (TYPE_MODE (TYPE)) == MODE_COMPLEX_INT \ | |
| 600 || GET_MODE_CLASS (TYPE_MODE (TYPE)) == MODE_COMPLEX_FLOAT) \ | |
| 601 ? (unsigned) MIN (BIGGEST_ALIGNMENT, GET_MODE_BITSIZE (TYPE_MODE (TYPE))) \ | |
| 602 : (unsigned) DATA_ALIGNMENT(TYPE, ALIGN)) | |
| 603 | |
| 604 /* Make arrays of chars word-aligned for the same reasons. */ | |
| 605 #define DATA_ALIGNMENT(TYPE, ALIGN) \ | |
| 606 (TREE_CODE (TYPE) == ARRAY_TYPE \ | |
| 607 && TYPE_MODE (TREE_TYPE (TYPE)) == QImode \ | |
| 608 && (ALIGN) < FASTEST_ALIGNMENT ? FASTEST_ALIGNMENT : (ALIGN)) | |
| 609 | |
| 610 /* Number of bits which any structure or union's size must be a | |
| 611 multiple of. Each structure or union's size is rounded up to a | |
| 612 multiple of this. */ | |
| 613 #define STRUCTURE_SIZE_BOUNDARY (TARGET_PADSTRUCT ? 32 : 8) | |
| 614 | |
| 615 /* Set this nonzero if move instructions will actually fail to work | |
| 616 when given unaligned data. */ | |
| 617 #define STRICT_ALIGNMENT 1 | |
| 618 | |
| 619 /* If LABEL_AFTER_BARRIER demands an alignment, return its base 2 logarithm. */ | |
| 620 #define LABEL_ALIGN_AFTER_BARRIER(LABEL_AFTER_BARRIER) \ | |
| 621 barrier_align (LABEL_AFTER_BARRIER) | |
| 622 | |
| 623 #define LOOP_ALIGN(A_LABEL) \ | |
| 624 ((! optimize || TARGET_HARD_SH4 || TARGET_SMALLCODE) \ | |
| 625 ? 0 : sh_loop_align (A_LABEL)) | |
| 626 | |
| 627 #define LABEL_ALIGN(A_LABEL) \ | |
| 628 ( \ | |
| 629 (PREV_INSN (A_LABEL) \ | |
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630 && NONJUMP_INSN_P (PREV_INSN (A_LABEL)) \ |
| 0 | 631 && GET_CODE (PATTERN (PREV_INSN (A_LABEL))) == UNSPEC_VOLATILE \ |
| 632 && XINT (PATTERN (PREV_INSN (A_LABEL)), 1) == UNSPECV_ALIGN) \ | |
| 633 /* explicit alignment insn in constant tables. */ \ | |
| 634 ? INTVAL (XVECEXP (PATTERN (PREV_INSN (A_LABEL)), 0, 0)) \ | |
| 635 : 0) | |
| 636 | |
| 637 /* Jump tables must be 32 bit aligned, no matter the size of the element. */ | |
| 638 #define ADDR_VEC_ALIGN(ADDR_VEC) 2 | |
| 639 | |
| 640 /* The base two logarithm of the known minimum alignment of an insn length. */ | |
| 641 #define INSN_LENGTH_ALIGNMENT(A_INSN) \ | |
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642 (NONJUMP_INSN_P (A_INSN) \ |
| 0 | 643 ? 1 << TARGET_SHMEDIA \ |
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644 : JUMP_P (A_INSN) || CALL_P (A_INSN) \ |
| 0 | 645 ? 1 << TARGET_SHMEDIA \ |
| 646 : CACHE_LOG) | |
| 647 | |
| 648 /* Standard register usage. */ | |
| 649 | |
| 650 /* Register allocation for the Renesas calling convention: | |
| 651 | |
| 652 r0 arg return | |
| 653 r1..r3 scratch | |
| 654 r4..r7 args in | |
| 655 r8..r13 call saved | |
| 656 r14 frame pointer/call saved | |
| 657 r15 stack pointer | |
| 658 ap arg pointer (doesn't really exist, always eliminated) | |
| 659 pr subroutine return address | |
| 660 t t bit | |
| 661 mach multiply/accumulate result, high part | |
| 662 macl multiply/accumulate result, low part. | |
| 663 fpul fp/int communication register | |
| 664 rap return address pointer register | |
| 665 fr0 fp arg return | |
| 666 fr1..fr3 scratch floating point registers | |
| 667 fr4..fr11 fp args in | |
| 668 fr12..fr15 call saved floating point registers */ | |
| 669 | |
| 670 #define MAX_REGISTER_NAME_LENGTH 5 | |
| 671 extern char sh_register_names[][MAX_REGISTER_NAME_LENGTH + 1]; | |
| 672 | |
| 673 #define SH_REGISTER_NAMES_INITIALIZER \ | |
| 674 { \ | |
| 675 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", \ | |
| 676 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", \ | |
| 677 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", \ | |
| 678 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31", \ | |
| 679 "r32", "r33", "r34", "r35", "r36", "r37", "r38", "r39", \ | |
| 680 "r40", "r41", "r42", "r43", "r44", "r45", "r46", "r47", \ | |
| 681 "r48", "r49", "r50", "r51", "r52", "r53", "r54", "r55", \ | |
| 682 "r56", "r57", "r58", "r59", "r60", "r61", "r62", "r63", \ | |
| 683 "fr0", "fr1", "fr2", "fr3", "fr4", "fr5", "fr6", "fr7", \ | |
| 684 "fr8", "fr9", "fr10", "fr11", "fr12", "fr13", "fr14", "fr15", \ | |
| 685 "fr16", "fr17", "fr18", "fr19", "fr20", "fr21", "fr22", "fr23", \ | |
| 686 "fr24", "fr25", "fr26", "fr27", "fr28", "fr29", "fr30", "fr31", \ | |
| 687 "fr32", "fr33", "fr34", "fr35", "fr36", "fr37", "fr38", "fr39", \ | |
| 688 "fr40", "fr41", "fr42", "fr43", "fr44", "fr45", "fr46", "fr47", \ | |
| 689 "fr48", "fr49", "fr50", "fr51", "fr52", "fr53", "fr54", "fr55", \ | |
| 690 "fr56", "fr57", "fr58", "fr59", "fr60", "fr61", "fr62", "fr63", \ | |
| 691 "tr0", "tr1", "tr2", "tr3", "tr4", "tr5", "tr6", "tr7", \ | |
| 692 "xd0", "xd2", "xd4", "xd6", "xd8", "xd10", "xd12", "xd14", \ | |
| 693 "gbr", "ap", "pr", "t", "mach", "macl", "fpul", "fpscr", \ | |
| 694 "rap", "sfp" \ | |
| 695 } | |
| 696 | |
| 697 #define REGNAMES_ARR_INDEX_1(index) \ | |
| 698 (sh_register_names[index]) | |
| 699 #define REGNAMES_ARR_INDEX_2(index) \ | |
| 700 REGNAMES_ARR_INDEX_1 ((index)), REGNAMES_ARR_INDEX_1 ((index)+1) | |
| 701 #define REGNAMES_ARR_INDEX_4(index) \ | |
| 702 REGNAMES_ARR_INDEX_2 ((index)), REGNAMES_ARR_INDEX_2 ((index)+2) | |
| 703 #define REGNAMES_ARR_INDEX_8(index) \ | |
| 704 REGNAMES_ARR_INDEX_4 ((index)), REGNAMES_ARR_INDEX_4 ((index)+4) | |
| 705 #define REGNAMES_ARR_INDEX_16(index) \ | |
| 706 REGNAMES_ARR_INDEX_8 ((index)), REGNAMES_ARR_INDEX_8 ((index)+8) | |
| 707 #define REGNAMES_ARR_INDEX_32(index) \ | |
| 708 REGNAMES_ARR_INDEX_16 ((index)), REGNAMES_ARR_INDEX_16 ((index)+16) | |
| 709 #define REGNAMES_ARR_INDEX_64(index) \ | |
| 710 REGNAMES_ARR_INDEX_32 ((index)), REGNAMES_ARR_INDEX_32 ((index)+32) | |
| 711 | |
| 712 #define REGISTER_NAMES \ | |
| 713 { \ | |
| 714 REGNAMES_ARR_INDEX_64 (0), \ | |
| 715 REGNAMES_ARR_INDEX_64 (64), \ | |
| 716 REGNAMES_ARR_INDEX_8 (128), \ | |
| 717 REGNAMES_ARR_INDEX_8 (136), \ | |
| 718 REGNAMES_ARR_INDEX_8 (144), \ | |
| 719 REGNAMES_ARR_INDEX_2 (152) \ | |
| 720 } | |
| 721 | |
| 722 #define ADDREGNAMES_SIZE 32 | |
| 723 #define MAX_ADDITIONAL_REGISTER_NAME_LENGTH 4 | |
| 724 extern char sh_additional_register_names[ADDREGNAMES_SIZE] \ | |
| 725 [MAX_ADDITIONAL_REGISTER_NAME_LENGTH + 1]; | |
| 726 | |
| 727 #define SH_ADDITIONAL_REGISTER_NAMES_INITIALIZER \ | |
| 728 { \ | |
| 729 "dr0", "dr2", "dr4", "dr6", "dr8", "dr10", "dr12", "dr14", \ | |
| 730 "dr16", "dr18", "dr20", "dr22", "dr24", "dr26", "dr28", "dr30", \ | |
| 731 "dr32", "dr34", "dr36", "dr38", "dr40", "dr42", "dr44", "dr46", \ | |
| 732 "dr48", "dr50", "dr52", "dr54", "dr56", "dr58", "dr60", "dr62" \ | |
| 733 } | |
| 734 | |
| 735 #define ADDREGNAMES_REGNO(index) \ | |
| 736 ((index < 32) ? (FIRST_FP_REG + (index) * 2) \ | |
| 737 : (-1)) | |
| 738 | |
| 739 #define ADDREGNAMES_ARR_INDEX_1(index) \ | |
| 740 { (sh_additional_register_names[index]), ADDREGNAMES_REGNO (index) } | |
| 741 #define ADDREGNAMES_ARR_INDEX_2(index) \ | |
| 742 ADDREGNAMES_ARR_INDEX_1 ((index)), ADDREGNAMES_ARR_INDEX_1 ((index)+1) | |
| 743 #define ADDREGNAMES_ARR_INDEX_4(index) \ | |
| 744 ADDREGNAMES_ARR_INDEX_2 ((index)), ADDREGNAMES_ARR_INDEX_2 ((index)+2) | |
| 745 #define ADDREGNAMES_ARR_INDEX_8(index) \ | |
| 746 ADDREGNAMES_ARR_INDEX_4 ((index)), ADDREGNAMES_ARR_INDEX_4 ((index)+4) | |
| 747 #define ADDREGNAMES_ARR_INDEX_16(index) \ | |
| 748 ADDREGNAMES_ARR_INDEX_8 ((index)), ADDREGNAMES_ARR_INDEX_8 ((index)+8) | |
| 749 #define ADDREGNAMES_ARR_INDEX_32(index) \ | |
| 750 ADDREGNAMES_ARR_INDEX_16 ((index)), ADDREGNAMES_ARR_INDEX_16 ((index)+16) | |
| 751 | |
| 752 #define ADDITIONAL_REGISTER_NAMES \ | |
| 753 { \ | |
| 754 ADDREGNAMES_ARR_INDEX_32 (0) \ | |
| 755 } | |
| 756 | |
| 757 /* Number of actual hardware registers. | |
| 758 The hardware registers are assigned numbers for the compiler | |
| 759 from 0 to just below FIRST_PSEUDO_REGISTER. | |
| 760 All registers that the compiler knows about must be given numbers, | |
| 761 even those that are not normally considered general registers. */ | |
| 762 | |
| 763 /* There are many other relevant definitions in sh.md's md_constants. */ | |
| 764 | |
| 765 #define FIRST_GENERAL_REG R0_REG | |
| 766 #define LAST_GENERAL_REG (FIRST_GENERAL_REG + (TARGET_SHMEDIA ? 63 : 15)) | |
| 767 #define FIRST_FP_REG DR0_REG | |
| 768 #define LAST_FP_REG (FIRST_FP_REG + \ | |
| 769 (TARGET_SHMEDIA_FPU ? 63 : TARGET_SH2E ? 15 : -1)) | |
| 770 #define FIRST_XD_REG XD0_REG | |
| 771 #define LAST_XD_REG (FIRST_XD_REG + ((TARGET_SH4 && TARGET_FMOVD) ? 7 : -1)) | |
| 772 #define FIRST_TARGET_REG TR0_REG | |
| 773 #define LAST_TARGET_REG (FIRST_TARGET_REG + (TARGET_SHMEDIA ? 7 : -1)) | |
| 774 | |
| 775 /* Registers that can be accessed through bank0 or bank1 depending on sr.md. */ | |
| 776 | |
| 777 #define FIRST_BANKED_REG R0_REG | |
| 778 #define LAST_BANKED_REG R7_REG | |
| 779 | |
| 780 #define BANKED_REGISTER_P(REGNO) \ | |
| 781 IN_RANGE ((REGNO), \ | |
| 782 (unsigned HOST_WIDE_INT) FIRST_BANKED_REG, \ | |
| 783 (unsigned HOST_WIDE_INT) LAST_BANKED_REG) | |
| 784 | |
| 785 #define GENERAL_REGISTER_P(REGNO) \ | |
| 786 IN_RANGE ((REGNO), \ | |
| 787 (unsigned HOST_WIDE_INT) FIRST_GENERAL_REG, \ | |
| 788 (unsigned HOST_WIDE_INT) LAST_GENERAL_REG) | |
| 789 | |
| 790 #define GENERAL_OR_AP_REGISTER_P(REGNO) \ | |
| 791 (GENERAL_REGISTER_P (REGNO) || ((REGNO) == AP_REG) \ | |
| 792 || ((REGNO) == FRAME_POINTER_REGNUM)) | |
| 793 | |
| 794 #define FP_REGISTER_P(REGNO) \ | |
| 795 ((int) (REGNO) >= FIRST_FP_REG && (int) (REGNO) <= LAST_FP_REG) | |
| 796 | |
| 797 #define XD_REGISTER_P(REGNO) \ | |
| 798 ((int) (REGNO) >= FIRST_XD_REG && (int) (REGNO) <= LAST_XD_REG) | |
| 799 | |
| 800 #define FP_OR_XD_REGISTER_P(REGNO) \ | |
| 801 (FP_REGISTER_P (REGNO) || XD_REGISTER_P (REGNO)) | |
| 802 | |
| 803 #define FP_ANY_REGISTER_P(REGNO) \ | |
| 804 (FP_REGISTER_P (REGNO) || XD_REGISTER_P (REGNO) || (REGNO) == FPUL_REG) | |
| 805 | |
| 806 #define SPECIAL_REGISTER_P(REGNO) \ | |
| 807 ((REGNO) == GBR_REG || (REGNO) == T_REG \ | |
| 808 || (REGNO) == MACH_REG || (REGNO) == MACL_REG) | |
| 809 | |
| 810 #define TARGET_REGISTER_P(REGNO) \ | |
| 811 ((int) (REGNO) >= FIRST_TARGET_REG && (int) (REGNO) <= LAST_TARGET_REG) | |
| 812 | |
| 813 #define SHMEDIA_REGISTER_P(REGNO) \ | |
| 814 (GENERAL_REGISTER_P (REGNO) || FP_REGISTER_P (REGNO) \ | |
| 815 || TARGET_REGISTER_P (REGNO)) | |
| 816 | |
| 817 /* This is to be used in CONDITIONAL_REGISTER_USAGE, to mark registers | |
| 818 that should be fixed. */ | |
| 819 #define VALID_REGISTER_P(REGNO) \ | |
| 820 (SHMEDIA_REGISTER_P (REGNO) || XD_REGISTER_P (REGNO) \ | |
| 821 || (REGNO) == AP_REG || (REGNO) == RAP_REG \ | |
| 822 || (REGNO) == FRAME_POINTER_REGNUM \ | |
| 823 || (TARGET_SH1 && (SPECIAL_REGISTER_P (REGNO) || (REGNO) == PR_REG)) \ | |
| 824 || (TARGET_SH2E && (REGNO) == FPUL_REG)) | |
| 825 | |
| 826 /* The mode that should be generally used to store a register by | |
| 827 itself in the stack, or to load it back. */ | |
| 828 #define REGISTER_NATURAL_MODE(REGNO) \ | |
| 829 (FP_REGISTER_P (REGNO) ? SFmode \ | |
| 830 : XD_REGISTER_P (REGNO) ? DFmode \ | |
| 831 : TARGET_SHMEDIA && ! HARD_REGNO_CALL_PART_CLOBBERED ((REGNO), DImode) \ | |
| 832 ? DImode \ | |
| 833 : SImode) | |
| 834 | |
| 835 #define FIRST_PSEUDO_REGISTER 154 | |
| 836 | |
| 837 /* Don't count soft frame pointer. */ | |
| 838 #define DWARF_FRAME_REGISTERS (FIRST_PSEUDO_REGISTER - 1) | |
| 839 | |
| 840 /* 1 for registers that have pervasive standard uses | |
| 841 and are not available for the register allocator. | |
| 842 | |
| 843 Mach register is fixed 'cause it's only 10 bits wide for SH1. | |
| 844 It is 32 bits wide for SH2. */ | |
| 845 | |
| 846 #define FIXED_REGISTERS \ | |
| 847 { \ | |
| 848 /* Regular registers. */ \ | |
| 849 0, 0, 0, 0, 0, 0, 0, 0, \ | |
| 850 0, 0, 0, 0, 0, 0, 0, 1, \ | |
| 851 /* r16 is reserved, r18 is the former pr. */ \ | |
| 852 1, 0, 0, 0, 0, 0, 0, 0, \ | |
| 853 /* r24 is reserved for the OS; r25, for the assembler or linker. */ \ | |
| 854 /* r26 is a global variable data pointer; r27 is for constants. */ \ | |
| 855 1, 1, 1, 1, 0, 0, 0, 0, \ | |
| 856 0, 0, 0, 0, 0, 0, 0, 0, \ | |
| 857 0, 0, 0, 0, 0, 0, 0, 0, \ | |
| 858 0, 0, 0, 0, 0, 0, 0, 0, \ | |
| 859 0, 0, 0, 0, 0, 0, 0, 1, \ | |
| 860 /* FP registers. */ \ | |
| 861 0, 0, 0, 0, 0, 0, 0, 0, \ | |
| 862 0, 0, 0, 0, 0, 0, 0, 0, \ | |
| 863 0, 0, 0, 0, 0, 0, 0, 0, \ | |
| 864 0, 0, 0, 0, 0, 0, 0, 0, \ | |
| 865 0, 0, 0, 0, 0, 0, 0, 0, \ | |
| 866 0, 0, 0, 0, 0, 0, 0, 0, \ | |
| 867 0, 0, 0, 0, 0, 0, 0, 0, \ | |
| 868 0, 0, 0, 0, 0, 0, 0, 0, \ | |
| 869 /* Branch target registers. */ \ | |
| 870 0, 0, 0, 0, 0, 0, 0, 0, \ | |
| 871 /* XD registers. */ \ | |
| 872 0, 0, 0, 0, 0, 0, 0, 0, \ | |
| 873 /*"gbr", "ap", "pr", "t", "mach", "macl", "fpul", "fpscr", */ \ | |
| 874 1, 1, 1, 1, 1, 1, 0, 1, \ | |
| 875 /*"rap", "sfp" */ \ | |
| 876 1, 1, \ | |
| 877 } | |
| 878 | |
| 879 /* 1 for registers not available across function calls. | |
| 880 These must include the FIXED_REGISTERS and also any | |
| 881 registers that can be used without being saved. | |
| 882 The latter must include the registers where values are returned | |
| 883 and the register where structure-value addresses are passed. | |
| 884 Aside from that, you can include as many other registers as you like. */ | |
| 885 | |
| 886 #define CALL_USED_REGISTERS \ | |
| 887 { \ | |
| 888 /* Regular registers. */ \ | |
| 889 1, 1, 1, 1, 1, 1, 1, 1, \ | |
| 890 /* R8 and R9 are call-clobbered on SH5, but not on earlier SH ABIs. \ | |
| 891 Only the lower 32bits of R10-R14 are guaranteed to be preserved \ | |
| 892 across SH5 function calls. */ \ | |
| 893 0, 0, 0, 0, 0, 0, 0, 1, \ | |
| 894 1, 1, 1, 1, 1, 1, 1, 1, \ | |
| 895 1, 1, 1, 1, 0, 0, 0, 0, \ | |
| 896 0, 0, 0, 0, 1, 1, 1, 1, \ | |
| 897 1, 1, 1, 1, 0, 0, 0, 0, \ | |
| 898 0, 0, 0, 0, 0, 0, 0, 0, \ | |
| 899 0, 0, 0, 0, 1, 1, 1, 1, \ | |
| 900 /* FP registers. */ \ | |
| 901 1, 1, 1, 1, 1, 1, 1, 1, \ | |
| 902 1, 1, 1, 1, 0, 0, 0, 0, \ | |
| 903 1, 1, 1, 1, 1, 1, 1, 1, \ | |
| 904 1, 1, 1, 1, 1, 1, 1, 1, \ | |
| 905 1, 1, 1, 1, 0, 0, 0, 0, \ | |
| 906 0, 0, 0, 0, 0, 0, 0, 0, \ | |
| 907 0, 0, 0, 0, 0, 0, 0, 0, \ | |
| 908 0, 0, 0, 0, 0, 0, 0, 0, \ | |
| 909 /* Branch target registers. */ \ | |
| 910 1, 1, 1, 1, 1, 0, 0, 0, \ | |
| 911 /* XD registers. */ \ | |
| 912 1, 1, 1, 1, 1, 1, 0, 0, \ | |
| 913 /*"gbr", "ap", "pr", "t", "mach", "macl", "fpul", "fpscr", */ \ | |
| 914 1, 1, 1, 1, 1, 1, 1, 1, \ | |
| 915 /*"rap", "sfp" */ \ | |
| 916 1, 1, \ | |
| 917 } | |
| 918 | |
| 919 /* CONDITIONAL_REGISTER_USAGE might want to make a register call-used, yet | |
| 920 fixed, like PIC_OFFSET_TABLE_REGNUM. */ | |
| 921 #define CALL_REALLY_USED_REGISTERS CALL_USED_REGISTERS | |
| 922 | |
| 923 /* Only the lower 32-bits of R10-R14 are guaranteed to be preserved | |
| 924 across SHcompact function calls. We can't tell whether a called | |
| 925 function is SHmedia or SHcompact, so we assume it may be when | |
| 926 compiling SHmedia code with the 32-bit ABI, since that's the only | |
| 927 ABI that can be linked with SHcompact code. */ | |
| 928 #define HARD_REGNO_CALL_PART_CLOBBERED(REGNO,MODE) \ | |
| 929 (TARGET_SHMEDIA32 \ | |
| 930 && GET_MODE_SIZE (MODE) > 4 \ | |
| 931 && (((REGNO) >= FIRST_GENERAL_REG + 10 \ | |
| 932 && (REGNO) <= FIRST_GENERAL_REG + 15) \ | |
| 933 || TARGET_REGISTER_P (REGNO) \ | |
| 934 || (REGNO) == PR_MEDIA_REG)) | |
| 935 | |
| 936 /* Return number of consecutive hard regs needed starting at reg REGNO | |
| 937 to hold something of mode MODE. | |
| 938 This is ordinarily the length in words of a value of mode MODE | |
| 939 but can be less for certain modes in special long registers. | |
| 940 | |
| 941 On the SH all but the XD regs are UNITS_PER_WORD bits wide. */ | |
| 942 | |
| 943 #define HARD_REGNO_NREGS(REGNO, MODE) \ | |
| 944 (XD_REGISTER_P (REGNO) \ | |
| 945 ? ((GET_MODE_SIZE (MODE) + (2*UNITS_PER_WORD - 1)) / (2*UNITS_PER_WORD)) \ | |
| 946 : (TARGET_SHMEDIA && FP_REGISTER_P (REGNO)) \ | |
| 947 ? ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD/2 - 1) / (UNITS_PER_WORD/2)) \ | |
| 948 : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)) | |
| 949 | |
| 950 /* Value is 1 if hard register REGNO can hold a value of machine-mode MODE. */ | |
| 951 | |
| 952 #define HARD_REGNO_MODE_OK(REGNO, MODE) \ | |
| 953 sh_hard_regno_mode_ok ((REGNO), (MODE)) | |
| 954 | |
| 955 /* Value is 1 if it is a good idea to tie two pseudo registers | |
| 956 when one has mode MODE1 and one has mode MODE2. | |
| 957 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2, | |
| 958 for any hard reg, then this must be 0 for correct output. | |
| 959 That's the case for xd registers: we don't hold SFmode values in | |
| 960 them, so we can't tie an SFmode pseudos with one in another | |
| 961 floating-point mode. */ | |
| 962 | |
| 963 #define MODES_TIEABLE_P(MODE1, MODE2) \ | |
| 964 ((MODE1) == (MODE2) \ | |
| 965 || (TARGET_SHMEDIA \ | |
| 966 && GET_MODE_SIZE (MODE1) == GET_MODE_SIZE (MODE2) \ | |
| 967 && INTEGRAL_MODE_P (MODE1) && INTEGRAL_MODE_P (MODE2)) \ | |
| 968 || (GET_MODE_CLASS (MODE1) == GET_MODE_CLASS (MODE2) \ | |
| 969 && (TARGET_SHMEDIA ? ((GET_MODE_SIZE (MODE1) <= 4) \ | |
| 970 && (GET_MODE_SIZE (MODE2) <= 4)) \ | |
| 971 : ((MODE1) != SFmode && (MODE2) != SFmode)))) | |
| 972 | |
| 973 /* A C expression that is nonzero if hard register NEW_REG can be | |
| 974 considered for use as a rename register for OLD_REG register */ | |
| 975 | |
| 976 #define HARD_REGNO_RENAME_OK(OLD_REG, NEW_REG) \ | |
| 977 sh_hard_regno_rename_ok (OLD_REG, NEW_REG) | |
| 978 | |
| 979 /* Specify the registers used for certain standard purposes. | |
| 980 The values of these macros are register numbers. */ | |
| 981 | |
| 982 /* Define this if the program counter is overloaded on a register. */ | |
| 983 /* #define PC_REGNUM 15*/ | |
| 984 | |
| 985 /* Register to use for pushing function arguments. */ | |
| 986 #define STACK_POINTER_REGNUM SP_REG | |
| 987 | |
| 988 /* Base register for access to local variables of the function. */ | |
| 989 #define HARD_FRAME_POINTER_REGNUM FP_REG | |
| 990 | |
| 991 /* Base register for access to local variables of the function. */ | |
| 992 #define FRAME_POINTER_REGNUM 153 | |
| 993 | |
| 994 /* Fake register that holds the address on the stack of the | |
| 995 current function's return address. */ | |
| 996 #define RETURN_ADDRESS_POINTER_REGNUM RAP_REG | |
| 997 | |
| 998 /* Register to hold the addressing base for position independent | |
| 999 code access to data items. */ | |
| 1000 #define PIC_OFFSET_TABLE_REGNUM (flag_pic ? PIC_REG : INVALID_REGNUM) | |
| 1001 | |
| 1002 #define GOT_SYMBOL_NAME "*_GLOBAL_OFFSET_TABLE_" | |
| 1003 | |
| 1004 /* Definitions for register eliminations. | |
| 1005 | |
| 1006 We have three registers that can be eliminated on the SH. First, the | |
| 1007 frame pointer register can often be eliminated in favor of the stack | |
| 1008 pointer register. Secondly, the argument pointer register can always be | |
| 1009 eliminated; it is replaced with either the stack or frame pointer. | |
| 1010 Third, there is the return address pointer, which can also be replaced | |
| 1011 with either the stack or the frame pointer. */ | |
| 1012 | |
| 1013 /* This is an array of structures. Each structure initializes one pair | |
| 1014 of eliminable registers. The "from" register number is given first, | |
| 1015 followed by "to". Eliminations of the same "from" register are listed | |
| 1016 in order of preference. */ | |
| 1017 | |
| 1018 /* If you add any registers here that are not actually hard registers, | |
| 1019 and that have any alternative of elimination that doesn't always | |
| 1020 apply, you need to amend calc_live_regs to exclude it, because | |
| 1021 reload spills all eliminable registers where it sees an | |
| 1022 can_eliminate == 0 entry, thus making them 'live' . | |
| 1023 If you add any hard registers that can be eliminated in different | |
| 1024 ways, you have to patch reload to spill them only when all alternatives | |
| 1025 of elimination fail. */ | |
| 1026 | |
| 1027 #define ELIMINABLE_REGS \ | |
| 1028 {{ HARD_FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \ | |
| 1029 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \ | |
| 1030 { FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}, \ | |
| 1031 { RETURN_ADDRESS_POINTER_REGNUM, STACK_POINTER_REGNUM}, \ | |
| 1032 { RETURN_ADDRESS_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}, \ | |
| 1033 { ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \ | |
| 1034 { ARG_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM},} | |
| 1035 | |
| 1036 /* Define the offset between two registers, one to be eliminated, and the other | |
| 1037 its replacement, at the start of a routine. */ | |
| 1038 | |
| 1039 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \ | |
| 1040 OFFSET = initial_elimination_offset ((FROM), (TO)) | |
| 1041 | |
| 1042 /* Base register for access to arguments of the function. */ | |
| 1043 #define ARG_POINTER_REGNUM AP_REG | |
| 1044 | |
| 1045 /* Register in which the static-chain is passed to a function. */ | |
| 1046 #define STATIC_CHAIN_REGNUM (TARGET_SH5 ? 1 : 3) | |
| 1047 | |
| 1048 /* Don't default to pcc-struct-return, because we have already specified | |
| 1049 exactly how to return structures in the TARGET_RETURN_IN_MEMORY | |
| 1050 target hook. */ | |
| 1051 | |
| 1052 #define DEFAULT_PCC_STRUCT_RETURN 0 | |
| 1053 | |
| 1054 #define SHMEDIA_REGS_STACK_ADJUST() \ | |
| 1055 (TARGET_SHCOMPACT && crtl->saves_all_registers \ | |
| 1056 ? (8 * (/* r28-r35 */ 8 + /* r44-r59 */ 16 + /* tr5-tr7 */ 3) \ | |
| 1057 + (TARGET_FPU_ANY ? 4 * (/* fr36 - fr63 */ 28) : 0)) \ | |
| 1058 : 0) | |
| 1059 | |
| 1060 | |
| 1061 /* Define the classes of registers for register constraints in the | |
| 1062 machine description. Also define ranges of constants. | |
| 1063 | |
| 1064 One of the classes must always be named ALL_REGS and include all hard regs. | |
| 1065 If there is more than one class, another class must be named NO_REGS | |
| 1066 and contain no registers. | |
| 1067 | |
| 1068 The name GENERAL_REGS must be the name of a class (or an alias for | |
| 1069 another name such as ALL_REGS). This is the class of registers | |
| 1070 that is allowed by "g" or "r" in a register constraint. | |
| 1071 Also, registers outside this class are allocated only when | |
| 1072 instructions express preferences for them. | |
| 1073 | |
| 1074 The classes must be numbered in nondecreasing order; that is, | |
| 1075 a larger-numbered class must never be contained completely | |
| 1076 in a smaller-numbered class. | |
| 1077 | |
| 1078 For any two classes, it is very desirable that there be another | |
| 1079 class that represents their union. */ | |
| 1080 | |
| 1081 /* The SH has two sorts of general registers, R0 and the rest. R0 can | |
| 1082 be used as the destination of some of the arithmetic ops. There are | |
| 1083 also some special purpose registers; the T bit register, the | |
| 1084 Procedure Return Register and the Multiply Accumulate Registers. */ | |
| 1085 /* Place GENERAL_REGS after FPUL_REGS so that it will be preferred by | |
| 1086 reg_class_subunion. We don't want to have an actual union class | |
| 1087 of these, because it would only be used when both classes are calculated | |
| 1088 to give the same cost, but there is only one FPUL register. | |
| 1089 Besides, regclass fails to notice the different REGISTER_MOVE_COSTS | |
| 1090 applying to the actual instruction alternative considered. E.g., the | |
| 1091 y/r alternative of movsi_ie is considered to have no more cost that | |
| 1092 the r/r alternative, which is patently untrue. */ | |
| 1093 | |
| 1094 enum reg_class | |
| 1095 { | |
| 1096 NO_REGS, | |
| 1097 R0_REGS, | |
| 1098 PR_REGS, | |
| 1099 T_REGS, | |
| 1100 MAC_REGS, | |
| 1101 FPUL_REGS, | |
| 1102 SIBCALL_REGS, | |
| 1103 GENERAL_REGS, | |
| 1104 FP0_REGS, | |
| 1105 FP_REGS, | |
| 1106 DF_HI_REGS, | |
| 1107 DF_REGS, | |
| 1108 FPSCR_REGS, | |
| 1109 GENERAL_FP_REGS, | |
| 1110 GENERAL_DF_REGS, | |
| 1111 TARGET_REGS, | |
| 1112 ALL_REGS, | |
| 1113 LIM_REG_CLASSES | |
| 1114 }; | |
| 1115 | |
| 1116 #define N_REG_CLASSES (int) LIM_REG_CLASSES | |
| 1117 | |
| 1118 /* Give names of register classes as strings for dump file. */ | |
| 1119 #define REG_CLASS_NAMES \ | |
| 1120 { \ | |
| 1121 "NO_REGS", \ | |
| 1122 "R0_REGS", \ | |
| 1123 "PR_REGS", \ | |
| 1124 "T_REGS", \ | |
| 1125 "MAC_REGS", \ | |
| 1126 "FPUL_REGS", \ | |
| 1127 "SIBCALL_REGS", \ | |
| 1128 "GENERAL_REGS", \ | |
| 1129 "FP0_REGS", \ | |
| 1130 "FP_REGS", \ | |
| 1131 "DF_HI_REGS", \ | |
| 1132 "DF_REGS", \ | |
| 1133 "FPSCR_REGS", \ | |
| 1134 "GENERAL_FP_REGS", \ | |
| 1135 "GENERAL_DF_REGS", \ | |
| 1136 "TARGET_REGS", \ | |
| 1137 "ALL_REGS", \ | |
| 1138 } | |
| 1139 | |
| 1140 /* Define which registers fit in which classes. | |
| 1141 This is an initializer for a vector of HARD_REG_SET | |
| 1142 of length N_REG_CLASSES. */ | |
| 1143 | |
| 1144 #define REG_CLASS_CONTENTS \ | |
| 1145 { \ | |
| 1146 /* NO_REGS: */ \ | |
| 1147 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, \ | |
| 1148 /* R0_REGS: */ \ | |
| 1149 { 0x00000001, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, \ | |
| 1150 /* PR_REGS: */ \ | |
| 1151 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00040000 }, \ | |
| 1152 /* T_REGS: */ \ | |
| 1153 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00080000 }, \ | |
| 1154 /* MAC_REGS: */ \ | |
| 1155 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00300000 }, \ | |
| 1156 /* FPUL_REGS: */ \ | |
| 1157 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00400000 }, \ | |
| 1158 /* SIBCALL_REGS: Initialized in CONDITIONAL_REGISTER_USAGE. */ \ | |
| 1159 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, \ | |
| 1160 /* GENERAL_REGS: */ \ | |
| 1161 { 0xffffffff, 0xffffffff, 0x00000000, 0x00000000, 0x03020000 }, \ | |
| 1162 /* FP0_REGS: */ \ | |
| 1163 { 0x00000000, 0x00000000, 0x00000001, 0x00000000, 0x00000000 }, \ | |
| 1164 /* FP_REGS: */ \ | |
| 1165 { 0x00000000, 0x00000000, 0xffffffff, 0xffffffff, 0x00000000 }, \ | |
| 1166 /* DF_HI_REGS: Initialized in CONDITIONAL_REGISTER_USAGE. */ \ | |
| 1167 { 0x00000000, 0x00000000, 0xffffffff, 0xffffffff, 0x0000ff00 }, \ | |
| 1168 /* DF_REGS: */ \ | |
| 1169 { 0x00000000, 0x00000000, 0xffffffff, 0xffffffff, 0x0000ff00 }, \ | |
| 1170 /* FPSCR_REGS: */ \ | |
| 1171 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00800000 }, \ | |
| 1172 /* GENERAL_FP_REGS: */ \ | |
| 1173 { 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0x03020000 }, \ | |
| 1174 /* GENERAL_DF_REGS: */ \ | |
| 1175 { 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0x0302ff00 }, \ | |
| 1176 /* TARGET_REGS: */ \ | |
| 1177 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x000000ff }, \ | |
| 1178 /* ALL_REGS: */ \ | |
| 1179 { 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0x03ffffff }, \ | |
| 1180 } | |
| 1181 | |
| 1182 /* The same information, inverted: | |
| 1183 Return the class number of the smallest class containing | |
| 1184 reg number REGNO. This could be a conditional expression | |
| 1185 or could index an array. */ | |
| 1186 | |
| 1187 extern enum reg_class regno_reg_class[FIRST_PSEUDO_REGISTER]; | |
| 1188 #define REGNO_REG_CLASS(REGNO) regno_reg_class[(REGNO)] | |
| 1189 | |
| 1190 /* The following macro defines cover classes for Integrated Register | |
| 1191 Allocator. Cover classes is a set of non-intersected register | |
| 1192 classes covering all hard registers used for register allocation | |
| 1193 purpose. Any move between two registers of a cover class should be | |
| 1194 cheaper than load or store of the registers. The macro value is | |
| 1195 array of register classes with LIM_REG_CLASSES used as the end | |
| 1196 marker. */ | |
| 1197 | |
| 1198 #define IRA_COVER_CLASSES \ | |
| 1199 { \ | |
| 1200 GENERAL_REGS, FP_REGS, PR_REGS, T_REGS, MAC_REGS, TARGET_REGS, \ | |
| 1201 FPUL_REGS, LIM_REG_CLASSES \ | |
| 1202 } | |
| 1203 | |
| 1204 /* When defined, the compiler allows registers explicitly used in the | |
| 1205 rtl to be used as spill registers but prevents the compiler from | |
| 1206 extending the lifetime of these registers. */ | |
| 1207 | |
| 1208 #define SMALL_REGISTER_CLASSES (! TARGET_SHMEDIA) | |
| 1209 | |
| 1210 /* The order in which register should be allocated. */ | |
| 1211 /* Sometimes FP0_REGS becomes the preferred class of a floating point pseudo, | |
| 1212 and GENERAL_FP_REGS the alternate class. Since FP0 is likely to be | |
| 1213 spilled or used otherwise, we better have the FP_REGS allocated first. */ | |
| 1214 #define REG_ALLOC_ORDER \ | |
| 1215 {/* Caller-saved FPRs */ \ | |
| 1216 65, 66, 67, 68, 69, 70, 71, 64, \ | |
| 1217 72, 73, 74, 75, 80, 81, 82, 83, \ | |
| 1218 84, 85, 86, 87, 88, 89, 90, 91, \ | |
| 1219 92, 93, 94, 95, 96, 97, 98, 99, \ | |
| 1220 /* Callee-saved FPRs */ \ | |
| 1221 76, 77, 78, 79,100,101,102,103, \ | |
| 1222 104,105,106,107,108,109,110,111, \ | |
| 1223 112,113,114,115,116,117,118,119, \ | |
| 1224 120,121,122,123,124,125,126,127, \ | |
| 1225 136,137,138,139,140,141,142,143, \ | |
| 1226 /* FPSCR */ 151, \ | |
| 1227 /* Caller-saved GPRs (except 8/9 on SH1-4) */ \ | |
| 1228 1, 2, 3, 7, 6, 5, 4, 0, \ | |
| 1229 8, 9, 17, 19, 20, 21, 22, 23, \ | |
| 1230 36, 37, 38, 39, 40, 41, 42, 43, \ | |
| 1231 60, 61, 62, \ | |
| 1232 /* SH1-4 callee-saved saved GPRs / SH5 partially-saved GPRs */ \ | |
| 1233 10, 11, 12, 13, 14, 18, \ | |
| 1234 /* SH5 callee-saved GPRs */ \ | |
| 1235 28, 29, 30, 31, 32, 33, 34, 35, \ | |
| 1236 44, 45, 46, 47, 48, 49, 50, 51, \ | |
| 1237 52, 53, 54, 55, 56, 57, 58, 59, \ | |
| 1238 /* FPUL */ 150, \ | |
| 1239 /* SH5 branch target registers */ \ | |
| 1240 128,129,130,131,132,133,134,135, \ | |
| 1241 /* Fixed registers */ \ | |
| 1242 15, 16, 24, 25, 26, 27, 63,144, \ | |
| 1243 145,146,147,148,149,152,153 } | |
| 1244 | |
| 1245 /* The class value for index registers, and the one for base regs. */ | |
| 1246 #define INDEX_REG_CLASS \ | |
| 1247 (!ALLOW_INDEXED_ADDRESS ? NO_REGS : TARGET_SHMEDIA ? GENERAL_REGS : R0_REGS) | |
| 1248 #define BASE_REG_CLASS GENERAL_REGS | |
| 1249 | |
| 1250 /* Defines for sh.md and constraints.md. */ | |
| 1251 | |
| 1252 #define CONST_OK_FOR_I06(VALUE) (((HOST_WIDE_INT)(VALUE)) >= -32 \ | |
| 1253 && ((HOST_WIDE_INT)(VALUE)) <= 31) | |
| 1254 #define CONST_OK_FOR_I08(VALUE) (((HOST_WIDE_INT)(VALUE))>= -128 \ | |
| 1255 && ((HOST_WIDE_INT)(VALUE)) <= 127) | |
| 1256 #define CONST_OK_FOR_I10(VALUE) (((HOST_WIDE_INT)(VALUE)) >= -512 \ | |
| 1257 && ((HOST_WIDE_INT)(VALUE)) <= 511) | |
| 1258 #define CONST_OK_FOR_I16(VALUE) (((HOST_WIDE_INT)(VALUE)) >= -32768 \ | |
| 1259 && ((HOST_WIDE_INT)(VALUE)) <= 32767) | |
| 1260 | |
| 1261 #define CONST_OK_FOR_J16(VALUE) \ | |
| 1262 ((HOST_BITS_PER_WIDE_INT >= 64 && (VALUE) == (HOST_WIDE_INT) 0xffffffff) \ | |
| 1263 || (HOST_BITS_PER_WIDE_INT >= 64 && (VALUE) == (HOST_WIDE_INT) -1 << 32)) | |
| 1264 | |
| 1265 #define CONST_OK_FOR_K08(VALUE) (((HOST_WIDE_INT)(VALUE))>= 0 \ | |
| 1266 && ((HOST_WIDE_INT)(VALUE)) <= 255) | |
| 1267 | |
| 1268 /* Given an rtx X being reloaded into a reg required to be | |
| 1269 in class CLASS, return the class of reg to actually use. | |
| 1270 In general this is just CLASS; but on some machines | |
| 1271 in some cases it is preferable to use a more restrictive class. */ | |
| 1272 | |
| 1273 #define PREFERRED_RELOAD_CLASS(X, CLASS) \ | |
| 1274 ((CLASS) == NO_REGS && TARGET_SHMEDIA \ | |
| 1275 && (GET_CODE (X) == CONST_DOUBLE \ | |
| 1276 || GET_CODE (X) == SYMBOL_REF \ | |
| 1277 || PIC_ADDR_P (X)) \ | |
| 1278 ? GENERAL_REGS \ | |
| 1279 : (CLASS)) \ | |
| 1280 | |
| 1281 #if 0 | |
| 1282 #define SECONDARY_INOUT_RELOAD_CLASS(CLASS,MODE,X,ELSE) \ | |
| 1283 ((((REGCLASS_HAS_FP_REG (CLASS) \ | |
|
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1284 && (REG_P (X) \ |
| 0 | 1285 && (GENERAL_OR_AP_REGISTER_P (REGNO (X)) \ |
| 1286 || (FP_REGISTER_P (REGNO (X)) && (MODE) == SImode \ | |
| 1287 && TARGET_FMOVD)))) \ | |
| 1288 || (REGCLASS_HAS_GENERAL_REG (CLASS) \ | |
|
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1289 && REG_P (X) \ |
| 0 | 1290 && FP_REGISTER_P (REGNO (X)))) \ |
| 1291 && ! TARGET_SHMEDIA \ | |
| 1292 && ((MODE) == SFmode || (MODE) == SImode)) \ | |
| 1293 ? FPUL_REGS \ | |
| 1294 : (((CLASS) == FPUL_REGS \ | |
| 1295 || (REGCLASS_HAS_FP_REG (CLASS) \ | |
| 1296 && ! TARGET_SHMEDIA && MODE == SImode)) \ | |
|
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1297 && (MEM_P (X) \ |
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1298 || (REG_P (X) \ |
| 0 | 1299 && (REGNO (X) >= FIRST_PSEUDO_REGISTER \ |
| 1300 || REGNO (X) == T_REG \ | |
| 1301 || system_reg_operand (X, VOIDmode))))) \ | |
| 1302 ? GENERAL_REGS \ | |
| 1303 : (((CLASS) == TARGET_REGS \ | |
| 1304 || (TARGET_SHMEDIA && (CLASS) == SIBCALL_REGS)) \ | |
| 1305 && !satisfies_constraint_Csy (X) \ | |
|
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1306 && (!REG_P (X) || ! GENERAL_REGISTER_P (REGNO (X)))) \ |
| 0 | 1307 ? GENERAL_REGS \ |
| 1308 : (((CLASS) == MAC_REGS || (CLASS) == PR_REGS) \ | |
|
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1309 && REG_P (X) && ! GENERAL_REGISTER_P (REGNO (X)) \ |
| 0 | 1310 && (CLASS) != REGNO_REG_CLASS (REGNO (X))) \ |
| 1311 ? GENERAL_REGS \ | |
|
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1312 : ((CLASS) != GENERAL_REGS && REG_P (X) \ |
| 0 | 1313 && TARGET_REGISTER_P (REGNO (X))) \ |
| 1314 ? GENERAL_REGS : (ELSE)) | |
| 1315 | |
| 1316 #define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS,MODE,X) \ | |
| 1317 SECONDARY_INOUT_RELOAD_CLASS(CLASS,MODE,X,NO_REGS) | |
| 1318 | |
| 1319 #define SECONDARY_INPUT_RELOAD_CLASS(CLASS,MODE,X) \ | |
| 1320 ((REGCLASS_HAS_FP_REG (CLASS) \ | |
| 1321 && ! TARGET_SHMEDIA \ | |
| 1322 && immediate_operand ((X), (MODE)) \ | |
| 1323 && ! ((fp_zero_operand (X) || fp_one_operand (X)) \ | |
| 1324 && (MODE) == SFmode && fldi_ok ())) \ | |
| 1325 ? R0_REGS \ | |
| 1326 : ((CLASS) == FPUL_REGS \ | |
|
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1327 && ((REG_P (X) \ |
| 0 | 1328 && (REGNO (X) == MACL_REG || REGNO (X) == MACH_REG \ |
| 1329 || REGNO (X) == T_REG)) \ | |
| 1330 || GET_CODE (X) == PLUS)) \ | |
| 1331 ? GENERAL_REGS \ | |
| 1332 : (CLASS) == FPUL_REGS && immediate_operand ((X), (MODE)) \ | |
| 1333 ? (satisfies_constraint_I08 (X) \ | |
| 1334 ? GENERAL_REGS \ | |
| 1335 : R0_REGS) \ | |
| 1336 : ((CLASS) == FPSCR_REGS \ | |
|
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1337 && ((REG_P (X) && REGNO (X) >= FIRST_PSEUDO_REGISTER) \ |
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1338 || (MEM_P (X) && GET_CODE (XEXP ((X), 0)) == PLUS))) \ |
| 0 | 1339 ? GENERAL_REGS \ |
| 1340 : (REGCLASS_HAS_FP_REG (CLASS) \ | |
| 1341 && TARGET_SHMEDIA \ | |
| 1342 && immediate_operand ((X), (MODE)) \ | |
| 1343 && (X) != CONST0_RTX (GET_MODE (X)) \ | |
| 1344 && GET_MODE (X) != V4SFmode) \ | |
| 1345 ? GENERAL_REGS \ | |
| 1346 : (((MODE) == QImode || (MODE) == HImode) \ | |
| 1347 && TARGET_SHMEDIA && inqhi_operand ((X), (MODE))) \ | |
| 1348 ? GENERAL_REGS \ | |
| 1349 : (TARGET_SHMEDIA && (CLASS) == GENERAL_REGS \ | |
| 1350 && (GET_CODE (X) == LABEL_REF || PIC_ADDR_P (X))) \ | |
| 1351 ? TARGET_REGS \ | |
| 1352 : SECONDARY_INOUT_RELOAD_CLASS((CLASS),(MODE),(X), NO_REGS)) | |
| 1353 #endif | |
| 1354 | |
| 1355 /* Return the maximum number of consecutive registers | |
| 1356 needed to represent mode MODE in a register of class CLASS. | |
| 1357 | |
| 1358 If TARGET_SHMEDIA, we need two FP registers per word. | |
| 1359 Otherwise we will need at most one register per word. */ | |
| 1360 #define CLASS_MAX_NREGS(CLASS, MODE) \ | |
| 1361 (TARGET_SHMEDIA \ | |
| 1362 && TEST_HARD_REG_BIT (reg_class_contents[CLASS], FIRST_FP_REG) \ | |
| 1363 ? (GET_MODE_SIZE (MODE) + UNITS_PER_WORD/2 - 1) / (UNITS_PER_WORD/2) \ | |
| 1364 : (GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD) | |
| 1365 | |
| 1366 /* If defined, gives a class of registers that cannot be used as the | |
| 1367 operand of a SUBREG that changes the mode of the object illegally. */ | |
| 1368 /* ??? We need to renumber the internal numbers for the frnn registers | |
| 1369 when in little endian in order to allow mode size changes. */ | |
| 1370 | |
| 1371 #define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS) \ | |
| 1372 sh_cannot_change_mode_class (FROM, TO, CLASS) | |
| 1373 | |
| 1374 /* Stack layout; function entry, exit and calling. */ | |
| 1375 | |
| 1376 /* Define the number of registers that can hold parameters. | |
| 1377 These macros are used only in other macro definitions below. */ | |
| 1378 | |
| 1379 #define NPARM_REGS(MODE) \ | |
| 1380 (TARGET_FPU_ANY && (MODE) == SFmode \ | |
| 1381 ? (TARGET_SH5 ? 12 : 8) \ | |
| 1382 : (TARGET_SH4 || TARGET_SH2A_DOUBLE) && (GET_MODE_CLASS (MODE) == MODE_FLOAT \ | |
| 1383 || GET_MODE_CLASS (MODE) == MODE_COMPLEX_FLOAT) \ | |
| 1384 ? (TARGET_SH5 ? 12 : 8) \ | |
| 1385 : (TARGET_SH5 ? 8 : 4)) | |
| 1386 | |
| 1387 #define FIRST_PARM_REG (FIRST_GENERAL_REG + (TARGET_SH5 ? 2 : 4)) | |
| 1388 #define FIRST_RET_REG (FIRST_GENERAL_REG + (TARGET_SH5 ? 2 : 0)) | |
| 1389 | |
| 1390 #define FIRST_FP_PARM_REG (FIRST_FP_REG + (TARGET_SH5 ? 0 : 4)) | |
| 1391 #define FIRST_FP_RET_REG FIRST_FP_REG | |
| 1392 | |
| 1393 /* Define this if pushing a word on the stack | |
| 1394 makes the stack pointer a smaller address. */ | |
| 1395 #define STACK_GROWS_DOWNWARD | |
| 1396 | |
| 1397 /* Define this macro to nonzero if the addresses of local variable slots | |
| 1398 are at negative offsets from the frame pointer. */ | |
| 1399 #define FRAME_GROWS_DOWNWARD 1 | |
| 1400 | |
| 1401 /* Offset from the frame pointer to the first local variable slot to | |
| 1402 be allocated. */ | |
| 1403 #define STARTING_FRAME_OFFSET 0 | |
| 1404 | |
| 1405 /* If we generate an insn to push BYTES bytes, | |
| 1406 this says how many the stack pointer really advances by. */ | |
| 1407 /* Don't define PUSH_ROUNDING, since the hardware doesn't do this. | |
| 1408 When PUSH_ROUNDING is not defined, PARM_BOUNDARY will cause gcc to | |
| 1409 do correct alignment. */ | |
| 1410 #if 0 | |
| 1411 #define PUSH_ROUNDING(NPUSHED) (((NPUSHED) + 3) & ~3) | |
| 1412 #endif | |
| 1413 | |
| 1414 /* Offset of first parameter from the argument pointer register value. */ | |
| 1415 #define FIRST_PARM_OFFSET(FNDECL) 0 | |
| 1416 | |
| 1417 /* Value is the number of byte of arguments automatically | |
| 1418 popped when returning from a subroutine call. | |
| 1419 FUNDECL is the declaration node of the function (as a tree), | |
| 1420 FUNTYPE is the data type of the function (as a tree), | |
| 1421 or for a library call it is an identifier node for the subroutine name. | |
| 1422 SIZE is the number of bytes of arguments passed on the stack. | |
| 1423 | |
| 1424 On the SH, the caller does not pop any of its arguments that were passed | |
| 1425 on the stack. */ | |
| 1426 #define RETURN_POPS_ARGS(FUNDECL,FUNTYPE,SIZE) 0 | |
| 1427 | |
| 1428 /* Value is the number of bytes of arguments automatically popped when | |
| 1429 calling a subroutine. | |
| 1430 CUM is the accumulated argument list. | |
| 1431 | |
| 1432 On SHcompact, the call trampoline pops arguments off the stack. */ | |
| 1433 #define CALL_POPS_ARGS(CUM) (TARGET_SHCOMPACT ? (CUM).stack_regs * 8 : 0) | |
| 1434 | |
| 1435 /* Some subroutine macros specific to this machine. */ | |
| 1436 | |
| 1437 #define BASE_RETURN_VALUE_REG(MODE) \ | |
| 1438 ((TARGET_FPU_ANY && ((MODE) == SFmode)) \ | |
| 1439 ? FIRST_FP_RET_REG \ | |
| 1440 : TARGET_FPU_ANY && (MODE) == SCmode \ | |
| 1441 ? FIRST_FP_RET_REG \ | |
| 1442 : (TARGET_FPU_DOUBLE \ | |
| 1443 && ((MODE) == DFmode || (MODE) == SFmode \ | |
| 1444 || (MODE) == DCmode || (MODE) == SCmode )) \ | |
| 1445 ? FIRST_FP_RET_REG \ | |
| 1446 : FIRST_RET_REG) | |
| 1447 | |
| 1448 #define BASE_ARG_REG(MODE) \ | |
| 1449 ((TARGET_SH2E && ((MODE) == SFmode)) \ | |
| 1450 ? FIRST_FP_PARM_REG \ | |
| 1451 : (TARGET_SH4 || TARGET_SH2A_DOUBLE) && (GET_MODE_CLASS (MODE) == MODE_FLOAT \ | |
| 1452 || GET_MODE_CLASS (MODE) == MODE_COMPLEX_FLOAT)\ | |
| 1453 ? FIRST_FP_PARM_REG \ | |
| 1454 : FIRST_PARM_REG) | |
| 1455 | |
|
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1456 #define FUNCTION_VALUE_REGNO_P(REGNO) sh_function_value_regno_p (REGNO) |
| 0 | 1457 |
| 1458 /* 1 if N is a possible register number for function argument passing. */ | |
| 1459 /* ??? There are some callers that pass REGNO as int, and others that pass | |
| 1460 it as unsigned. We get warnings unless we do casts everywhere. */ | |
| 1461 #define FUNCTION_ARG_REGNO_P(REGNO) \ | |
| 1462 (((unsigned) (REGNO) >= (unsigned) FIRST_PARM_REG \ | |
| 1463 && (unsigned) (REGNO) < (unsigned) (FIRST_PARM_REG + NPARM_REGS (SImode)))\ | |
| 1464 || (TARGET_FPU_ANY \ | |
| 1465 && (unsigned) (REGNO) >= (unsigned) FIRST_FP_PARM_REG \ | |
| 1466 && (unsigned) (REGNO) < (unsigned) (FIRST_FP_PARM_REG \ | |
| 1467 + NPARM_REGS (SFmode)))) | |
| 1468 | |
| 1469 /* Define a data type for recording info about an argument list | |
| 1470 during the scan of that argument list. This data type should | |
| 1471 hold all necessary information about the function itself | |
| 1472 and about the args processed so far, enough to enable macros | |
| 1473 such as FUNCTION_ARG to determine where the next arg should go. | |
| 1474 | |
| 1475 On SH, this is a single integer, which is a number of words | |
| 1476 of arguments scanned so far (including the invisible argument, | |
| 1477 if any, which holds the structure-value-address). | |
| 1478 Thus NARGREGS or more means all following args should go on the stack. */ | |
| 1479 | |
| 1480 enum sh_arg_class { SH_ARG_INT = 0, SH_ARG_FLOAT = 1 }; | |
| 1481 struct sh_args { | |
| 1482 int arg_count[2]; | |
| 1483 int force_mem; | |
| 1484 /* Nonzero if a prototype is available for the function. */ | |
| 1485 int prototype_p; | |
| 1486 /* The number of an odd floating-point register, that should be used | |
| 1487 for the next argument of type float. */ | |
| 1488 int free_single_fp_reg; | |
| 1489 /* Whether we're processing an outgoing function call. */ | |
| 1490 int outgoing; | |
| 1491 /* The number of general-purpose registers that should have been | |
| 1492 used to pass partial arguments, that are passed totally on the | |
| 1493 stack. On SHcompact, a call trampoline will pop them off the | |
| 1494 stack before calling the actual function, and, if the called | |
| 1495 function is implemented in SHcompact mode, the incoming arguments | |
| 1496 decoder will push such arguments back onto the stack. For | |
| 1497 incoming arguments, STACK_REGS also takes into account other | |
| 1498 arguments passed by reference, that the decoder will also push | |
| 1499 onto the stack. */ | |
| 1500 int stack_regs; | |
| 1501 /* The number of general-purpose registers that should have been | |
| 1502 used to pass arguments, if the arguments didn't have to be passed | |
| 1503 by reference. */ | |
| 1504 int byref_regs; | |
| 1505 /* Set as by shcompact_byref if the current argument is to be passed | |
| 1506 by reference. */ | |
| 1507 int byref; | |
| 1508 | |
| 1509 /* call_cookie is a bitmask used by call expanders, as well as | |
| 1510 function prologue and epilogues, to allow SHcompact to comply | |
| 1511 with the SH5 32-bit ABI, that requires 64-bit registers to be | |
| 1512 used even though only the lower 32-bit half is visible in | |
| 1513 SHcompact mode. The strategy is to call SHmedia trampolines. | |
| 1514 | |
| 1515 The alternatives for each of the argument-passing registers are | |
| 1516 (a) leave it unchanged; (b) pop it off the stack; (c) load its | |
| 1517 contents from the address in it; (d) add 8 to it, storing the | |
| 1518 result in the next register, then (c); (e) copy it from some | |
| 1519 floating-point register, | |
| 1520 | |
| 1521 Regarding copies from floating-point registers, r2 may only be | |
| 1522 copied from dr0. r3 may be copied from dr0 or dr2. r4 maybe | |
| 1523 copied from dr0, dr2 or dr4. r5 maybe copied from dr0, dr2, | |
| 1524 dr4 or dr6. r6 may be copied from dr0, dr2, dr4, dr6 or dr8. | |
| 1525 r7 through to r9 may be copied from dr0, dr2, dr4, dr8, dr8 or | |
| 1526 dr10. | |
| 1527 | |
| 1528 The bit mask is structured as follows: | |
| 1529 | |
| 1530 - 1 bit to tell whether to set up a return trampoline. | |
| 1531 | |
| 1532 - 3 bits to count the number consecutive registers to pop off the | |
| 1533 stack. | |
| 1534 | |
| 1535 - 4 bits for each of r9, r8, r7 and r6. | |
| 1536 | |
| 1537 - 3 bits for each of r5, r4, r3 and r2. | |
| 1538 | |
| 1539 - 3 bits set to 0 (the most significant ones) | |
| 1540 | |
| 1541 3 2 1 0 | |
| 1542 1098 7654 3210 9876 5432 1098 7654 3210 | |
| 1543 FLPF LPFL PFLP FFLP FFLP FFLP FFLP SSST | |
| 1544 2223 3344 4555 6666 7777 8888 9999 SSS- | |
| 1545 | |
| 1546 - If F is set, the register must be copied from an FP register, | |
| 1547 whose number is encoded in the remaining bits. | |
| 1548 | |
| 1549 - Else, if L is set, the register must be loaded from the address | |
| 1550 contained in it. If the P bit is *not* set, the address of the | |
| 1551 following dword should be computed first, and stored in the | |
| 1552 following register. | |
| 1553 | |
| 1554 - Else, if P is set, the register alone should be popped off the | |
| 1555 stack. | |
| 1556 | |
| 1557 - After all this processing, the number of registers represented | |
| 1558 in SSS will be popped off the stack. This is an optimization | |
| 1559 for pushing/popping consecutive registers, typically used for | |
| 1560 varargs and large arguments partially passed in registers. | |
| 1561 | |
| 1562 - If T is set, a return trampoline will be set up for 64-bit | |
| 1563 return values to be split into 2 32-bit registers. */ | |
| 1564 long call_cookie; | |
| 1565 | |
| 1566 /* This is set to nonzero when the call in question must use the Renesas ABI, | |
| 1567 even without the -mrenesas option. */ | |
| 1568 int renesas_abi; | |
| 1569 }; | |
| 1570 | |
| 1571 #define CALL_COOKIE_RET_TRAMP_SHIFT 0 | |
| 1572 #define CALL_COOKIE_RET_TRAMP(VAL) ((VAL) << CALL_COOKIE_RET_TRAMP_SHIFT) | |
| 1573 #define CALL_COOKIE_STACKSEQ_SHIFT 1 | |
| 1574 #define CALL_COOKIE_STACKSEQ(VAL) ((VAL) << CALL_COOKIE_STACKSEQ_SHIFT) | |
| 1575 #define CALL_COOKIE_STACKSEQ_GET(COOKIE) \ | |
| 1576 (((COOKIE) >> CALL_COOKIE_STACKSEQ_SHIFT) & 7) | |
| 1577 #define CALL_COOKIE_INT_REG_SHIFT(REG) \ | |
| 1578 (4 * (7 - (REG)) + (((REG) <= 2) ? ((REG) - 2) : 1) + 3) | |
| 1579 #define CALL_COOKIE_INT_REG(REG, VAL) \ | |
| 1580 ((VAL) << CALL_COOKIE_INT_REG_SHIFT (REG)) | |
| 1581 #define CALL_COOKIE_INT_REG_GET(COOKIE, REG) \ | |
| 1582 (((COOKIE) >> CALL_COOKIE_INT_REG_SHIFT (REG)) & ((REG) < 4 ? 7 : 15)) | |
| 1583 | |
| 1584 #define CUMULATIVE_ARGS struct sh_args | |
| 1585 | |
| 1586 #define GET_SH_ARG_CLASS(MODE) \ | |
| 1587 ((TARGET_FPU_ANY && (MODE) == SFmode) \ | |
| 1588 ? SH_ARG_FLOAT \ | |
| 1589 /* There's no mention of complex float types in the SH5 ABI, so we | |
| 1590 should presumably handle them as aggregate types. */ \ | |
| 1591 : TARGET_SH5 && GET_MODE_CLASS (MODE) == MODE_COMPLEX_FLOAT \ | |
| 1592 ? SH_ARG_INT \ | |
| 1593 : TARGET_FPU_DOUBLE && (GET_MODE_CLASS (MODE) == MODE_FLOAT \ | |
| 1594 || GET_MODE_CLASS (MODE) == MODE_COMPLEX_FLOAT) \ | |
| 1595 ? SH_ARG_FLOAT : SH_ARG_INT) | |
| 1596 | |
| 1597 #define ROUND_ADVANCE(SIZE) \ | |
| 1598 (((SIZE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD) | |
| 1599 | |
| 1600 /* Round a register number up to a proper boundary for an arg of mode | |
| 1601 MODE. | |
| 1602 | |
| 1603 The SH doesn't care about double alignment, so we only | |
| 1604 round doubles to even regs when asked to explicitly. */ | |
| 1605 | |
| 1606 #define ROUND_REG(CUM, MODE) \ | |
| 1607 (((TARGET_ALIGN_DOUBLE \ | |
| 1608 || ((TARGET_SH4 || TARGET_SH2A_DOUBLE) && ((MODE) == DFmode || (MODE) == DCmode) \ | |
| 1609 && (CUM).arg_count[(int) SH_ARG_FLOAT] < NPARM_REGS (MODE)))\ | |
| 1610 && GET_MODE_UNIT_SIZE ((MODE)) > UNITS_PER_WORD) \ | |
| 1611 ? ((CUM).arg_count[(int) GET_SH_ARG_CLASS (MODE)] \ | |
| 1612 + ((CUM).arg_count[(int) GET_SH_ARG_CLASS (MODE)] & 1)) \ | |
| 1613 : (CUM).arg_count[(int) GET_SH_ARG_CLASS (MODE)]) | |
| 1614 | |
| 1615 /* Initialize a variable CUM of type CUMULATIVE_ARGS | |
| 1616 for a call to a function whose data type is FNTYPE. | |
| 1617 For a library call, FNTYPE is 0. | |
| 1618 | |
| 1619 On SH, the offset always starts at 0: the first parm reg is always | |
| 1620 the same reg for a given argument class. | |
| 1621 | |
| 1622 For TARGET_HITACHI, the structure value pointer is passed in memory. */ | |
| 1623 | |
| 1624 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, FNDECL, N_NAMED_ARGS) \ | |
| 1625 sh_init_cumulative_args (& (CUM), (FNTYPE), (LIBNAME), (FNDECL), (N_NAMED_ARGS), VOIDmode) | |
| 1626 | |
| 1627 #define INIT_CUMULATIVE_LIBCALL_ARGS(CUM, MODE, LIBNAME) \ | |
| 1628 sh_init_cumulative_args (& (CUM), NULL_TREE, (LIBNAME), NULL_TREE, 0, (MODE)) | |
| 1629 | |
| 1630 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \ | |
| 1631 sh_function_arg_advance (&(CUM), (MODE), (TYPE), (NAMED)) | |
| 1632 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \ | |
| 1633 sh_function_arg (&(CUM), (MODE), (TYPE), (NAMED)) | |
| 1634 | |
| 1635 /* Return boolean indicating arg of mode MODE will be passed in a reg. | |
| 1636 This macro is only used in this file. */ | |
| 1637 | |
| 1638 #define PASS_IN_REG_P(CUM, MODE, TYPE) \ | |
| 1639 (((TYPE) == 0 \ | |
| 1640 || (! TREE_ADDRESSABLE ((tree)(TYPE)) \ | |
| 1641 && (! (TARGET_HITACHI || (CUM).renesas_abi) \ | |
| 1642 || ! (AGGREGATE_TYPE_P (TYPE) \ | |
| 1643 || (!TARGET_FPU_ANY \ | |
| 1644 && (GET_MODE_CLASS (MODE) == MODE_FLOAT \ | |
| 1645 && GET_MODE_SIZE (MODE) > GET_MODE_SIZE (SFmode))))))) \ | |
| 1646 && ! (CUM).force_mem \ | |
| 1647 && (TARGET_SH2E \ | |
| 1648 ? ((MODE) == BLKmode \ | |
| 1649 ? (((CUM).arg_count[(int) SH_ARG_INT] * UNITS_PER_WORD \ | |
| 1650 + int_size_in_bytes (TYPE)) \ | |
| 1651 <= NPARM_REGS (SImode) * UNITS_PER_WORD) \ | |
| 1652 : ((ROUND_REG((CUM), (MODE)) \ | |
| 1653 + HARD_REGNO_NREGS (BASE_ARG_REG (MODE), (MODE))) \ | |
| 1654 <= NPARM_REGS (MODE))) \ | |
| 1655 : ROUND_REG ((CUM), (MODE)) < NPARM_REGS (MODE))) | |
| 1656 | |
| 1657 /* By accident we got stuck with passing SCmode on SH4 little endian | |
| 1658 in two registers that are nominally successive - which is different from | |
| 1659 two single SFmode values, where we take endianness translation into | |
| 1660 account. That does not work at all if an odd number of registers is | |
| 1661 already in use, so that got fixed, but library functions are still more | |
| 1662 likely to use complex numbers without mixing them with SFmode arguments | |
| 1663 (which in C would have to be structures), so for the sake of ABI | |
| 1664 compatibility the way SCmode values are passed when an even number of | |
| 1665 FP registers is in use remains different from a pair of SFmode values for | |
| 1666 now. | |
| 1667 I.e.: | |
| 1668 foo (double); a: fr5,fr4 | |
| 1669 foo (float a, float b); a: fr5 b: fr4 | |
| 1670 foo (__complex float a); a.real fr4 a.imag: fr5 - for consistency, | |
| 1671 this should be the other way round... | |
| 1672 foo (float a, __complex float b); a: fr5 b.real: fr4 b.imag: fr7 */ | |
| 1673 #define FUNCTION_ARG_SCmode_WART 1 | |
| 1674 | |
| 1675 /* If an argument of size 5, 6 or 7 bytes is to be passed in a 64-bit | |
| 1676 register in SHcompact mode, it must be padded in the most | |
| 1677 significant end. This means that passing it by reference wouldn't | |
| 1678 pad properly on a big-endian machine. In this particular case, we | |
| 1679 pass this argument on the stack, in a way that the call trampoline | |
| 1680 will load its value into the appropriate register. */ | |
| 1681 #define SHCOMPACT_FORCE_ON_STACK(MODE,TYPE) \ | |
| 1682 ((MODE) == BLKmode \ | |
| 1683 && TARGET_SHCOMPACT \ | |
| 1684 && ! TARGET_LITTLE_ENDIAN \ | |
| 1685 && int_size_in_bytes (TYPE) > 4 \ | |
| 1686 && int_size_in_bytes (TYPE) < 8) | |
| 1687 | |
| 1688 /* Minimum alignment for an argument to be passed by callee-copy | |
| 1689 reference. We need such arguments to be aligned to 8 byte | |
| 1690 boundaries, because they'll be loaded using quad loads. */ | |
| 1691 #define SH_MIN_ALIGN_FOR_CALLEE_COPY (8 * BITS_PER_UNIT) | |
| 1692 | |
| 1693 /* The SH5 ABI requires floating-point arguments to be passed to | |
| 1694 functions without a prototype in both an FP register and a regular | |
| 1695 register or the stack. When passing the argument in both FP and | |
| 1696 general-purpose registers, list the FP register first. */ | |
| 1697 #define SH5_PROTOTYPELESS_FLOAT_ARG(CUM,MODE) \ | |
| 1698 (gen_rtx_PARALLEL \ | |
| 1699 ((MODE), \ | |
| 1700 gen_rtvec (2, \ | |
| 1701 gen_rtx_EXPR_LIST \ | |
| 1702 (VOIDmode, \ | |
| 1703 ((CUM).arg_count[(int) SH_ARG_INT] < NPARM_REGS (SImode) \ | |
| 1704 ? gen_rtx_REG ((MODE), FIRST_FP_PARM_REG \ | |
| 1705 + (CUM).arg_count[(int) SH_ARG_FLOAT]) \ | |
| 1706 : NULL_RTX), \ | |
| 1707 const0_rtx), \ | |
| 1708 gen_rtx_EXPR_LIST \ | |
| 1709 (VOIDmode, \ | |
| 1710 ((CUM).arg_count[(int) SH_ARG_INT] < NPARM_REGS (SImode) \ | |
| 1711 ? gen_rtx_REG ((MODE), FIRST_PARM_REG \ | |
| 1712 + (CUM).arg_count[(int) SH_ARG_INT]) \ | |
| 1713 : gen_rtx_REG ((MODE), FIRST_FP_PARM_REG \ | |
| 1714 + (CUM).arg_count[(int) SH_ARG_FLOAT])), \ | |
| 1715 const0_rtx)))) | |
| 1716 | |
| 1717 /* The SH5 ABI requires regular registers or stack slots to be | |
| 1718 reserved for floating-point arguments. Registers are taken care of | |
| 1719 in FUNCTION_ARG_ADVANCE, but stack slots must be reserved here. | |
| 1720 Unfortunately, there's no way to just reserve a stack slot, so | |
| 1721 we'll end up needlessly storing a copy of the argument in the | |
| 1722 stack. For incoming arguments, however, the PARALLEL will be | |
| 1723 optimized to the register-only form, and the value in the stack | |
| 1724 slot won't be used at all. */ | |
| 1725 #define SH5_PROTOTYPED_FLOAT_ARG(CUM,MODE,REG) \ | |
| 1726 ((CUM).arg_count[(int) SH_ARG_INT] < NPARM_REGS (SImode) \ | |
| 1727 ? gen_rtx_REG ((MODE), (REG)) \ | |
| 1728 : gen_rtx_PARALLEL ((MODE), \ | |
| 1729 gen_rtvec (2, \ | |
| 1730 gen_rtx_EXPR_LIST \ | |
| 1731 (VOIDmode, NULL_RTX, \ | |
| 1732 const0_rtx), \ | |
| 1733 gen_rtx_EXPR_LIST \ | |
| 1734 (VOIDmode, gen_rtx_REG ((MODE), \ | |
| 1735 (REG)), \ | |
| 1736 const0_rtx)))) | |
| 1737 | |
| 1738 #define SH5_WOULD_BE_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) \ | |
| 1739 (TARGET_SH5 \ | |
| 1740 && ((MODE) == BLKmode || (MODE) == TImode || (MODE) == CDImode \ | |
| 1741 || (MODE) == DCmode) \ | |
| 1742 && ((CUM).arg_count[(int) SH_ARG_INT] \ | |
| 1743 + (((MODE) == BLKmode ? int_size_in_bytes (TYPE) \ | |
| 1744 : GET_MODE_SIZE (MODE)) \ | |
| 1745 + 7) / 8) > NPARM_REGS (SImode)) | |
| 1746 | |
| 1747 /* Perform any needed actions needed for a function that is receiving a | |
| 1748 variable number of arguments. */ | |
| 1749 | |
| 1750 /* Call the function profiler with a given profile label. | |
| 1751 We use two .aligns, so as to make sure that both the .long is aligned | |
| 1752 on a 4 byte boundary, and that the .long is a fixed distance (2 bytes) | |
| 1753 from the trapa instruction. */ | |
| 1754 | |
| 1755 #define FUNCTION_PROFILER(STREAM,LABELNO) \ | |
| 1756 { \ | |
| 1757 if (TARGET_SHMEDIA) \ | |
| 1758 { \ | |
| 1759 fprintf((STREAM), "\tmovi\t33,r0\n"); \ | |
| 1760 fprintf((STREAM), "\ttrapa\tr0\n"); \ | |
| 1761 asm_fprintf((STREAM), "\t.long\t%LLP%d\n", (LABELNO)); \ | |
| 1762 } \ | |
| 1763 else \ | |
| 1764 { \ | |
| 1765 fprintf((STREAM), "\t.align\t2\n"); \ | |
| 1766 fprintf((STREAM), "\ttrapa\t#33\n"); \ | |
| 1767 fprintf((STREAM), "\t.align\t2\n"); \ | |
| 1768 asm_fprintf((STREAM), "\t.long\t%LLP%d\n", (LABELNO)); \ | |
| 1769 } \ | |
| 1770 } | |
| 1771 | |
| 1772 /* Define this macro if the code for function profiling should come | |
| 1773 before the function prologue. Normally, the profiling code comes | |
| 1774 after. */ | |
| 1775 | |
| 1776 #define PROFILE_BEFORE_PROLOGUE | |
| 1777 | |
| 1778 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function, | |
| 1779 the stack pointer does not matter. The value is tested only in | |
| 1780 functions that have frame pointers. | |
| 1781 No definition is equivalent to always zero. */ | |
| 1782 | |
| 1783 #define EXIT_IGNORE_STACK 1 | |
| 1784 | |
| 1785 /* | |
| 1786 On the SH, the trampoline looks like | |
| 1787 2 0002 D202 mov.l l2,r2 | |
| 1788 1 0000 D301 mov.l l1,r3 | |
| 1789 3 0004 422B jmp @r2 | |
| 1790 4 0006 0009 nop | |
| 1791 5 0008 00000000 l1: .long area | |
| 1792 6 000c 00000000 l2: .long function */ | |
| 1793 | |
| 1794 /* Length in units of the trampoline for entering a nested function. */ | |
| 1795 #define TRAMPOLINE_SIZE (TARGET_SHMEDIA64 ? 40 : TARGET_SH5 ? 24 : 16) | |
| 1796 | |
| 1797 /* Alignment required for a trampoline in bits . */ | |
| 1798 #define TRAMPOLINE_ALIGNMENT \ | |
| 1799 ((CACHE_LOG < 3 || (TARGET_SMALLCODE && ! TARGET_HARVARD)) ? 32 \ | |
| 1800 : TARGET_SHMEDIA ? 256 : 64) | |
| 1801 | |
| 1802 /* A C expression whose value is RTL representing the value of the return | |
| 1803 address for the frame COUNT steps up from the current frame. | |
| 1804 FRAMEADDR is already the frame pointer of the COUNT frame, so we | |
| 1805 can ignore COUNT. */ | |
| 1806 | |
| 1807 #define RETURN_ADDR_RTX(COUNT, FRAME) \ | |
| 1808 (((COUNT) == 0) ? sh_get_pr_initial_val () : (rtx) 0) | |
| 1809 | |
| 1810 /* A C expression whose value is RTL representing the location of the | |
| 1811 incoming return address at the beginning of any function, before the | |
| 1812 prologue. This RTL is either a REG, indicating that the return | |
| 1813 value is saved in REG, or a MEM representing a location in | |
| 1814 the stack. */ | |
| 1815 #define INCOMING_RETURN_ADDR_RTX \ | |
| 1816 gen_rtx_REG (Pmode, TARGET_SHMEDIA ? PR_MEDIA_REG : PR_REG) | |
| 1817 | |
| 1818 /* Addressing modes, and classification of registers for them. */ | |
| 1819 #define HAVE_POST_INCREMENT TARGET_SH1 | |
| 1820 #define HAVE_PRE_DECREMENT TARGET_SH1 | |
| 1821 | |
| 1822 #define USE_LOAD_POST_INCREMENT(mode) ((mode == SImode || mode == DImode) \ | |
| 1823 ? 0 : TARGET_SH1) | |
| 1824 #define USE_LOAD_PRE_DECREMENT(mode) 0 | |
| 1825 #define USE_STORE_POST_INCREMENT(mode) 0 | |
| 1826 #define USE_STORE_PRE_DECREMENT(mode) ((mode == SImode || mode == DImode) \ | |
| 1827 ? 0 : TARGET_SH1) | |
| 1828 | |
| 1829 #define MOVE_BY_PIECES_P(SIZE, ALIGN) \ | |
| 1830 (move_by_pieces_ninsns (SIZE, ALIGN, MOVE_MAX_PIECES + 1) \ | |
| 1831 < (TARGET_SMALLCODE ? 2 : ((ALIGN >= 32) ? 16 : 2))) | |
| 1832 | |
| 1833 #define STORE_BY_PIECES_P(SIZE, ALIGN) \ | |
| 1834 (move_by_pieces_ninsns (SIZE, ALIGN, STORE_MAX_PIECES + 1) \ | |
| 1835 < (TARGET_SMALLCODE ? 2 : ((ALIGN >= 32) ? 16 : 2))) | |
| 1836 | |
| 1837 #define SET_BY_PIECES_P(SIZE, ALIGN) STORE_BY_PIECES_P(SIZE, ALIGN) | |
| 1838 | |
| 1839 /* Macros to check register numbers against specific register classes. */ | |
| 1840 | |
| 1841 /* These assume that REGNO is a hard or pseudo reg number. | |
| 1842 They give nonzero only if REGNO is a hard reg of the suitable class | |
| 1843 or a pseudo reg currently allocated to a suitable hard reg. | |
| 1844 Since they use reg_renumber, they are safe only once reg_renumber | |
| 1845 has been allocated, which happens in local-alloc.c. */ | |
| 1846 | |
| 1847 #define REGNO_OK_FOR_BASE_P(REGNO) \ | |
| 1848 (GENERAL_OR_AP_REGISTER_P (REGNO) \ | |
| 1849 || GENERAL_OR_AP_REGISTER_P (reg_renumber[(REGNO)])) | |
| 1850 #define REGNO_OK_FOR_INDEX_P(REGNO) \ | |
| 1851 (TARGET_SHMEDIA \ | |
| 1852 ? (GENERAL_REGISTER_P (REGNO) \ | |
| 1853 || GENERAL_REGISTER_P ((unsigned) reg_renumber[(REGNO)])) \ | |
| 1854 : (REGNO) == R0_REG || (unsigned) reg_renumber[(REGNO)] == R0_REG) | |
| 1855 | |
| 1856 /* Maximum number of registers that can appear in a valid memory | |
| 1857 address. */ | |
| 1858 | |
| 1859 #define MAX_REGS_PER_ADDRESS 2 | |
| 1860 | |
| 1861 /* Recognize any constant value that is a valid address. */ | |
| 1862 | |
| 1863 #define CONSTANT_ADDRESS_P(X) (GET_CODE (X) == LABEL_REF) | |
| 1864 | |
| 1865 /* Nonzero if the constant value X is a legitimate general operand. */ | |
| 1866 /* can_store_by_pieces constructs VOIDmode CONST_DOUBLEs. */ | |
| 1867 | |
| 1868 #define LEGITIMATE_CONSTANT_P(X) \ | |
| 1869 (TARGET_SHMEDIA \ | |
| 1870 ? ((GET_MODE (X) != DFmode \ | |
| 1871 && GET_MODE_CLASS (GET_MODE (X)) != MODE_VECTOR_FLOAT) \ | |
| 1872 || (X) == CONST0_RTX (GET_MODE (X)) \ | |
| 1873 || ! TARGET_SHMEDIA_FPU \ | |
| 1874 || TARGET_SHMEDIA64) \ | |
| 1875 : (GET_CODE (X) != CONST_DOUBLE \ | |
| 1876 || GET_MODE (X) == DFmode || GET_MODE (X) == SFmode \ | |
| 1877 || GET_MODE (X) == DImode || GET_MODE (X) == VOIDmode)) | |
| 1878 | |
| 1879 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx | |
| 1880 and check its validity for a certain class. | |
|
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1881 The suitable hard regs are always accepted and all pseudo regs |
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1882 are also accepted if STRICT is not set. */ |
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1883 |
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1884 /* Nonzero if X is a reg that can be used as a base reg. */ |
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1885 #define REG_OK_FOR_BASE_P(X, STRICT) \ |
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1886 (GENERAL_OR_AP_REGISTER_P (REGNO (X)) \ |
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1887 || (!STRICT && REGNO (X) >= FIRST_PSEUDO_REGISTER)) |
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1888 |
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1889 /* Nonzero if X is a reg that can be used as an index. */ |
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1890 #define REG_OK_FOR_INDEX_P(X, STRICT) \ |
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1891 ((TARGET_SHMEDIA ? GENERAL_REGISTER_P (REGNO (X)) \ |
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1892 : REGNO (X) == R0_REG) \ |
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1893 || (!STRICT && REGNO (X) >= FIRST_PSEUDO_REGISTER)) |
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1894 |
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1895 /* Nonzero if X/OFFSET is a reg that can be used as an index. */ |
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1896 #define SUBREG_OK_FOR_INDEX_P(X, OFFSET, STRICT) \ |
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1897 ((TARGET_SHMEDIA ? GENERAL_REGISTER_P (REGNO (X)) \ |
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1898 : REGNO (X) == R0_REG && OFFSET == 0) \ |
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1899 || (!STRICT && REGNO (X) >= FIRST_PSEUDO_REGISTER)) |
| 0 | 1900 |
| 1901 /* Macros for extra constraints. */ | |
| 1902 | |
| 1903 #define IS_PC_RELATIVE_LOAD_ADDR_P(OP) \ | |
| 1904 ((GET_CODE ((OP)) == LABEL_REF) \ | |
| 1905 || (GET_CODE ((OP)) == CONST \ | |
| 1906 && GET_CODE (XEXP ((OP), 0)) == PLUS \ | |
| 1907 && GET_CODE (XEXP (XEXP ((OP), 0), 0)) == LABEL_REF \ | |
|
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1908 && CONST_INT_P (XEXP (XEXP ((OP), 0), 1)))) |
| 0 | 1909 |
| 1910 #define IS_NON_EXPLICIT_CONSTANT_P(OP) \ | |
| 1911 (CONSTANT_P (OP) \ | |
|
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1912 && !CONST_INT_P (OP) \ |
| 0 | 1913 && GET_CODE (OP) != CONST_DOUBLE \ |
| 1914 && (!flag_pic \ | |
| 1915 || (LEGITIMATE_PIC_OPERAND_P (OP) \ | |
| 1916 && !PIC_ADDR_P (OP) \ | |
| 1917 && GET_CODE (OP) != LABEL_REF))) | |
| 1918 | |
| 1919 /* Check whether OP is a datalabel unspec. */ | |
| 1920 #define DATALABEL_REF_NO_CONST_P(OP) \ | |
| 1921 (GET_CODE (OP) == UNSPEC \ | |
| 1922 && XINT ((OP), 1) == UNSPEC_DATALABEL \ | |
| 1923 && XVECLEN ((OP), 0) == 1 \ | |
| 1924 && GET_CODE (XVECEXP ((OP), 0, 0)) == LABEL_REF) | |
| 1925 | |
| 1926 #define GOT_ENTRY_P(OP) \ | |
| 1927 (GET_CODE (OP) == CONST && GET_CODE (XEXP ((OP), 0)) == UNSPEC \ | |
| 1928 && XINT (XEXP ((OP), 0), 1) == UNSPEC_GOT) | |
| 1929 | |
| 1930 #define GOTPLT_ENTRY_P(OP) \ | |
| 1931 (GET_CODE (OP) == CONST && GET_CODE (XEXP ((OP), 0)) == UNSPEC \ | |
| 1932 && XINT (XEXP ((OP), 0), 1) == UNSPEC_GOTPLT) | |
| 1933 | |
| 1934 #define UNSPEC_GOTOFF_P(OP) \ | |
| 1935 (GET_CODE (OP) == UNSPEC && XINT ((OP), 1) == UNSPEC_GOTOFF) | |
| 1936 | |
| 1937 #define GOTOFF_P(OP) \ | |
| 1938 (GET_CODE (OP) == CONST \ | |
| 1939 && (UNSPEC_GOTOFF_P (XEXP ((OP), 0)) \ | |
| 1940 || (GET_CODE (XEXP ((OP), 0)) == PLUS \ | |
| 1941 && UNSPEC_GOTOFF_P (XEXP (XEXP ((OP), 0), 0)) \ | |
|
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1942 && CONST_INT_P (XEXP (XEXP ((OP), 0), 1))))) |
| 0 | 1943 |
| 1944 #define PIC_ADDR_P(OP) \ | |
| 1945 (GET_CODE (OP) == CONST && GET_CODE (XEXP ((OP), 0)) == UNSPEC \ | |
| 1946 && XINT (XEXP ((OP), 0), 1) == UNSPEC_PIC) | |
| 1947 | |
| 1948 #define PCREL_SYMOFF_P(OP) \ | |
| 1949 (GET_CODE (OP) == CONST \ | |
| 1950 && GET_CODE (XEXP ((OP), 0)) == UNSPEC \ | |
| 1951 && XINT (XEXP ((OP), 0), 1) == UNSPEC_PCREL_SYMOFF) | |
| 1952 | |
| 1953 #define NON_PIC_REFERENCE_P(OP) \ | |
| 1954 (GET_CODE (OP) == LABEL_REF || GET_CODE (OP) == SYMBOL_REF \ | |
| 1955 || (GET_CODE (OP) == CONST \ | |
| 1956 && (GET_CODE (XEXP ((OP), 0)) == LABEL_REF \ | |
| 1957 || GET_CODE (XEXP ((OP), 0)) == SYMBOL_REF \ | |
| 1958 || DATALABEL_REF_NO_CONST_P (XEXP ((OP), 0)))) \ | |
| 1959 || (GET_CODE (OP) == CONST && GET_CODE (XEXP ((OP), 0)) == PLUS \ | |
| 1960 && (GET_CODE (XEXP (XEXP ((OP), 0), 0)) == SYMBOL_REF \ | |
| 1961 || GET_CODE (XEXP (XEXP ((OP), 0), 0)) == LABEL_REF \ | |
| 1962 || DATALABEL_REF_NO_CONST_P (XEXP (XEXP ((OP), 0), 0))) \ | |
|
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1963 && CONST_INT_P (XEXP (XEXP ((OP), 0), 1)))) |
| 0 | 1964 |
| 1965 #define PIC_REFERENCE_P(OP) \ | |
| 1966 (GOT_ENTRY_P (OP) || GOTPLT_ENTRY_P (OP) \ | |
| 1967 || GOTOFF_P (OP) || PIC_ADDR_P (OP)) | |
| 1968 | |
| 1969 #define MOVI_SHORI_BASE_OPERAND_P(OP) \ | |
| 1970 (flag_pic \ | |
| 1971 ? (GOT_ENTRY_P (OP) || GOTPLT_ENTRY_P (OP) || GOTOFF_P (OP) \ | |
| 1972 || PCREL_SYMOFF_P (OP)) \ | |
| 1973 : NON_PIC_REFERENCE_P (OP)) | |
| 1974 | |
|
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1975 #define MAYBE_BASE_REGISTER_RTX_P(X, STRICT) \ |
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1976 ((REG_P (X) && REG_OK_FOR_BASE_P (X, STRICT)) \ |
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1977 || (GET_CODE (X) == SUBREG \ |
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1978 && TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (GET_MODE ((X))), \ |
| 0 | 1979 GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (X)))) \ |
|
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1980 && REG_P (SUBREG_REG (X)) \ |
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1981 && REG_OK_FOR_BASE_P (SUBREG_REG (X), STRICT))) |
| 0 | 1982 |
| 1983 /* Since this must be r0, which is a single register class, we must check | |
| 1984 SUBREGs more carefully, to be sure that we don't accept one that extends | |
| 1985 outside the class. */ | |
|
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1986 #define MAYBE_INDEX_REGISTER_RTX_P(X, STRICT) \ |
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1987 ((REG_P (X) && REG_OK_FOR_INDEX_P (X, STRICT)) \ |
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1988 || (GET_CODE (X) == SUBREG \ |
| 0 | 1989 && TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (GET_MODE ((X))), \ |
| 1990 GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (X)))) \ | |
|
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1991 && REG_P (SUBREG_REG (X)) \ |
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1992 && SUBREG_OK_FOR_INDEX_P (SUBREG_REG (X), SUBREG_BYTE (X), STRICT))) |
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1993 |
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1994 #ifdef REG_OK_STRICT |
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1995 #define BASE_REGISTER_RTX_P(X) MAYBE_BASE_REGISTER_RTX_P(X, true) |
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1996 #define INDEX_REGISTER_RTX_P(X) MAYBE_INDEX_REGISTER_RTX_P(X, true) |
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1997 #else |
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1998 #define BASE_REGISTER_RTX_P(X) MAYBE_BASE_REGISTER_RTX_P(X, false) |
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1999 #define INDEX_REGISTER_RTX_P(X) MAYBE_INDEX_REGISTER_RTX_P(X, false) |
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2000 #endif |
| 0 | 2001 |
| 2002 #define ALLOW_INDEXED_ADDRESS \ | |
| 2003 ((!TARGET_SHMEDIA32 && !TARGET_SHCOMPACT) || TARGET_ALLOW_INDEXED_ADDRESS) | |
| 2004 | |
|
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2005 #define GO_IF_LEGITIMATE_INDEX(MODE, OP, WIN) \ |
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2006 do { \ |
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2007 if (sh_legitimate_index_p ((MODE), (OP))) \ |
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2008 goto WIN; \ |
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2009 } while (0) |
| 0 | 2010 |
| 2011 /* A C compound statement that attempts to replace X, which is an address | |
| 2012 that needs reloading, with a valid memory address for an operand of | |
| 2013 mode MODE. WIN is a C statement label elsewhere in the code. | |
| 2014 | |
| 2015 Like for LEGITIMIZE_ADDRESS, for the SH we try to get a normal form | |
| 2016 of the address. That will allow inheritance of the address reloads. */ | |
| 2017 | |
| 2018 #define LEGITIMIZE_RELOAD_ADDRESS(X,MODE,OPNUM,TYPE,IND_LEVELS,WIN) \ | |
| 2019 { \ | |
| 2020 if (GET_CODE (X) == PLUS \ | |
| 2021 && (GET_MODE_SIZE (MODE) == 4 || GET_MODE_SIZE (MODE) == 8) \ | |
|
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2022 && CONST_INT_P (XEXP (X, 1)) \ |
| 0 | 2023 && BASE_REGISTER_RTX_P (XEXP (X, 0)) \ |
| 2024 && ! TARGET_SHMEDIA \ | |
| 2025 && ! (TARGET_SH4 && (MODE) == DFmode) \ | |
| 2026 && ! ((MODE) == PSImode && (TYPE) == RELOAD_FOR_INPUT_ADDRESS) \ | |
| 2027 && (ALLOW_INDEXED_ADDRESS \ | |
| 2028 || XEXP ((X), 0) == stack_pointer_rtx \ | |
| 2029 || XEXP ((X), 0) == hard_frame_pointer_rtx)) \ | |
| 2030 { \ | |
| 2031 rtx index_rtx = XEXP (X, 1); \ | |
| 2032 HOST_WIDE_INT offset = INTVAL (index_rtx), offset_base; \ | |
| 2033 rtx sum; \ | |
| 2034 \ | |
| 2035 if (TARGET_SH2A && (MODE) == DFmode && (offset & 0x7)) \ | |
| 2036 { \ | |
| 2037 push_reload (X, NULL_RTX, &X, NULL, \ | |
| 2038 BASE_REG_CLASS, Pmode, VOIDmode, 0, 0, (OPNUM), \ | |
| 2039 (TYPE)); \ | |
| 2040 goto WIN; \ | |
| 2041 } \ | |
| 2042 if (TARGET_SH2E && MODE == SFmode) \ | |
| 2043 { \ | |
| 2044 X = copy_rtx (X); \ | |
| 2045 push_reload (X, NULL_RTX, &X, NULL, \ | |
| 2046 BASE_REG_CLASS, Pmode, VOIDmode, 0, 0, (OPNUM), \ | |
| 2047 (TYPE)); \ | |
| 2048 goto WIN; \ | |
| 2049 } \ | |
| 2050 /* Instead of offset_base 128..131 use 124..127, so that \ | |
| 2051 simple add suffices. */ \ | |
| 2052 if (offset > 127) \ | |
| 2053 { \ | |
| 2054 offset_base = ((offset + 4) & ~60) - 4; \ | |
| 2055 } \ | |
| 2056 else \ | |
| 2057 offset_base = offset & ~60; \ | |
| 2058 /* Sometimes the normal form does not suit DImode. We \ | |
| 2059 could avoid that by using smaller ranges, but that \ | |
| 2060 would give less optimized code when SImode is \ | |
| 2061 prevalent. */ \ | |
| 2062 if (GET_MODE_SIZE (MODE) + offset - offset_base <= 64) \ | |
| 2063 { \ | |
| 2064 sum = gen_rtx_PLUS (Pmode, XEXP (X, 0), \ | |
| 2065 GEN_INT (offset_base)); \ | |
| 2066 X = gen_rtx_PLUS (Pmode, sum, GEN_INT (offset - offset_base));\ | |
| 2067 push_reload (sum, NULL_RTX, &XEXP (X, 0), NULL, \ | |
| 2068 BASE_REG_CLASS, Pmode, VOIDmode, 0, 0, (OPNUM), \ | |
| 2069 (TYPE)); \ | |
| 2070 goto WIN; \ | |
| 2071 } \ | |
| 2072 } \ | |
| 2073 /* We must re-recognize what we created before. */ \ | |
| 2074 else if (GET_CODE (X) == PLUS \ | |
| 2075 && (GET_MODE_SIZE (MODE) == 4 || GET_MODE_SIZE (MODE) == 8) \ | |
| 2076 && GET_CODE (XEXP (X, 0)) == PLUS \ | |
|
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2077 && CONST_INT_P (XEXP (XEXP (X, 0), 1)) \ |
| 0 | 2078 && BASE_REGISTER_RTX_P (XEXP (XEXP (X, 0), 0)) \ |
|
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2079 && CONST_INT_P (XEXP (X, 1)) \ |
| 0 | 2080 && ! TARGET_SHMEDIA \ |
| 2081 && ! (TARGET_SH2E && MODE == SFmode)) \ | |
| 2082 { \ | |
| 2083 /* Because this address is so complex, we know it must have \ | |
| 2084 been created by LEGITIMIZE_RELOAD_ADDRESS before; thus, \ | |
| 2085 it is already unshared, and needs no further unsharing. */ \ | |
| 2086 push_reload (XEXP ((X), 0), NULL_RTX, &XEXP ((X), 0), NULL, \ | |
| 2087 BASE_REG_CLASS, Pmode, VOIDmode, 0, 0, (OPNUM), (TYPE));\ | |
| 2088 goto WIN; \ | |
| 2089 } \ | |
| 2090 } | |
| 2091 | |
| 2092 /* Specify the machine mode that this machine uses | |
| 2093 for the index in the tablejump instruction. */ | |
| 2094 #define CASE_VECTOR_MODE ((! optimize || TARGET_BIGTABLE) ? SImode : HImode) | |
| 2095 | |
| 2096 #define CASE_VECTOR_SHORTEN_MODE(MIN_OFFSET, MAX_OFFSET, BODY) \ | |
| 2097 ((MIN_OFFSET) >= 0 && (MAX_OFFSET) <= 127 \ | |
| 2098 ? (ADDR_DIFF_VEC_FLAGS (BODY).offset_unsigned = 0, QImode) \ | |
| 2099 : (MIN_OFFSET) >= 0 && (MAX_OFFSET) <= 255 \ | |
| 2100 ? (ADDR_DIFF_VEC_FLAGS (BODY).offset_unsigned = 1, QImode) \ | |
| 2101 : (MIN_OFFSET) >= -32768 && (MAX_OFFSET) <= 32767 ? HImode \ | |
| 2102 : SImode) | |
| 2103 | |
| 2104 /* Define as C expression which evaluates to nonzero if the tablejump | |
| 2105 instruction expects the table to contain offsets from the address of the | |
| 2106 table. | |
| 2107 Do not define this if the table should contain absolute addresses. */ | |
| 2108 #define CASE_VECTOR_PC_RELATIVE 1 | |
| 2109 | |
| 2110 /* Define it here, so that it doesn't get bumped to 64-bits on SHmedia. */ | |
| 2111 #define FLOAT_TYPE_SIZE 32 | |
| 2112 | |
| 2113 /* Since the SH2e has only `float' support, it is desirable to make all | |
| 2114 floating point types equivalent to `float'. */ | |
| 2115 #define DOUBLE_TYPE_SIZE ((TARGET_SH2E && ! TARGET_SH4 && ! TARGET_SH2A_DOUBLE) ? 32 : 64) | |
| 2116 | |
|
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2117 #if defined(__SH2E__) || defined(__SH3E__) || defined( __SH2A_SINGLE_ONLY__) || defined( __SH4_SINGLE_ONLY__) |
| 0 | 2118 #define LIBGCC2_DOUBLE_TYPE_SIZE 32 |
| 2119 #else | |
| 2120 #define LIBGCC2_DOUBLE_TYPE_SIZE 64 | |
| 2121 #endif | |
| 2122 | |
| 2123 /* 'char' is signed by default. */ | |
| 2124 #define DEFAULT_SIGNED_CHAR 1 | |
| 2125 | |
| 2126 /* The type of size_t unsigned int. */ | |
| 2127 #define SIZE_TYPE (TARGET_SH5 ? "long unsigned int" : "unsigned int") | |
| 2128 | |
| 2129 #undef PTRDIFF_TYPE | |
| 2130 #define PTRDIFF_TYPE (TARGET_SH5 ? "long int" : "int") | |
| 2131 | |
| 2132 #define WCHAR_TYPE "short unsigned int" | |
| 2133 #define WCHAR_TYPE_SIZE 16 | |
| 2134 | |
| 2135 #define SH_ELF_WCHAR_TYPE "long int" | |
| 2136 | |
| 2137 /* Max number of bytes we can move from memory to memory | |
| 2138 in one reasonably fast instruction. */ | |
| 2139 #define MOVE_MAX (TARGET_SHMEDIA ? 8 : 4) | |
| 2140 | |
| 2141 /* Maximum value possibly taken by MOVE_MAX. Must be defined whenever | |
| 2142 MOVE_MAX is not a compile-time constant. */ | |
| 2143 #define MAX_MOVE_MAX 8 | |
| 2144 | |
| 2145 /* Max number of bytes we want move_by_pieces to be able to copy | |
| 2146 efficiently. */ | |
| 2147 #define MOVE_MAX_PIECES (TARGET_SH4 || TARGET_SHMEDIA ? 8 : 4) | |
| 2148 | |
| 2149 /* Define if operations between registers always perform the operation | |
| 2150 on the full register even if a narrower mode is specified. */ | |
| 2151 #define WORD_REGISTER_OPERATIONS | |
| 2152 | |
| 2153 /* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD | |
| 2154 will either zero-extend or sign-extend. The value of this macro should | |
| 2155 be the code that says which one of the two operations is implicitly | |
| 2156 done, UNKNOWN if none. */ | |
| 2157 /* For SHmedia, we can truncate to QImode easier using zero extension. */ | |
| 2158 /* FP registers can load SImode values, but don't implicitly sign-extend | |
| 2159 them to DImode. */ | |
| 2160 #define LOAD_EXTEND_OP(MODE) \ | |
| 2161 (((MODE) == QImode && TARGET_SHMEDIA) ? ZERO_EXTEND \ | |
| 2162 : (MODE) != SImode ? SIGN_EXTEND : UNKNOWN) | |
| 2163 | |
| 2164 /* Define if loading short immediate values into registers sign extends. */ | |
| 2165 #define SHORT_IMMEDIATES_SIGN_EXTEND | |
| 2166 | |
| 2167 /* Nonzero if access to memory by bytes is no faster than for words. */ | |
| 2168 #define SLOW_BYTE_ACCESS 1 | |
| 2169 | |
| 2170 /* Immediate shift counts are truncated by the output routines (or was it | |
| 2171 the assembler?). Shift counts in a register are truncated by SH. Note | |
| 2172 that the native compiler puts too large (> 32) immediate shift counts | |
| 2173 into a register and shifts by the register, letting the SH decide what | |
| 2174 to do instead of doing that itself. */ | |
| 2175 /* ??? The library routines in lib1funcs.asm truncate the shift count. | |
| 2176 However, the SH3 has hardware shifts that do not truncate exactly as gcc | |
| 2177 expects - the sign bit is significant - so it appears that we need to | |
| 2178 leave this zero for correct SH3 code. */ | |
| 2179 #define SHIFT_COUNT_TRUNCATED (! TARGET_SH3 && ! TARGET_SH2A) | |
| 2180 | |
| 2181 /* All integers have the same format so truncation is easy. */ | |
| 2182 /* But SHmedia must sign-extend DImode when truncating to SImode. */ | |
| 2183 #define TRULY_NOOP_TRUNCATION(OUTPREC,INPREC) \ | |
| 2184 (!TARGET_SHMEDIA || (INPREC) < 64 || (OUTPREC) >= 64) | |
| 2185 | |
| 2186 /* Define this if addresses of constant functions | |
| 2187 shouldn't be put through pseudo regs where they can be cse'd. | |
| 2188 Desirable on machines where ordinary constants are expensive | |
| 2189 but a CALL with constant address is cheap. */ | |
| 2190 /*#define NO_FUNCTION_CSE 1*/ | |
| 2191 | |
| 2192 /* The machine modes of pointers and functions. */ | |
| 2193 #define Pmode (TARGET_SHMEDIA64 ? DImode : SImode) | |
| 2194 #define FUNCTION_MODE Pmode | |
| 2195 | |
| 2196 /* The multiply insn on the SH1 and the divide insns on the SH1 and SH2 | |
| 2197 are actually function calls with some special constraints on arguments | |
| 2198 and register usage. | |
| 2199 | |
| 2200 These macros tell reorg that the references to arguments and | |
| 2201 register clobbers for insns of type sfunc do not appear to happen | |
| 2202 until after the millicode call. This allows reorg to put insns | |
| 2203 which set the argument registers into the delay slot of the millicode | |
| 2204 call -- thus they act more like traditional CALL_INSNs. | |
| 2205 | |
| 2206 get_attr_is_sfunc will try to recognize the given insn, so make sure to | |
| 2207 filter out things it will not accept -- SEQUENCE, USE and CLOBBER insns | |
| 2208 in particular. */ | |
| 2209 | |
| 2210 #define INSN_SETS_ARE_DELAYED(X) \ | |
|
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2211 ((NONJUMP_INSN_P (X) \ |
| 0 | 2212 && GET_CODE (PATTERN (X)) != SEQUENCE \ |
| 2213 && GET_CODE (PATTERN (X)) != USE \ | |
| 2214 && GET_CODE (PATTERN (X)) != CLOBBER \ | |
| 2215 && get_attr_is_sfunc (X))) | |
| 2216 | |
| 2217 #define INSN_REFERENCES_ARE_DELAYED(X) \ | |
|
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2218 ((NONJUMP_INSN_P (X) \ |
| 0 | 2219 && GET_CODE (PATTERN (X)) != SEQUENCE \ |
| 2220 && GET_CODE (PATTERN (X)) != USE \ | |
| 2221 && GET_CODE (PATTERN (X)) != CLOBBER \ | |
| 2222 && get_attr_is_sfunc (X))) | |
| 2223 | |
| 2224 | |
| 2225 /* Position Independent Code. */ | |
| 2226 | |
| 2227 /* We can't directly access anything that contains a symbol, | |
| 2228 nor can we indirect via the constant pool. */ | |
| 2229 #define LEGITIMATE_PIC_OPERAND_P(X) \ | |
| 2230 ((! nonpic_symbol_mentioned_p (X) \ | |
| 2231 && (GET_CODE (X) != SYMBOL_REF \ | |
| 2232 || ! CONSTANT_POOL_ADDRESS_P (X) \ | |
| 2233 || ! nonpic_symbol_mentioned_p (get_pool_constant (X)))) \ | |
| 2234 || (TARGET_SHMEDIA && GET_CODE (X) == LABEL_REF)) | |
| 2235 | |
| 2236 #define SYMBOLIC_CONST_P(X) \ | |
| 2237 ((GET_CODE (X) == SYMBOL_REF || GET_CODE (X) == LABEL_REF) \ | |
| 2238 && nonpic_symbol_mentioned_p (X)) | |
| 2239 | |
| 2240 /* Compute extra cost of moving data between one register class | |
| 2241 and another. */ | |
| 2242 | |
| 2243 /* If SECONDARY*_RELOAD_CLASS says something about the src/dst pair, regclass | |
| 2244 uses this information. Hence, the general register <-> floating point | |
| 2245 register information here is not used for SFmode. */ | |
| 2246 | |
| 2247 #define REGCLASS_HAS_GENERAL_REG(CLASS) \ | |
| 2248 ((CLASS) == GENERAL_REGS || (CLASS) == R0_REGS \ | |
| 2249 || (! TARGET_SHMEDIA && (CLASS) == SIBCALL_REGS)) | |
| 2250 | |
| 2251 #define REGCLASS_HAS_FP_REG(CLASS) \ | |
| 2252 ((CLASS) == FP0_REGS || (CLASS) == FP_REGS \ | |
| 2253 || (CLASS) == DF_REGS || (CLASS) == DF_HI_REGS) | |
| 2254 | |
| 2255 #define REGISTER_MOVE_COST(MODE, SRCCLASS, DSTCLASS) \ | |
| 2256 sh_register_move_cost ((MODE), (SRCCLASS), (DSTCLASS)) | |
| 2257 | |
| 2258 /* ??? Perhaps make MEMORY_MOVE_COST depend on compiler option? This | |
| 2259 would be so that people with slow memory systems could generate | |
| 2260 different code that does fewer memory accesses. */ | |
| 2261 | |
| 2262 /* A C expression for the cost of a branch instruction. A value of 1 | |
| 2263 is the default; other values are interpreted relative to that. | |
| 2264 The SH1 does not have delay slots, hence we get a pipeline stall | |
| 2265 at every branch. The SH4 is superscalar, so the single delay slot | |
| 2266 is not sufficient to keep both pipelines filled. */ | |
| 2267 #define BRANCH_COST(speed_p, predictable_p) \ | |
| 2268 (TARGET_SH5 ? 1 : ! TARGET_SH2 || TARGET_HARD_SH4 ? 2 : 1) | |
| 2269 | |
| 2270 /* Assembler output control. */ | |
| 2271 | |
| 2272 /* A C string constant describing how to begin a comment in the target | |
| 2273 assembler language. The compiler assumes that the comment will end at | |
| 2274 the end of the line. */ | |
| 2275 #define ASM_COMMENT_START "!" | |
| 2276 | |
| 2277 #define ASM_APP_ON "" | |
| 2278 #define ASM_APP_OFF "" | |
| 2279 #define FILE_ASM_OP "\t.file\n" | |
| 2280 #define SET_ASM_OP "\t.set\t" | |
| 2281 | |
| 2282 /* How to change between sections. */ | |
| 2283 | |
| 2284 #define TEXT_SECTION_ASM_OP (TARGET_SHMEDIA32 ? "\t.section\t.text..SHmedia32,\"ax\"" : "\t.text") | |
| 2285 #define DATA_SECTION_ASM_OP "\t.data" | |
| 2286 | |
| 2287 #if defined CRT_BEGIN || defined CRT_END | |
| 2288 /* Arrange for TEXT_SECTION_ASM_OP to be a compile-time constant. */ | |
| 2289 # undef TEXT_SECTION_ASM_OP | |
| 2290 # if __SHMEDIA__ == 1 && __SH5__ == 32 | |
| 2291 # define TEXT_SECTION_ASM_OP "\t.section\t.text..SHmedia32,\"ax\"" | |
| 2292 # else | |
| 2293 # define TEXT_SECTION_ASM_OP "\t.text" | |
| 2294 # endif | |
| 2295 #endif | |
| 2296 | |
| 2297 | |
| 2298 /* If defined, a C expression whose value is a string containing the | |
| 2299 assembler operation to identify the following data as | |
| 2300 uninitialized global data. If not defined, and neither | |
| 2301 `ASM_OUTPUT_BSS' nor `ASM_OUTPUT_ALIGNED_BSS' are defined, | |
| 2302 uninitialized global data will be output in the data section if | |
| 2303 `-fno-common' is passed, otherwise `ASM_OUTPUT_COMMON' will be | |
| 2304 used. */ | |
| 2305 #ifndef BSS_SECTION_ASM_OP | |
| 2306 #define BSS_SECTION_ASM_OP "\t.section\t.bss" | |
| 2307 #endif | |
| 2308 | |
| 2309 /* Like `ASM_OUTPUT_BSS' except takes the required alignment as a | |
| 2310 separate, explicit argument. If you define this macro, it is used | |
| 2311 in place of `ASM_OUTPUT_BSS', and gives you more flexibility in | |
| 2312 handling the required alignment of the variable. The alignment is | |
| 2313 specified as the number of bits. | |
| 2314 | |
| 2315 Try to use function `asm_output_aligned_bss' defined in file | |
| 2316 `varasm.c' when defining this macro. */ | |
| 2317 #ifndef ASM_OUTPUT_ALIGNED_BSS | |
| 2318 #define ASM_OUTPUT_ALIGNED_BSS(FILE, DECL, NAME, SIZE, ALIGN) \ | |
| 2319 asm_output_aligned_bss (FILE, DECL, NAME, SIZE, ALIGN) | |
| 2320 #endif | |
| 2321 | |
| 2322 /* Define this so that jump tables go in same section as the current function, | |
| 2323 which could be text or it could be a user defined section. */ | |
| 2324 #define JUMP_TABLES_IN_TEXT_SECTION 1 | |
| 2325 | |
| 2326 #undef DO_GLOBAL_CTORS_BODY | |
| 2327 #define DO_GLOBAL_CTORS_BODY \ | |
| 2328 { \ | |
| 2329 typedef void (*pfunc) (void); \ | |
| 2330 extern pfunc __ctors[]; \ | |
| 2331 extern pfunc __ctors_end[]; \ | |
| 2332 pfunc *p; \ | |
| 2333 for (p = __ctors_end; p > __ctors; ) \ | |
| 2334 { \ | |
| 2335 (*--p)(); \ | |
| 2336 } \ | |
| 2337 } | |
| 2338 | |
| 2339 #undef DO_GLOBAL_DTORS_BODY | |
| 2340 #define DO_GLOBAL_DTORS_BODY \ | |
| 2341 { \ | |
| 2342 typedef void (*pfunc) (void); \ | |
| 2343 extern pfunc __dtors[]; \ | |
| 2344 extern pfunc __dtors_end[]; \ | |
| 2345 pfunc *p; \ | |
| 2346 for (p = __dtors; p < __dtors_end; p++) \ | |
| 2347 { \ | |
| 2348 (*p)(); \ | |
| 2349 } \ | |
| 2350 } | |
| 2351 | |
| 2352 #define ASM_OUTPUT_REG_PUSH(file, v) \ | |
| 2353 { \ | |
| 2354 if (TARGET_SHMEDIA) \ | |
| 2355 { \ | |
| 2356 fprintf ((file), "\taddi.l\tr15,-8,r15\n"); \ | |
| 2357 fprintf ((file), "\tst.q\tr15,0,r%d\n", (v)); \ | |
| 2358 } \ | |
| 2359 else \ | |
| 2360 fprintf ((file), "\tmov.l\tr%d,@-r15\n", (v)); \ | |
| 2361 } | |
| 2362 | |
| 2363 #define ASM_OUTPUT_REG_POP(file, v) \ | |
| 2364 { \ | |
| 2365 if (TARGET_SHMEDIA) \ | |
| 2366 { \ | |
| 2367 fprintf ((file), "\tld.q\tr15,0,r%d\n", (v)); \ | |
| 2368 fprintf ((file), "\taddi.l\tr15,8,r15\n"); \ | |
| 2369 } \ | |
| 2370 else \ | |
| 2371 fprintf ((file), "\tmov.l\t@r15+,r%d\n", (v)); \ | |
| 2372 } | |
| 2373 | |
| 2374 /* DBX register number for a given compiler register number. */ | |
| 2375 /* GDB has FPUL at 23 and FP0 at 25, so we must add one to all FP registers | |
| 2376 to match gdb. */ | |
| 2377 /* svr4.h undefines this macro, yet we really want to use the same numbers | |
| 2378 for coff as for elf, so we go via another macro: SH_DBX_REGISTER_NUMBER. */ | |
| 2379 /* expand_builtin_init_dwarf_reg_sizes uses this to test if a | |
| 2380 register exists, so we should return -1 for invalid register numbers. */ | |
| 2381 #define DBX_REGISTER_NUMBER(REGNO) SH_DBX_REGISTER_NUMBER (REGNO) | |
| 2382 | |
| 2383 /* SHcompact PR_REG used to use the encoding 241, and SHcompact FP registers | |
| 2384 used to use the encodings 245..260, but that doesn't make sense: | |
| 2385 PR_REG and PR_MEDIA_REG are actually the same register, and likewise | |
| 2386 the FP registers stay the same when switching between compact and media | |
| 2387 mode. Hence, we also need to use the same dwarf frame columns. | |
| 2388 Likewise, we need to support unwind information for SHmedia registers | |
| 2389 even in compact code. */ | |
| 2390 #define SH_DBX_REGISTER_NUMBER(REGNO) \ | |
| 2391 (IN_RANGE ((REGNO), \ | |
| 2392 (unsigned HOST_WIDE_INT) FIRST_GENERAL_REG, \ | |
| 2393 FIRST_GENERAL_REG + (TARGET_SH5 ? 63U :15U)) \ | |
| 2394 ? ((unsigned) (REGNO) - FIRST_GENERAL_REG) \ | |
| 2395 : ((int) (REGNO) >= FIRST_FP_REG \ | |
| 2396 && ((int) (REGNO) \ | |
| 2397 <= (FIRST_FP_REG + \ | |
| 2398 ((TARGET_SH5 && TARGET_FPU_ANY) ? 63 : TARGET_SH2E ? 15 : -1)))) \ | |
| 2399 ? ((unsigned) (REGNO) - FIRST_FP_REG \ | |
| 2400 + (TARGET_SH5 ? 77 : 25)) \ | |
| 2401 : XD_REGISTER_P (REGNO) \ | |
| 2402 ? ((unsigned) (REGNO) - FIRST_XD_REG + (TARGET_SH5 ? 289 : 87)) \ | |
| 2403 : TARGET_REGISTER_P (REGNO) \ | |
| 2404 ? ((unsigned) (REGNO) - FIRST_TARGET_REG + 68) \ | |
| 2405 : (REGNO) == PR_REG \ | |
| 2406 ? (TARGET_SH5 ? 18 : 17) \ | |
| 2407 : (REGNO) == PR_MEDIA_REG \ | |
| 2408 ? (TARGET_SH5 ? 18 : (unsigned) -1) \ | |
| 2409 : (REGNO) == GBR_REG \ | |
| 2410 ? (TARGET_SH5 ? 238 : 18) \ | |
| 2411 : (REGNO) == MACH_REG \ | |
| 2412 ? (TARGET_SH5 ? 239 : 20) \ | |
| 2413 : (REGNO) == MACL_REG \ | |
| 2414 ? (TARGET_SH5 ? 240 : 21) \ | |
| 2415 : (REGNO) == T_REG \ | |
| 2416 ? (TARGET_SH5 ? 242 : 22) \ | |
| 2417 : (REGNO) == FPUL_REG \ | |
| 2418 ? (TARGET_SH5 ? 244 : 23) \ | |
| 2419 : (REGNO) == FPSCR_REG \ | |
| 2420 ? (TARGET_SH5 ? 243 : 24) \ | |
| 2421 : (unsigned) -1) | |
| 2422 | |
| 2423 /* This is how to output a reference to a symbol_ref. On SH5, | |
| 2424 references to non-code symbols must be preceded by `datalabel'. */ | |
| 2425 #define ASM_OUTPUT_SYMBOL_REF(FILE,SYM) \ | |
| 2426 do \ | |
| 2427 { \ | |
| 2428 if (TARGET_SH5 && !SYMBOL_REF_FUNCTION_P (SYM)) \ | |
| 2429 fputs ("datalabel ", (FILE)); \ | |
| 2430 assemble_name ((FILE), XSTR ((SYM), 0)); \ | |
| 2431 } \ | |
| 2432 while (0) | |
| 2433 | |
| 2434 /* This is how to output an assembler line | |
| 2435 that says to advance the location counter | |
| 2436 to a multiple of 2**LOG bytes. */ | |
| 2437 | |
| 2438 #define ASM_OUTPUT_ALIGN(FILE,LOG) \ | |
| 2439 if ((LOG) != 0) \ | |
| 2440 fprintf ((FILE), "\t.align %d\n", (LOG)) | |
| 2441 | |
| 2442 /* Globalizing directive for a label. */ | |
| 2443 #define GLOBAL_ASM_OP "\t.global\t" | |
| 2444 | |
| 2445 /* #define ASM_OUTPUT_CASE_END(STREAM,NUM,TABLE) */ | |
| 2446 | |
| 2447 /* Output a relative address table. */ | |
| 2448 | |
| 2449 #define ASM_OUTPUT_ADDR_DIFF_ELT(STREAM,BODY,VALUE,REL) \ | |
| 2450 switch (GET_MODE (BODY)) \ | |
| 2451 { \ | |
| 2452 case SImode: \ | |
| 2453 if (TARGET_SH5) \ | |
| 2454 { \ | |
| 2455 asm_fprintf ((STREAM), "\t.long\t%LL%d-datalabel %LL%d\n", \ | |
| 2456 (VALUE), (REL)); \ | |
| 2457 break; \ | |
| 2458 } \ | |
| 2459 asm_fprintf ((STREAM), "\t.long\t%LL%d-%LL%d\n", (VALUE),(REL)); \ | |
| 2460 break; \ | |
| 2461 case HImode: \ | |
| 2462 if (TARGET_SH5) \ | |
| 2463 { \ | |
| 2464 asm_fprintf ((STREAM), "\t.word\t%LL%d-datalabel %LL%d\n", \ | |
| 2465 (VALUE), (REL)); \ | |
| 2466 break; \ | |
| 2467 } \ | |
| 2468 asm_fprintf ((STREAM), "\t.word\t%LL%d-%LL%d\n", (VALUE),(REL)); \ | |
| 2469 break; \ | |
| 2470 case QImode: \ | |
| 2471 if (TARGET_SH5) \ | |
| 2472 { \ | |
| 2473 asm_fprintf ((STREAM), "\t.byte\t%LL%d-datalabel %LL%d\n", \ | |
| 2474 (VALUE), (REL)); \ | |
| 2475 break; \ | |
| 2476 } \ | |
| 2477 asm_fprintf ((STREAM), "\t.byte\t%LL%d-%LL%d\n", (VALUE),(REL)); \ | |
| 2478 break; \ | |
| 2479 default: \ | |
| 2480 break; \ | |
| 2481 } | |
| 2482 | |
| 2483 /* Output an absolute table element. */ | |
| 2484 | |
| 2485 #define ASM_OUTPUT_ADDR_VEC_ELT(STREAM,VALUE) \ | |
| 2486 if (! optimize || TARGET_BIGTABLE) \ | |
| 2487 asm_fprintf ((STREAM), "\t.long\t%LL%d\n", (VALUE)); \ | |
| 2488 else \ | |
| 2489 asm_fprintf ((STREAM), "\t.word\t%LL%d\n", (VALUE)); | |
| 2490 | |
| 2491 | |
| 2492 /* A C statement to be executed just prior to the output of | |
| 2493 assembler code for INSN, to modify the extracted operands so | |
| 2494 they will be output differently. | |
| 2495 | |
| 2496 Here the argument OPVEC is the vector containing the operands | |
| 2497 extracted from INSN, and NOPERANDS is the number of elements of | |
| 2498 the vector which contain meaningful data for this insn. | |
| 2499 The contents of this vector are what will be used to convert the insn | |
| 2500 template into assembler code, so you can change the assembler output | |
| 2501 by changing the contents of the vector. */ | |
| 2502 | |
| 2503 #define FINAL_PRESCAN_INSN(INSN, OPVEC, NOPERANDS) \ | |
| 2504 final_prescan_insn ((INSN), (OPVEC), (NOPERANDS)) | |
| 2505 | |
| 2506 /* Print operand X (an rtx) in assembler syntax to file FILE. | |
| 2507 CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified. | |
| 2508 For `%' followed by punctuation, CODE is the punctuation and X is null. */ | |
| 2509 | |
| 2510 #define PRINT_OPERAND(STREAM, X, CODE) print_operand ((STREAM), (X), (CODE)) | |
| 2511 | |
| 2512 /* Print a memory address as an operand to reference that memory location. */ | |
| 2513 | |
| 2514 #define PRINT_OPERAND_ADDRESS(STREAM,X) print_operand_address ((STREAM), (X)) | |
| 2515 | |
| 2516 #define PRINT_OPERAND_PUNCT_VALID_P(CHAR) \ | |
| 2517 ((CHAR) == '.' || (CHAR) == '#' || (CHAR) == '@' || (CHAR) == ',' \ | |
| 2518 || (CHAR) == '$' || (CHAR) == '\'' || (CHAR) == '>') | |
| 2519 | |
| 2520 /* Recognize machine-specific patterns that may appear within | |
| 2521 constants. Used for PIC-specific UNSPECs. */ | |
| 2522 #define OUTPUT_ADDR_CONST_EXTRA(STREAM, X, FAIL) \ | |
| 2523 do \ | |
| 2524 if (GET_CODE (X) == UNSPEC) \ | |
| 2525 { \ | |
| 2526 switch (XINT ((X), 1)) \ | |
| 2527 { \ | |
| 2528 case UNSPEC_DATALABEL: \ | |
| 2529 fputs ("datalabel ", (STREAM)); \ | |
| 2530 output_addr_const ((STREAM), XVECEXP ((X), 0, 0)); \ | |
| 2531 break; \ | |
| 2532 case UNSPEC_PIC: \ | |
| 2533 /* GLOBAL_OFFSET_TABLE or local symbols, no suffix. */ \ | |
| 2534 output_addr_const ((STREAM), XVECEXP ((X), 0, 0)); \ | |
| 2535 break; \ | |
| 2536 case UNSPEC_GOT: \ | |
| 2537 output_addr_const ((STREAM), XVECEXP ((X), 0, 0)); \ | |
| 2538 fputs ("@GOT", (STREAM)); \ | |
| 2539 break; \ | |
| 2540 case UNSPEC_GOTOFF: \ | |
| 2541 output_addr_const ((STREAM), XVECEXP ((X), 0, 0)); \ | |
| 2542 fputs ("@GOTOFF", (STREAM)); \ | |
| 2543 break; \ | |
| 2544 case UNSPEC_PLT: \ | |
| 2545 output_addr_const ((STREAM), XVECEXP ((X), 0, 0)); \ | |
| 2546 fputs ("@PLT", (STREAM)); \ | |
| 2547 break; \ | |
| 2548 case UNSPEC_GOTPLT: \ | |
| 2549 output_addr_const ((STREAM), XVECEXP ((X), 0, 0)); \ | |
| 2550 fputs ("@GOTPLT", (STREAM)); \ | |
| 2551 break; \ | |
| 2552 case UNSPEC_DTPOFF: \ | |
| 2553 output_addr_const ((STREAM), XVECEXP ((X), 0, 0)); \ | |
| 2554 fputs ("@DTPOFF", (STREAM)); \ | |
| 2555 break; \ | |
| 2556 case UNSPEC_GOTTPOFF: \ | |
| 2557 output_addr_const ((STREAM), XVECEXP ((X), 0, 0)); \ | |
| 2558 fputs ("@GOTTPOFF", (STREAM)); \ | |
| 2559 break; \ | |
| 2560 case UNSPEC_TPOFF: \ | |
| 2561 output_addr_const ((STREAM), XVECEXP ((X), 0, 0)); \ | |
| 2562 fputs ("@TPOFF", (STREAM)); \ | |
| 2563 break; \ | |
| 2564 case UNSPEC_CALLER: \ | |
| 2565 { \ | |
| 2566 char name[32]; \ | |
| 2567 /* LPCS stands for Label for PIC Call Site. */ \ | |
| 2568 ASM_GENERATE_INTERNAL_LABEL \ | |
| 2569 (name, "LPCS", INTVAL (XVECEXP ((X), 0, 0))); \ | |
| 2570 assemble_name ((STREAM), name); \ | |
| 2571 } \ | |
| 2572 break; \ | |
| 2573 case UNSPEC_EXTRACT_S16: \ | |
| 2574 case UNSPEC_EXTRACT_U16: \ | |
| 2575 { \ | |
| 2576 rtx val, shift; \ | |
| 2577 \ | |
| 2578 val = XVECEXP (X, 0, 0); \ | |
| 2579 shift = XVECEXP (X, 0, 1); \ | |
| 2580 fputc ('(', STREAM); \ | |
| 2581 if (shift != const0_rtx) \ | |
| 2582 fputc ('(', STREAM); \ | |
| 2583 if (GET_CODE (val) == CONST \ | |
| 2584 || GET_RTX_CLASS (GET_CODE (val)) != RTX_OBJ) \ | |
| 2585 { \ | |
| 2586 fputc ('(', STREAM); \ | |
| 2587 output_addr_const (STREAM, val); \ | |
| 2588 fputc (')', STREAM); \ | |
| 2589 } \ | |
| 2590 else \ | |
| 2591 output_addr_const (STREAM, val); \ | |
| 2592 if (shift != const0_rtx) \ | |
| 2593 { \ | |
| 2594 fputs (" >> ", STREAM); \ | |
| 2595 output_addr_const (STREAM, shift); \ | |
| 2596 fputc (')', STREAM); \ | |
| 2597 } \ | |
| 2598 fputs (" & 65535)", STREAM); \ | |
| 2599 } \ | |
| 2600 break; \ | |
| 2601 case UNSPEC_SYMOFF: \ | |
| 2602 output_addr_const (STREAM, XVECEXP (X, 0, 0)); \ | |
| 2603 fputc ('-', STREAM); \ | |
| 2604 if (GET_CODE (XVECEXP (X, 0, 1)) == CONST) \ | |
| 2605 { \ | |
| 2606 fputc ('(', STREAM); \ | |
| 2607 output_addr_const (STREAM, XVECEXP (X, 0, 1)); \ | |
| 2608 fputc (')', STREAM); \ | |
| 2609 } \ | |
| 2610 else \ | |
| 2611 output_addr_const (STREAM, XVECEXP (X, 0, 1)); \ | |
| 2612 break; \ | |
| 2613 case UNSPEC_PCREL_SYMOFF: \ | |
| 2614 output_addr_const (STREAM, XVECEXP (X, 0, 0)); \ | |
| 2615 fputs ("-(", STREAM); \ | |
| 2616 output_addr_const (STREAM, XVECEXP (X, 0, 1)); \ | |
| 2617 fputs ("-.)", STREAM); \ | |
| 2618 break; \ | |
| 2619 default: \ | |
| 2620 goto FAIL; \ | |
| 2621 } \ | |
| 2622 break; \ | |
| 2623 } \ | |
| 2624 else \ | |
| 2625 goto FAIL; \ | |
| 2626 while (0) | |
| 2627 | |
| 2628 | |
| 2629 extern struct rtx_def *sh_compare_op0; | |
| 2630 extern struct rtx_def *sh_compare_op1; | |
| 2631 | |
| 2632 /* Which processor to schedule for. The elements of the enumeration must | |
| 2633 match exactly the cpu attribute in the sh.md file. */ | |
| 2634 | |
| 2635 enum processor_type { | |
| 2636 PROCESSOR_SH1, | |
| 2637 PROCESSOR_SH2, | |
| 2638 PROCESSOR_SH2E, | |
| 2639 PROCESSOR_SH2A, | |
| 2640 PROCESSOR_SH3, | |
| 2641 PROCESSOR_SH3E, | |
| 2642 PROCESSOR_SH4, | |
| 2643 PROCESSOR_SH4A, | |
| 2644 PROCESSOR_SH5 | |
| 2645 }; | |
| 2646 | |
| 2647 #define sh_cpu_attr ((enum attr_cpu)sh_cpu) | |
| 2648 extern enum processor_type sh_cpu; | |
| 2649 | |
| 2650 extern int optimize; /* needed for gen_casesi. */ | |
| 2651 | |
| 2652 enum mdep_reorg_phase_e | |
| 2653 { | |
| 2654 SH_BEFORE_MDEP_REORG, | |
| 2655 SH_INSERT_USES_LABELS, | |
| 2656 SH_SHORTEN_BRANCHES0, | |
| 2657 SH_FIXUP_PCLOAD, | |
| 2658 SH_SHORTEN_BRANCHES1, | |
| 2659 SH_AFTER_MDEP_REORG | |
| 2660 }; | |
| 2661 | |
| 2662 extern enum mdep_reorg_phase_e mdep_reorg_phase; | |
| 2663 | |
| 2664 /* Handle Renesas compiler's pragmas. */ | |
| 2665 #define REGISTER_TARGET_PRAGMAS() do { \ | |
| 2666 c_register_pragma (0, "interrupt", sh_pr_interrupt); \ | |
| 2667 c_register_pragma (0, "trapa", sh_pr_trapa); \ | |
| 2668 c_register_pragma (0, "nosave_low_regs", sh_pr_nosave_low_regs); \ | |
| 2669 } while (0) | |
| 2670 | |
| 2671 extern tree sh_deferred_function_attributes; | |
| 2672 extern tree *sh_deferred_function_attributes_tail; | |
| 2673 | |
| 2674 /* Set when processing a function with interrupt attribute. */ | |
| 2675 | |
| 2676 extern int current_function_interrupt; | |
| 2677 | |
| 2678 | |
| 2679 /* Instructions with unfilled delay slots take up an | |
| 2680 extra two bytes for the nop in the delay slot. | |
| 2681 sh-dsp parallel processing insns are four bytes long. */ | |
| 2682 | |
| 2683 #define ADJUST_INSN_LENGTH(X, LENGTH) \ | |
| 2684 (LENGTH) += sh_insn_length_adjustment (X); | |
| 2685 | |
| 2686 /* Define this macro if it is advisable to hold scalars in registers | |
| 2687 in a wider mode than that declared by the program. In such cases, | |
| 2688 the value is constrained to be within the bounds of the declared | |
| 2689 type, but kept valid in the wider mode. The signedness of the | |
| 2690 extension may differ from that of the type. | |
| 2691 | |
| 2692 Leaving the unsignedp unchanged gives better code than always setting it | |
| 2693 to 0. This is despite the fact that we have only signed char and short | |
| 2694 load instructions. */ | |
| 2695 #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \ | |
| 2696 if (GET_MODE_CLASS (MODE) == MODE_INT \ | |
| 2697 && GET_MODE_SIZE (MODE) < 4/* ! UNITS_PER_WORD */)\ | |
| 2698 (UNSIGNEDP) = ((MODE) == SImode ? 0 : (UNSIGNEDP)), \ | |
| 2699 (MODE) = (TARGET_SH1 ? SImode \ | |
| 2700 : TARGET_SHMEDIA32 ? SImode : DImode); | |
| 2701 | |
| 2702 #define MAX_FIXED_MODE_SIZE (TARGET_SH5 ? 128 : 64) | |
| 2703 | |
| 2704 #define SIDI_OFF (TARGET_LITTLE_ENDIAN ? 0 : 4) | |
| 2705 | |
| 2706 /* ??? Define ACCUMULATE_OUTGOING_ARGS? This is more efficient than pushing | |
| 2707 and popping arguments. However, we do have push/pop instructions, and | |
| 2708 rather limited offsets (4 bits) in load/store instructions, so it isn't | |
| 2709 clear if this would give better code. If implemented, should check for | |
| 2710 compatibility problems. */ | |
| 2711 | |
| 2712 #define SH_DYNAMIC_SHIFT_COST \ | |
| 2713 (TARGET_HARD_SH4 ? 1 : TARGET_SH3 ? (TARGET_SMALLCODE ? 1 : 2) : 20) | |
| 2714 | |
| 2715 | |
| 2716 #define NUM_MODES_FOR_MODE_SWITCHING { FP_MODE_NONE } | |
| 2717 | |
| 2718 #define OPTIMIZE_MODE_SWITCHING(ENTITY) (TARGET_SH4 || TARGET_SH2A_DOUBLE) | |
| 2719 | |
| 2720 #define ACTUAL_NORMAL_MODE(ENTITY) \ | |
| 2721 (TARGET_FPU_SINGLE ? FP_MODE_SINGLE : FP_MODE_DOUBLE) | |
| 2722 | |
| 2723 #define NORMAL_MODE(ENTITY) \ | |
| 2724 (sh_cfun_interrupt_handler_p () \ | |
| 2725 ? (TARGET_FMOVD ? FP_MODE_DOUBLE : FP_MODE_NONE) \ | |
| 2726 : ACTUAL_NORMAL_MODE (ENTITY)) | |
| 2727 | |
| 2728 #define MODE_ENTRY(ENTITY) NORMAL_MODE (ENTITY) | |
| 2729 | |
| 2730 #define MODE_EXIT(ENTITY) \ | |
| 2731 (sh_cfun_attr_renesas_p () ? FP_MODE_NONE : NORMAL_MODE (ENTITY)) | |
| 2732 | |
| 2733 #define EPILOGUE_USES(REGNO) ((TARGET_SH2E || TARGET_SH4) \ | |
| 2734 && (REGNO) == FPSCR_REG) | |
| 2735 | |
| 2736 #define MODE_NEEDED(ENTITY, INSN) \ | |
| 2737 (recog_memoized (INSN) >= 0 \ | |
| 2738 ? get_attr_fp_mode (INSN) \ | |
| 2739 : FP_MODE_NONE) | |
| 2740 | |
| 2741 #define MODE_AFTER(MODE, INSN) \ | |
| 2742 (TARGET_HITACHI \ | |
| 2743 && recog_memoized (INSN) >= 0 \ | |
| 2744 && get_attr_fp_set (INSN) != FP_SET_NONE \ | |
| 2745 ? (int) get_attr_fp_set (INSN) \ | |
| 2746 : (MODE)) | |
| 2747 | |
| 2748 #define MODE_PRIORITY_TO_MODE(ENTITY, N) \ | |
| 2749 ((TARGET_FPU_SINGLE != 0) ^ (N) ? FP_MODE_SINGLE : FP_MODE_DOUBLE) | |
| 2750 | |
| 2751 #define EMIT_MODE_SET(ENTITY, MODE, HARD_REGS_LIVE) \ | |
| 2752 fpscr_set_from_mem ((MODE), (HARD_REGS_LIVE)) | |
| 2753 | |
| 2754 #define MD_CAN_REDIRECT_BRANCH(INSN, SEQ) \ | |
| 2755 sh_can_redirect_branch ((INSN), (SEQ)) | |
| 2756 | |
| 2757 #define DWARF_FRAME_RETURN_COLUMN \ | |
| 2758 (TARGET_SH5 ? DWARF_FRAME_REGNUM (PR_MEDIA_REG) : DWARF_FRAME_REGNUM (PR_REG)) | |
| 2759 | |
| 2760 #define EH_RETURN_DATA_REGNO(N) \ | |
| 2761 ((N) < 4 ? (N) + (TARGET_SH5 ? 2U : 4U) : INVALID_REGNUM) | |
| 2762 | |
| 2763 #define EH_RETURN_STACKADJ_REGNO STATIC_CHAIN_REGNUM | |
| 2764 #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, EH_RETURN_STACKADJ_REGNO) | |
| 2765 | |
| 2766 /* We have to distinguish between code and data, so that we apply | |
| 2767 datalabel where and only where appropriate. Use sdataN for data. */ | |
| 2768 #define ASM_PREFERRED_EH_DATA_FORMAT(CODE, GLOBAL) \ | |
| 2769 ((flag_pic && (GLOBAL) ? DW_EH_PE_indirect : 0) \ | |
| 2770 | (flag_pic ? DW_EH_PE_pcrel : DW_EH_PE_absptr) \ | |
| 2771 | ((CODE) ? 0 : (TARGET_SHMEDIA64 ? DW_EH_PE_sdata8 : DW_EH_PE_sdata4))) | |
| 2772 | |
| 2773 /* Handle special EH pointer encodings. Absolute, pc-relative, and | |
| 2774 indirect are handled automatically. */ | |
| 2775 #define ASM_MAYBE_OUTPUT_ENCODED_ADDR_RTX(FILE, ENCODING, SIZE, ADDR, DONE) \ | |
| 2776 do { \ | |
| 2777 if (((ENCODING) & 0xf) != DW_EH_PE_sdata4 \ | |
| 2778 && ((ENCODING) & 0xf) != DW_EH_PE_sdata8) \ | |
| 2779 { \ | |
| 2780 gcc_assert (GET_CODE (ADDR) == SYMBOL_REF); \ | |
| 2781 SYMBOL_REF_FLAGS (ADDR) |= SYMBOL_FLAG_FUNCTION; \ | |
| 2782 if (0) goto DONE; \ | |
| 2783 } \ | |
| 2784 } while (0) | |
| 2785 | |
| 2786 #if (defined CRT_BEGIN || defined CRT_END) && ! __SHMEDIA__ | |
| 2787 /* SH constant pool breaks the devices in crtstuff.c to control section | |
| 2788 in where code resides. We have to write it as asm code. */ | |
| 2789 #define CRT_CALL_STATIC_FUNCTION(SECTION_OP, FUNC) \ | |
| 2790 asm (SECTION_OP "\n\ | |
| 2791 mov.l 1f,r1\n\ | |
| 2792 mova 2f,r0\n\ | |
| 2793 braf r1\n\ | |
| 2794 lds r0,pr\n\ | |
| 2795 0: .p2align 2\n\ | |
| 2796 1: .long " USER_LABEL_PREFIX #FUNC " - 0b\n\ | |
| 2797 2:\n" TEXT_SECTION_ASM_OP); | |
| 2798 #endif /* (defined CRT_BEGIN || defined CRT_END) && ! __SHMEDIA__ */ | |
| 2799 | |
| 2800 /* FIXME: middle-end support for highpart optimizations is missing. */ | |
| 2801 #define high_life_started reload_in_progress | |
| 2802 | |
| 2803 #endif /* ! GCC_SH_H */ |