comparison gcc/ira-int.h @ 55:77e2b8dfacca gcc-4.4.5

update it from 4.4.3 to 4.5.0
author ryoma <e075725@ie.u-ryukyu.ac.jp>
date Fri, 12 Feb 2010 23:39:51 +0900
parents 58ad6c70ea60
children b7f97abdc517
comparison
equal deleted inserted replaced
52:c156f1bd5cd9 55:77e2b8dfacca
403 regno of the allocno cover class. The member value can be NULL 403 regno of the allocno cover class. The member value can be NULL
404 if all costs are the same. These costs are used to reflect 404 if all costs are the same. These costs are used to reflect
405 preferences of other allocnos not assigned yet during assigning 405 preferences of other allocnos not assigned yet during assigning
406 to given allocno. */ 406 to given allocno. */
407 int *conflict_hard_reg_costs, *updated_conflict_hard_reg_costs; 407 int *conflict_hard_reg_costs, *updated_conflict_hard_reg_costs;
408 /* Number of the same cover class allocnos with TRUE in_graph_p 408 /* Size (in hard registers) of the same cover class allocnos with
409 value and conflicting with given allocno during each point of 409 TRUE in_graph_p value and conflicting with given allocno during
410 graph coloring. */ 410 each point of graph coloring. */
411 int left_conflicts_num; 411 int left_conflicts_size;
412 /* Number of hard registers of the allocno cover class really 412 /* Number of hard registers of the allocno cover class really
413 available for the allocno allocation. */ 413 available for the allocno allocation. */
414 int available_regs_num; 414 int available_regs_num;
415 /* Allocnos in a bucket (used in coloring) chained by the following 415 /* Allocnos in a bucket (used in coloring) chained by the following
416 two members. */ 416 two members. */
462 #define ALLOCNO_UPDATED_HARD_REG_COSTS(A) ((A)->updated_hard_reg_costs) 462 #define ALLOCNO_UPDATED_HARD_REG_COSTS(A) ((A)->updated_hard_reg_costs)
463 #define ALLOCNO_CONFLICT_HARD_REG_COSTS(A) \ 463 #define ALLOCNO_CONFLICT_HARD_REG_COSTS(A) \
464 ((A)->conflict_hard_reg_costs) 464 ((A)->conflict_hard_reg_costs)
465 #define ALLOCNO_UPDATED_CONFLICT_HARD_REG_COSTS(A) \ 465 #define ALLOCNO_UPDATED_CONFLICT_HARD_REG_COSTS(A) \
466 ((A)->updated_conflict_hard_reg_costs) 466 ((A)->updated_conflict_hard_reg_costs)
467 #define ALLOCNO_LEFT_CONFLICTS_NUM(A) ((A)->left_conflicts_num) 467 #define ALLOCNO_LEFT_CONFLICTS_SIZE(A) ((A)->left_conflicts_size)
468 #define ALLOCNO_COVER_CLASS(A) ((A)->cover_class) 468 #define ALLOCNO_COVER_CLASS(A) ((A)->cover_class)
469 #define ALLOCNO_COVER_CLASS_COST(A) ((A)->cover_class_cost) 469 #define ALLOCNO_COVER_CLASS_COST(A) ((A)->cover_class_cost)
470 #define ALLOCNO_UPDATED_COVER_CLASS_COST(A) ((A)->updated_cover_class_cost) 470 #define ALLOCNO_UPDATED_COVER_CLASS_COST(A) ((A)->updated_cover_class_cost)
471 #define ALLOCNO_MEMORY_COST(A) ((A)->memory_cost) 471 #define ALLOCNO_MEMORY_COST(A) ((A)->memory_cost)
472 #define ALLOCNO_UPDATED_MEMORY_COST(A) ((A)->updated_memory_cost) 472 #define ALLOCNO_UPDATED_MEMORY_COST(A) ((A)->updated_memory_cost)
480 #define ALLOCNO_LIVE_RANGES(A) ((A)->live_ranges) 480 #define ALLOCNO_LIVE_RANGES(A) ((A)->live_ranges)
481 #define ALLOCNO_MIN(A) ((A)->min) 481 #define ALLOCNO_MIN(A) ((A)->min)
482 #define ALLOCNO_MAX(A) ((A)->max) 482 #define ALLOCNO_MAX(A) ((A)->max)
483 #define ALLOCNO_CONFLICT_ID(A) ((A)->conflict_id) 483 #define ALLOCNO_CONFLICT_ID(A) ((A)->conflict_id)
484 484
485 /* Map regno -> allocnos with given regno (see comments for 485 /* Map regno -> allocnos with given regno (see comments for
486 allocno member `next_regno_allocno'). */ 486 allocno member `next_regno_allocno'). */
487 extern ira_allocno_t *ira_regno_allocno_map; 487 extern ira_allocno_t *ira_regno_allocno_map;
488 488
489 /* Array of references to all allocnos. The order number of the 489 /* Array of references to all allocnos. The order number of the
490 allocno corresponds to the index in the array. Removed allocnos 490 allocno corresponds to the index in the array. Removed allocnos
563 extern int ira_overall_cost; 563 extern int ira_overall_cost;
564 extern int ira_reg_cost, ira_mem_cost; 564 extern int ira_reg_cost, ira_mem_cost;
565 extern int ira_load_cost, ira_store_cost, ira_shuffle_cost; 565 extern int ira_load_cost, ira_store_cost, ira_shuffle_cost;
566 extern int ira_move_loops_num, ira_additional_jumps_num; 566 extern int ira_move_loops_num, ira_additional_jumps_num;
567 567
568 /* Map: hard register number -> cover class it belongs to. If the 568 /* Maximal value of element of array ira_reg_class_nregs. */
569 corresponding class is NO_REGS, the hard register is not available
570 for allocation. */
571 extern enum reg_class ira_hard_regno_cover_class[FIRST_PSEUDO_REGISTER];
572
573 /* Map: register class x machine mode -> number of hard registers of
574 given class needed to store value of given mode. If the number for
575 some hard-registers of the register class is different, the size
576 will be negative. */
577 extern int ira_reg_class_nregs[N_REG_CLASSES][MAX_MACHINE_MODE];
578
579 /* Maximal value of the previous array elements. */
580 extern int ira_max_nregs; 569 extern int ira_max_nregs;
581 570
582 /* The number of bits in each element of array used to implement a bit 571 /* The number of bits in each element of array used to implement a bit
583 vector of allocnos and what type that element has. We use the 572 vector of allocnos and what type that element has. We use the
584 largest integer format on the host machine. */ 573 largest integer format on the host machine. */
599 __FILE__, __LINE__, __FUNCTION__, _i, _min, _max); \ 588 __FILE__, __LINE__, __FUNCTION__, _i, _min, _max); \
600 gcc_unreachable (); \ 589 gcc_unreachable (); \
601 } \ 590 } \
602 ((R)[(unsigned) (_i - _min) / IRA_INT_BITS] \ 591 ((R)[(unsigned) (_i - _min) / IRA_INT_BITS] \
603 |= ((IRA_INT_TYPE) 1 << ((unsigned) (_i - _min) % IRA_INT_BITS))); })) 592 |= ((IRA_INT_TYPE) 1 << ((unsigned) (_i - _min) % IRA_INT_BITS))); }))
604 593
605 594
606 #define CLEAR_ALLOCNO_SET_BIT(R, I, MIN, MAX) __extension__ \ 595 #define CLEAR_ALLOCNO_SET_BIT(R, I, MIN, MAX) __extension__ \
607 (({ int _min = (MIN), _max = (MAX), _i = (I); \ 596 (({ int _min = (MIN), _max = (MAX), _i = (I); \
608 if (_i < _min || _i > _max) \ 597 if (_i < _min || _i > _max) \
609 { \ 598 { \
689 /* Skip words that are zeros. */ 678 /* Skip words that are zeros. */
690 for (; i->word == 0; i->word = i->vec[i->word_num]) 679 for (; i->word == 0; i->word = i->vec[i->word_num])
691 { 680 {
692 i->word_num++; 681 i->word_num++;
693 i->bit_num = i->word_num * IRA_INT_BITS; 682 i->bit_num = i->word_num * IRA_INT_BITS;
694 683
695 /* If we have reached the end, break. */ 684 /* If we have reached the end, break. */
696 if (i->bit_num >= i->nel) 685 if (i->bit_num >= i->nel)
697 return false; 686 return false;
698 } 687 }
699 688
700 /* Skip bits that are zero. */ 689 /* Skip bits that are zero. */
701 for (; (i->word & 1) == 0; i->word >>= 1) 690 for (; (i->word & 1) == 0; i->word >>= 1)
702 i->bit_num++; 691 i->bit_num++;
703 692
704 *n = (int) i->bit_num + i->start_val; 693 *n = (int) i->bit_num + i->start_val;
705 694
706 return true; 695 return true;
707 } 696 }
708 697
709 /* Advance to the next allocno in the set. */ 698 /* Advance to the next allocno in the set. */
710 static inline void 699 static inline void
728 /* Map: hard regs X modes -> set of hard registers for storing value 717 /* Map: hard regs X modes -> set of hard registers for storing value
729 of given mode starting with given hard register. */ 718 of given mode starting with given hard register. */
730 extern HARD_REG_SET ira_reg_mode_hard_regset 719 extern HARD_REG_SET ira_reg_mode_hard_regset
731 [FIRST_PSEUDO_REGISTER][NUM_MACHINE_MODES]; 720 [FIRST_PSEUDO_REGISTER][NUM_MACHINE_MODES];
732 721
733 /* Arrays analogous to macros MEMORY_MOVE_COST and REGISTER_MOVE_COST. 722 /* Array analogous to macro REGISTER_MOVE_COST. Don't use
734 Don't use ira_register_move_cost directly. Use function of 723 ira_register_move_cost directly. Use function of
735 ira_get_may_move_cost instead. */ 724 ira_get_may_move_cost instead. */
736 extern short ira_memory_move_cost[MAX_MACHINE_MODE][N_REG_CLASSES][2];
737 extern move_table *ira_register_move_cost[MAX_MACHINE_MODE]; 725 extern move_table *ira_register_move_cost[MAX_MACHINE_MODE];
738 726
739 /* Similar to may_move_in_cost but it is calculated in IRA instead of 727 /* Similar to may_move_in_cost but it is calculated in IRA instead of
740 regclass. Another difference we take only available hard registers 728 regclass. Another difference we take only available hard registers
741 into account to figure out that one register class is a subset of 729 into account to figure out that one register class is a subset of
753 /* Register class subset relation: TRUE if the first class is a subset 741 /* Register class subset relation: TRUE if the first class is a subset
754 of the second one considering only hard registers available for the 742 of the second one considering only hard registers available for the
755 allocation. */ 743 allocation. */
756 extern int ira_class_subset_p[N_REG_CLASSES][N_REG_CLASSES]; 744 extern int ira_class_subset_p[N_REG_CLASSES][N_REG_CLASSES];
757 745
758 /* Array of number of hard registers of given class which are
759 available for the allocation. The order is defined by the
760 allocation order. */
761 extern short ira_class_hard_regs[N_REG_CLASSES][FIRST_PSEUDO_REGISTER];
762
763 /* The number of elements of the above array for given register
764 class. */
765 extern int ira_class_hard_regs_num[N_REG_CLASSES];
766
767 /* Index (in ira_class_hard_regs) for given register class and hard 746 /* Index (in ira_class_hard_regs) for given register class and hard
768 register (in general case a hard register can belong to several 747 register (in general case a hard register can belong to several
769 register classes). The index is negative for hard registers 748 register classes). The index is negative for hard registers
770 unavailable for the allocation. */ 749 unavailable for the allocation. */
771 extern short ira_class_hard_reg_index[N_REG_CLASSES][FIRST_PSEUDO_REGISTER]; 750 extern short ira_class_hard_reg_index[N_REG_CLASSES][FIRST_PSEUDO_REGISTER];
772 751
773 /* Function specific hard registers can not be used for the register
774 allocation. */
775 extern HARD_REG_SET ira_no_alloc_regs;
776
777 /* Number of given class hard registers available for the register
778 allocation for given classes. */
779 extern int ira_available_class_regs[N_REG_CLASSES];
780
781 /* Array whose values are hard regset of hard registers available for 752 /* Array whose values are hard regset of hard registers available for
782 the allocation of given register class whose HARD_REGNO_MODE_OK 753 the allocation of given register class whose HARD_REGNO_MODE_OK
783 values for given mode are zero. */ 754 values for given mode are zero. */
784 extern HARD_REG_SET prohibited_class_mode_regs 755 extern HARD_REG_SET prohibited_class_mode_regs
785 [N_REG_CLASSES][NUM_MACHINE_MODES]; 756 [N_REG_CLASSES][NUM_MACHINE_MODES];
787 /* Array whose values are hard regset of hard registers for which 758 /* Array whose values are hard regset of hard registers for which
788 move of the hard register in given mode into itself is 759 move of the hard register in given mode into itself is
789 prohibited. */ 760 prohibited. */
790 extern HARD_REG_SET ira_prohibited_mode_move_regs[NUM_MACHINE_MODES]; 761 extern HARD_REG_SET ira_prohibited_mode_move_regs[NUM_MACHINE_MODES];
791 762
792 /* Number of cover classes. Cover classes is non-intersected register
793 classes containing all hard-registers available for the
794 allocation. */
795 extern int ira_reg_class_cover_size;
796
797 /* The array containing cover classes (see also comments for macro
798 IRA_COVER_CLASSES). Only first IRA_REG_CLASS_COVER_SIZE elements are
799 used for this. */
800 extern enum reg_class ira_reg_class_cover[N_REG_CLASSES];
801
802 /* The value is number of elements in the subsequent array. */ 763 /* The value is number of elements in the subsequent array. */
803 extern int ira_important_classes_num; 764 extern int ira_important_classes_num;
804 765
805 /* The array containing non-empty classes (including non-empty cover 766 /* The array containing non-empty classes (including non-empty cover
806 classes) which are subclasses of cover classes. Such classes is 767 classes) which are subclasses of cover classes. Such classes is
809 770
810 /* The array containing indexes of important classes in the previous 771 /* The array containing indexes of important classes in the previous
811 array. The array elements are defined only for important 772 array. The array elements are defined only for important
812 classes. */ 773 classes. */
813 extern int ira_important_class_nums[N_REG_CLASSES]; 774 extern int ira_important_class_nums[N_REG_CLASSES];
814
815 /* Map of all register classes to corresponding cover class containing
816 the given class. If given class is not a subset of a cover class,
817 we translate it into the cheapest cover class. */
818 extern enum reg_class ira_class_translate[N_REG_CLASSES];
819 775
820 /* The biggest important class inside of intersection of the two 776 /* The biggest important class inside of intersection of the two
821 classes (that is calculated taking only hard registers available 777 classes (that is calculated taking only hard registers available
822 for allocation into account). If the both classes contain no hard 778 for allocation into account). If the both classes contain no hard
823 registers available for allocation, the value is calculated with 779 registers available for allocation, the value is calculated with
1128 { 1084 {
1129 /* Skip words that are zeros. */ 1085 /* Skip words that are zeros. */
1130 for (; i->word == 0; i->word = ((IRA_INT_TYPE *) i->vec)[i->word_num]) 1086 for (; i->word == 0; i->word = ((IRA_INT_TYPE *) i->vec)[i->word_num])
1131 { 1087 {
1132 i->word_num++; 1088 i->word_num++;
1133 1089
1134 /* If we have reached the end, break. */ 1090 /* If we have reached the end, break. */
1135 if (i->word_num * sizeof (IRA_INT_TYPE) >= i->size) 1091 if (i->word_num * sizeof (IRA_INT_TYPE) >= i->size)
1136 return false; 1092 return false;
1137 1093
1138 i->bit_num = i->word_num * IRA_INT_BITS; 1094 i->bit_num = i->word_num * IRA_INT_BITS;
1139 } 1095 }
1140 1096
1141 /* Skip bits that are zero. */ 1097 /* Skip bits that are zero. */
1142 for (; (i->word & 1) == 0; i->word >>= 1) 1098 for (; (i->word & 1) == 0; i->word >>= 1)
1143 i->bit_num++; 1099 i->bit_num++;
1144 1100
1145 *a = ira_conflict_id_allocno_map[i->bit_num + i->base_conflict_id]; 1101 *a = ira_conflict_id_allocno_map[i->bit_num + i->base_conflict_id];
1146 1102
1147 return true; 1103 return true;
1148 } 1104 }
1149 } 1105 }
1150 1106
1151 /* Advance to the next conflicting allocno. */ 1107 /* Advance to the next conflicting allocno. */