--- a/gcc/ira-int.h	Sun Feb 07 18:28:00 2010 +0900
+++ b/gcc/ira-int.h	Fri Feb 12 23:39:51 2010 +0900
@@ -405,10 +405,10 @@
      preferences of other allocnos not assigned yet during assigning
      to given allocno.  */
   int *conflict_hard_reg_costs, *updated_conflict_hard_reg_costs;
-  /* Number of the same cover class allocnos with TRUE in_graph_p
-     value and conflicting with given allocno during each point of
-     graph coloring.  */
-  int left_conflicts_num;
+  /* Size (in hard registers) of the same cover class allocnos with
+     TRUE in_graph_p value and conflicting with given allocno during
+     each point of graph coloring.  */
+  int left_conflicts_size;
   /* Number of hard registers of the allocno cover class really
      available for the allocno allocation.  */
   int available_regs_num;
@@ -464,7 +464,7 @@
   ((A)->conflict_hard_reg_costs)
 #define ALLOCNO_UPDATED_CONFLICT_HARD_REG_COSTS(A) \
   ((A)->updated_conflict_hard_reg_costs)
-#define ALLOCNO_LEFT_CONFLICTS_NUM(A) ((A)->left_conflicts_num)
+#define ALLOCNO_LEFT_CONFLICTS_SIZE(A) ((A)->left_conflicts_size)
 #define ALLOCNO_COVER_CLASS(A) ((A)->cover_class)
 #define ALLOCNO_COVER_CLASS_COST(A) ((A)->cover_class_cost)
 #define ALLOCNO_UPDATED_COVER_CLASS_COST(A) ((A)->updated_cover_class_cost)
@@ -482,7 +482,7 @@
 #define ALLOCNO_MAX(A) ((A)->max)
 #define ALLOCNO_CONFLICT_ID(A) ((A)->conflict_id)
 
-/* Map regno -> allocnos with given regno (see comments for 
+/* Map regno -> allocnos with given regno (see comments for
    allocno member `next_regno_allocno').  */
 extern ira_allocno_t *ira_regno_allocno_map;
 
@@ -565,18 +565,7 @@
 extern int ira_load_cost, ira_store_cost, ira_shuffle_cost;
 extern int ira_move_loops_num, ira_additional_jumps_num;
 
-/* Map: hard register number -> cover class it belongs to.  If the
-   corresponding class is NO_REGS, the hard register is not available
-   for allocation.  */
-extern enum reg_class ira_hard_regno_cover_class[FIRST_PSEUDO_REGISTER];
-
-/* Map: register class x machine mode -> number of hard registers of
-   given class needed to store value of given mode.  If the number for
-   some hard-registers of the register class is different, the size
-   will be negative.  */
-extern int ira_reg_class_nregs[N_REG_CLASSES][MAX_MACHINE_MODE];
-
-/* Maximal value of the previous array elements.  */
+/* Maximal value of element of array ira_reg_class_nregs.  */
 extern int ira_max_nregs;
 
 /* The number of bits in each element of array used to implement a bit
@@ -601,7 +590,7 @@
        }								\
      ((R)[(unsigned) (_i - _min) / IRA_INT_BITS]			\
       |= ((IRA_INT_TYPE) 1 << ((unsigned) (_i - _min) % IRA_INT_BITS))); }))
-  
+
 
 #define CLEAR_ALLOCNO_SET_BIT(R, I, MIN, MAX) __extension__	        \
   (({ int _min = (MIN), _max = (MAX), _i = (I);				\
@@ -691,18 +680,18 @@
     {
       i->word_num++;
       i->bit_num = i->word_num * IRA_INT_BITS;
-      
+
       /* If we have reached the end, break.  */
       if (i->bit_num >= i->nel)
 	return false;
     }
-  
+
   /* Skip bits that are zero.  */
   for (; (i->word & 1) == 0; i->word >>= 1)
     i->bit_num++;
-  
+
   *n = (int) i->bit_num + i->start_val;
-  
+
   return true;
 }
 
@@ -730,10 +719,9 @@
 extern HARD_REG_SET ira_reg_mode_hard_regset
                     [FIRST_PSEUDO_REGISTER][NUM_MACHINE_MODES];
 
-/* Arrays analogous to macros MEMORY_MOVE_COST and REGISTER_MOVE_COST.
-   Don't use ira_register_move_cost directly.  Use function of
+/* Array analogous to macro REGISTER_MOVE_COST.  Don't use
+   ira_register_move_cost directly.  Use function of
    ira_get_may_move_cost instead.  */
-extern short ira_memory_move_cost[MAX_MACHINE_MODE][N_REG_CLASSES][2];
 extern move_table *ira_register_move_cost[MAX_MACHINE_MODE];
 
 /* Similar to may_move_in_cost but it is calculated in IRA instead of
@@ -755,29 +743,12 @@
    allocation.  */
 extern int ira_class_subset_p[N_REG_CLASSES][N_REG_CLASSES];
 
-/* Array of number of hard registers of given class which are
-   available for the allocation.  The order is defined by the
-   allocation order.  */
-extern short ira_class_hard_regs[N_REG_CLASSES][FIRST_PSEUDO_REGISTER];
-
-/* The number of elements of the above array for given register
-   class.  */
-extern int ira_class_hard_regs_num[N_REG_CLASSES];
-
 /* Index (in ira_class_hard_regs) for given register class and hard
    register (in general case a hard register can belong to several
    register classes).  The index is negative for hard registers
    unavailable for the allocation. */
 extern short ira_class_hard_reg_index[N_REG_CLASSES][FIRST_PSEUDO_REGISTER];
 
-/* Function specific hard registers can not be used for the register
-   allocation.  */
-extern HARD_REG_SET ira_no_alloc_regs;
-
-/* Number of given class hard registers available for the register
-   allocation for given classes.  */
-extern int ira_available_class_regs[N_REG_CLASSES];
-
 /* Array whose values are hard regset of hard registers available for
    the allocation of given register class whose HARD_REGNO_MODE_OK
    values for given mode are zero.  */
@@ -789,16 +760,6 @@
    prohibited.  */
 extern HARD_REG_SET ira_prohibited_mode_move_regs[NUM_MACHINE_MODES];
 
-/* Number of cover classes.  Cover classes is non-intersected register
-   classes containing all hard-registers available for the
-   allocation.  */
-extern int ira_reg_class_cover_size;
-
-/* The array containing cover classes (see also comments for macro
-   IRA_COVER_CLASSES).  Only first IRA_REG_CLASS_COVER_SIZE elements are
-   used for this.  */
-extern enum reg_class ira_reg_class_cover[N_REG_CLASSES];
-
 /* The value is number of elements in the subsequent array.  */
 extern int ira_important_classes_num;
 
@@ -812,11 +773,6 @@
    classes.  */
 extern int ira_important_class_nums[N_REG_CLASSES];
 
-/* Map of all register classes to corresponding cover class containing
-   the given class.  If given class is not a subset of a cover class,
-   we translate it into the cheapest cover class.  */
-extern enum reg_class ira_class_translate[N_REG_CLASSES];
-
 /* The biggest important class inside of intersection of the two
    classes (that is calculated taking only hard registers available
    for allocation into account).  If the both classes contain no hard
@@ -1130,20 +1086,20 @@
       for (; i->word == 0; i->word = ((IRA_INT_TYPE *) i->vec)[i->word_num])
 	{
 	  i->word_num++;
-	  
+
 	  /* If we have reached the end, break.  */
 	  if (i->word_num * sizeof (IRA_INT_TYPE) >= i->size)
 	    return false;
-	  
+
 	  i->bit_num = i->word_num * IRA_INT_BITS;
 	}
-      
+
       /* Skip bits that are zero.  */
       for (; (i->word & 1) == 0; i->word >>= 1)
 	i->bit_num++;
-      
+
       *a = ira_conflict_id_allocno_map[i->bit_num + i->base_conflict_id];
-      
+
       return true;
     }
 }