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comparison gcc/config/aarch64/iterators.md @ 131:84e7813d76e9

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gcc-8.2
author mir3636
date Thu, 25 Oct 2018 07:37:49 +0900
parents 04ced10e8804
children 1830386684a0
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111:04ced10e8804 131:84e7813d76e9
1 ;; Machine description for AArch64 architecture. 1 ;; Machine description for AArch64 architecture.
2 ;; Copyright (C) 2009-2017 Free Software Foundation, Inc. 2 ;; Copyright (C) 2009-2018 Free Software Foundation, Inc.
3 ;; Contributed by ARM Ltd. 3 ;; Contributed by ARM Ltd.
4 ;; 4 ;;
5 ;; This file is part of GCC. 5 ;; This file is part of GCC.
6 ;; 6 ;;
7 ;; GCC is free software; you can redistribute it and/or modify it 7 ;; GCC is free software; you can redistribute it and/or modify it
33 (define_mode_iterator SHORT [QI HI]) 33 (define_mode_iterator SHORT [QI HI])
34 34
35 ;; Iterator for all integer modes (up to 64-bit) 35 ;; Iterator for all integer modes (up to 64-bit)
36 (define_mode_iterator ALLI [QI HI SI DI]) 36 (define_mode_iterator ALLI [QI HI SI DI])
37 37
38 ;; Iterator for all integer modes (up to 128-bit)
39 (define_mode_iterator ALLI_TI [QI HI SI DI TI])
40
38 ;; Iterator for all integer modes that can be extended (up to 64-bit) 41 ;; Iterator for all integer modes that can be extended (up to 64-bit)
39 (define_mode_iterator ALLX [QI HI SI]) 42 (define_mode_iterator ALLX [QI HI SI])
40 43
41 ;; Iterator for General Purpose Floating-point registers (32- and 64-bit modes) 44 ;; Iterator for General Purpose Floating-point registers (32- and 64-bit modes)
42 (define_mode_iterator GPF [SF DF]) 45 (define_mode_iterator GPF [SF DF])
54 (define_mode_iterator VDF [V2SF V4HF]) 57 (define_mode_iterator VDF [V2SF V4HF])
55 58
56 ;; Iterator for all scalar floating point modes (SF, DF and TF) 59 ;; Iterator for all scalar floating point modes (SF, DF and TF)
57 (define_mode_iterator GPF_TF [SF DF TF]) 60 (define_mode_iterator GPF_TF [SF DF TF])
58 61
59 ;; Integer vector modes. 62 ;; Integer Advanced SIMD modes.
60 (define_mode_iterator VDQ_I [V8QI V16QI V4HI V8HI V2SI V4SI V2DI]) 63 (define_mode_iterator VDQ_I [V8QI V16QI V4HI V8HI V2SI V4SI V2DI])
61 64
62 ;; vector and scalar, 64 & 128-bit container, all integer modes 65 ;; Advanced SIMD and scalar, 64 & 128-bit container, all integer modes.
63 (define_mode_iterator VSDQ_I [V8QI V16QI V4HI V8HI V2SI V4SI V2DI QI HI SI DI]) 66 (define_mode_iterator VSDQ_I [V8QI V16QI V4HI V8HI V2SI V4SI V2DI QI HI SI DI])
64 67
65 ;; vector and scalar, 64 & 128-bit container: all vector integer modes; 68 ;; Advanced SIMD and scalar, 64 & 128-bit container: all Advanced SIMD
66 ;; 64-bit scalar integer mode 69 ;; integer modes; 64-bit scalar integer mode.
67 (define_mode_iterator VSDQ_I_DI [V8QI V16QI V4HI V8HI V2SI V4SI V2DI DI]) 70 (define_mode_iterator VSDQ_I_DI [V8QI V16QI V4HI V8HI V2SI V4SI V2DI DI])
68 71
69 ;; Double vector modes. 72 ;; Double vector modes.
70 (define_mode_iterator VD [V8QI V4HI V4HF V2SI V2SF]) 73 (define_mode_iterator VD [V8QI V4HI V4HF V2SI V2SF])
71 74
72 ;; vector, 64-bit container, all integer modes 75 ;; All modes stored in registers d0-d31.
76 (define_mode_iterator DREG [V8QI V4HI V4HF V2SI V2SF DF])
77
78 ;; Copy of the above.
79 (define_mode_iterator DREG2 [V8QI V4HI V4HF V2SI V2SF DF])
80
81 ;; Advanced SIMD, 64-bit container, all integer modes.
73 (define_mode_iterator VD_BHSI [V8QI V4HI V2SI]) 82 (define_mode_iterator VD_BHSI [V8QI V4HI V2SI])
74 83
75 ;; 128 and 64-bit container; 8, 16, 32-bit vector integer modes 84 ;; 128 and 64-bit container; 8, 16, 32-bit vector integer modes
76 (define_mode_iterator VDQ_BHSI [V8QI V16QI V4HI V8HI V2SI V4SI]) 85 (define_mode_iterator VDQ_BHSI [V8QI V16QI V4HI V8HI V2SI V4SI])
77 86
78 ;; Quad vector modes. 87 ;; Quad vector modes.
79 (define_mode_iterator VQ [V16QI V8HI V4SI V2DI V8HF V4SF V2DF]) 88 (define_mode_iterator VQ [V16QI V8HI V4SI V2DI V8HF V4SF V2DF])
89
90 ;; Copy of the above.
91 (define_mode_iterator VQ2 [V16QI V8HI V4SI V2DI V8HF V4SF V2DF])
92
93 ;; Quad integer vector modes.
94 (define_mode_iterator VQ_I [V16QI V8HI V4SI V2DI])
80 95
81 ;; VQ without 2 element modes. 96 ;; VQ without 2 element modes.
82 (define_mode_iterator VQ_NO2E [V16QI V8HI V4SI V8HF V4SF]) 97 (define_mode_iterator VQ_NO2E [V16QI V8HI V4SI V8HF V4SF])
83 98
84 ;; Quad vector with only 2 element modes. 99 ;; Quad vector with only 2 element modes.
92 107
93 ;; This mode iterator allows :PTR to be used for patterns that operate on 108 ;; This mode iterator allows :PTR to be used for patterns that operate on
94 ;; pointer-sized quantities. Exactly one of the two alternatives will match. 109 ;; pointer-sized quantities. Exactly one of the two alternatives will match.
95 (define_mode_iterator PTR [(SI "ptr_mode == SImode") (DI "ptr_mode == DImode")]) 110 (define_mode_iterator PTR [(SI "ptr_mode == SImode") (DI "ptr_mode == DImode")])
96 111
97 ;; Vector Float modes suitable for moving, loading and storing. 112 ;; Advanced SIMD Float modes suitable for moving, loading and storing.
98 (define_mode_iterator VDQF_F16 [V4HF V8HF V2SF V4SF V2DF]) 113 (define_mode_iterator VDQF_F16 [V4HF V8HF V2SF V4SF V2DF])
99 114
100 ;; Vector Float modes. 115 ;; Advanced SIMD Float modes.
101 (define_mode_iterator VDQF [V2SF V4SF V2DF]) 116 (define_mode_iterator VDQF [V2SF V4SF V2DF])
102 (define_mode_iterator VHSDF [(V4HF "TARGET_SIMD_F16INST") 117 (define_mode_iterator VHSDF [(V4HF "TARGET_SIMD_F16INST")
103 (V8HF "TARGET_SIMD_F16INST") 118 (V8HF "TARGET_SIMD_F16INST")
104 V2SF V4SF V2DF]) 119 V2SF V4SF V2DF])
105 120
106 ;; Vector Float modes, and DF. 121 ;; Advanced SIMD Float modes, and DF.
107 (define_mode_iterator VHSDF_DF [(V4HF "TARGET_SIMD_F16INST") 122 (define_mode_iterator VHSDF_DF [(V4HF "TARGET_SIMD_F16INST")
108 (V8HF "TARGET_SIMD_F16INST") 123 (V8HF "TARGET_SIMD_F16INST")
109 V2SF V4SF V2DF DF]) 124 V2SF V4SF V2DF DF])
110 (define_mode_iterator VHSDF_HSDF [(V4HF "TARGET_SIMD_F16INST") 125 (define_mode_iterator VHSDF_HSDF [(V4HF "TARGET_SIMD_F16INST")
111 (V8HF "TARGET_SIMD_F16INST") 126 (V8HF "TARGET_SIMD_F16INST")
112 V2SF V4SF V2DF 127 V2SF V4SF V2DF
113 (HF "TARGET_SIMD_F16INST") 128 (HF "TARGET_SIMD_F16INST")
114 SF DF]) 129 SF DF])
115 130
116 ;; Vector single Float modes. 131 ;; Advanced SIMD single Float modes.
117 (define_mode_iterator VDQSF [V2SF V4SF]) 132 (define_mode_iterator VDQSF [V2SF V4SF])
118 133
119 ;; Quad vector Float modes with half/single elements. 134 ;; Quad vector Float modes with half/single elements.
120 (define_mode_iterator VQ_HSF [V8HF V4SF]) 135 (define_mode_iterator VQ_HSF [V8HF V4SF])
121 136
122 ;; Modes suitable to use as the return type of a vcond expression. 137 ;; Modes suitable to use as the return type of a vcond expression.
123 (define_mode_iterator VDQF_COND [V2SF V2SI V4SF V4SI V2DF V2DI]) 138 (define_mode_iterator VDQF_COND [V2SF V2SI V4SF V4SI V2DF V2DI])
124 139
125 ;; All Float modes. 140 ;; All scalar and Advanced SIMD Float modes.
126 (define_mode_iterator VALLF [V2SF V4SF V2DF SF DF]) 141 (define_mode_iterator VALLF [V2SF V4SF V2DF SF DF])
127 142
128 ;; Vector Float modes with 2 elements. 143 ;; Advanced SIMD Float modes with 2 elements.
129 (define_mode_iterator V2F [V2SF V2DF]) 144 (define_mode_iterator V2F [V2SF V2DF])
130 145
131 ;; All vector modes on which we support any arithmetic operations. 146 ;; All Advanced SIMD modes on which we support any arithmetic operations.
132 (define_mode_iterator VALL [V8QI V16QI V4HI V8HI V2SI V4SI V2DI V2SF V4SF V2DF]) 147 (define_mode_iterator VALL [V8QI V16QI V4HI V8HI V2SI V4SI V2DI V2SF V4SF V2DF])
133 148
134 ;; All vector modes suitable for moving, loading, and storing. 149 ;; All Advanced SIMD modes suitable for moving, loading, and storing.
135 (define_mode_iterator VALL_F16 [V8QI V16QI V4HI V8HI V2SI V4SI V2DI 150 (define_mode_iterator VALL_F16 [V8QI V16QI V4HI V8HI V2SI V4SI V2DI
136 V4HF V8HF V2SF V4SF V2DF]) 151 V4HF V8HF V2SF V4SF V2DF])
137 152
138 ;; The VALL_F16 modes except the 128-bit 2-element ones. 153 ;; The VALL_F16 modes except the 128-bit 2-element ones.
139 (define_mode_iterator VALL_F16_NO_V2Q [V8QI V16QI V4HI V8HI V2SI V4SI 154 (define_mode_iterator VALL_F16_NO_V2Q [V8QI V16QI V4HI V8HI V2SI V4SI
140 V4HF V8HF V2SF V4SF]) 155 V4HF V8HF V2SF V4SF])
141 156
142 ;; All vector modes barring HF modes, plus DI. 157 ;; All Advanced SIMD modes barring HF modes, plus DI.
143 (define_mode_iterator VALLDI [V8QI V16QI V4HI V8HI V2SI V4SI V2DI V2SF V4SF V2DF DI]) 158 (define_mode_iterator VALLDI [V8QI V16QI V4HI V8HI V2SI V4SI V2DI V2SF V4SF V2DF DI])
144 159
145 ;; All vector modes and DI. 160 ;; All Advanced SIMD modes and DI.
146 (define_mode_iterator VALLDI_F16 [V8QI V16QI V4HI V8HI V2SI V4SI V2DI 161 (define_mode_iterator VALLDI_F16 [V8QI V16QI V4HI V8HI V2SI V4SI V2DI
147 V4HF V8HF V2SF V4SF V2DF DI]) 162 V4HF V8HF V2SF V4SF V2DF DI])
148 163
149 ;; All vector modes, plus DI and DF. 164 ;; All Advanced SIMD modes, plus DI and DF.
150 (define_mode_iterator VALLDIF [V8QI V16QI V4HI V8HI V2SI V4SI 165 (define_mode_iterator VALLDIF [V8QI V16QI V4HI V8HI V2SI V4SI
151 V2DI V4HF V8HF V2SF V4SF V2DF DI DF]) 166 V2DI V4HF V8HF V2SF V4SF V2DF DI DF])
152 167
153 ;; Vector modes for Integer reduction across lanes. 168 ;; Advanced SIMD modes for Integer reduction across lanes.
154 (define_mode_iterator VDQV [V8QI V16QI V4HI V8HI V4SI V2DI]) 169 (define_mode_iterator VDQV [V8QI V16QI V4HI V8HI V4SI V2DI])
155 170
156 ;; Vector modes(except V2DI) for Integer reduction across lanes. 171 ;; Advanced SIMD modes (except V2DI) for Integer reduction across lanes.
157 (define_mode_iterator VDQV_S [V8QI V16QI V4HI V8HI V4SI]) 172 (define_mode_iterator VDQV_S [V8QI V16QI V4HI V8HI V4SI])
158 173
159 ;; All double integer narrow-able modes. 174 ;; All double integer narrow-able modes.
160 (define_mode_iterator VDN [V4HI V2SI DI]) 175 (define_mode_iterator VDN [V4HI V2SI DI])
161 176
162 ;; All quad integer narrow-able modes. 177 ;; All quad integer narrow-able modes.
163 (define_mode_iterator VQN [V8HI V4SI V2DI]) 178 (define_mode_iterator VQN [V8HI V4SI V2DI])
164 179
165 ;; Vector and scalar 128-bit container: narrowable 16, 32, 64-bit integer modes 180 ;; Advanced SIMD and scalar 128-bit container: narrowable 16, 32, 64-bit
181 ;; integer modes
166 (define_mode_iterator VSQN_HSDI [V8HI V4SI V2DI HI SI DI]) 182 (define_mode_iterator VSQN_HSDI [V8HI V4SI V2DI HI SI DI])
167 183
168 ;; All quad integer widen-able modes. 184 ;; All quad integer widen-able modes.
169 (define_mode_iterator VQW [V16QI V8HI V4SI]) 185 (define_mode_iterator VQW [V16QI V8HI V4SI])
170 186
171 ;; Double vector modes for combines. 187 ;; Double vector modes for combines.
172 (define_mode_iterator VDC [V8QI V4HI V4HF V2SI V2SF DI DF]) 188 (define_mode_iterator VDC [V8QI V4HI V4HF V2SI V2SF DI DF])
173 189
174 ;; Vector modes except double int. 190 ;; Advanced SIMD modes except double int.
175 (define_mode_iterator VDQIF [V8QI V16QI V4HI V8HI V2SI V4SI V2SF V4SF V2DF]) 191 (define_mode_iterator VDQIF [V8QI V16QI V4HI V8HI V2SI V4SI V2SF V4SF V2DF])
176 (define_mode_iterator VDQIF_F16 [V8QI V16QI V4HI V8HI V2SI V4SI 192 (define_mode_iterator VDQIF_F16 [V8QI V16QI V4HI V8HI V2SI V4SI
177 V4HF V8HF V2SF V4SF V2DF]) 193 V4HF V8HF V2SF V4SF V2DF])
178 194
179 ;; Vector modes for S type. 195 ;; Advanced SIMD modes for S type.
180 (define_mode_iterator VDQ_SI [V2SI V4SI]) 196 (define_mode_iterator VDQ_SI [V2SI V4SI])
181 197
182 ;; Vector modes for S and D 198 ;; Advanced SIMD modes for S and D.
183 (define_mode_iterator VDQ_SDI [V2SI V4SI V2DI]) 199 (define_mode_iterator VDQ_SDI [V2SI V4SI V2DI])
184 200
185 ;; Vector modes for H, S and D 201 ;; Advanced SIMD modes for H, S and D.
186 (define_mode_iterator VDQ_HSDI [(V4HI "TARGET_SIMD_F16INST") 202 (define_mode_iterator VDQ_HSDI [(V4HI "TARGET_SIMD_F16INST")
187 (V8HI "TARGET_SIMD_F16INST") 203 (V8HI "TARGET_SIMD_F16INST")
188 V2SI V4SI V2DI]) 204 V2SI V4SI V2DI])
189 205
190 ;; Scalar and Vector modes for S and D 206 ;; Scalar and Advanced SIMD modes for S and D.
191 (define_mode_iterator VSDQ_SDI [V2SI V4SI V2DI SI DI]) 207 (define_mode_iterator VSDQ_SDI [V2SI V4SI V2DI SI DI])
192 208
193 ;; Scalar and Vector modes for S and D, Vector modes for H. 209 ;; Scalar and Advanced SIMD modes for S and D, Advanced SIMD modes for H.
194 (define_mode_iterator VSDQ_HSDI [(V4HI "TARGET_SIMD_F16INST") 210 (define_mode_iterator VSDQ_HSDI [(V4HI "TARGET_SIMD_F16INST")
195 (V8HI "TARGET_SIMD_F16INST") 211 (V8HI "TARGET_SIMD_F16INST")
196 V2SI V4SI V2DI 212 V2SI V4SI V2DI
197 (HI "TARGET_SIMD_F16INST") 213 (HI "TARGET_SIMD_F16INST")
198 SI DI]) 214 SI DI])
199 215
200 ;; Vector modes for Q and H types. 216 ;; Advanced SIMD modes for Q and H types.
201 (define_mode_iterator VDQQH [V8QI V16QI V4HI V8HI]) 217 (define_mode_iterator VDQQH [V8QI V16QI V4HI V8HI])
202 218
203 ;; Vector modes for H and S types. 219 ;; Advanced SIMD modes for H and S types.
204 (define_mode_iterator VDQHS [V4HI V8HI V2SI V4SI]) 220 (define_mode_iterator VDQHS [V4HI V8HI V2SI V4SI])
205 221
206 ;; Vector modes for H, S and D types. 222 ;; Advanced SIMD modes for H, S and D types.
207 (define_mode_iterator VDQHSD [V4HI V8HI V2SI V4SI V2DI]) 223 (define_mode_iterator VDQHSD [V4HI V8HI V2SI V4SI V2DI])
208 224
209 ;; Vector and scalar integer modes for H and S 225 ;; Advanced SIMD and scalar integer modes for H and S.
210 (define_mode_iterator VSDQ_HSI [V4HI V8HI V2SI V4SI HI SI]) 226 (define_mode_iterator VSDQ_HSI [V4HI V8HI V2SI V4SI HI SI])
211 227
212 ;; Vector and scalar 64-bit container: 16, 32-bit integer modes 228 ;; Advanced SIMD and scalar 64-bit container: 16, 32-bit integer modes.
213 (define_mode_iterator VSD_HSI [V4HI V2SI HI SI]) 229 (define_mode_iterator VSD_HSI [V4HI V2SI HI SI])
214 230
215 ;; Vector 64-bit container: 16, 32-bit integer modes 231 ;; Advanced SIMD 64-bit container: 16, 32-bit integer modes.
216 (define_mode_iterator VD_HSI [V4HI V2SI]) 232 (define_mode_iterator VD_HSI [V4HI V2SI])
217 233
218 ;; Scalar 64-bit container: 16, 32-bit integer modes 234 ;; Scalar 64-bit container: 16, 32-bit integer modes
219 (define_mode_iterator SD_HSI [HI SI]) 235 (define_mode_iterator SD_HSI [HI SI])
220 236
221 ;; Vector 64-bit container: 16, 32-bit integer modes 237 ;; Advanced SIMD 64-bit container: 16, 32-bit integer modes.
222 (define_mode_iterator VQ_HSI [V8HI V4SI]) 238 (define_mode_iterator VQ_HSI [V8HI V4SI])
223 239
224 ;; All byte modes. 240 ;; All byte modes.
225 (define_mode_iterator VB [V8QI V16QI]) 241 (define_mode_iterator VB [V8QI V16QI])
226 242
227 ;; 2 and 4 lane SI modes. 243 ;; 2 and 4 lane SI modes.
228 (define_mode_iterator VS [V2SI V4SI]) 244 (define_mode_iterator VS [V2SI V4SI])
229 245
230 (define_mode_iterator TX [TI TF]) 246 (define_mode_iterator TX [TI TF])
231 247
232 ;; Opaque structure modes. 248 ;; Advanced SIMD opaque structure modes.
233 (define_mode_iterator VSTRUCT [OI CI XI]) 249 (define_mode_iterator VSTRUCT [OI CI XI])
234 250
235 ;; Double scalar modes 251 ;; Double scalar modes
236 (define_mode_iterator DX [DI DF]) 252 (define_mode_iterator DX [DI DF])
237 253
238 ;; Modes available for <f>mul lane operations. 254 ;; Duplicate of the above
255 (define_mode_iterator DX2 [DI DF])
256
257 ;; Single scalar modes
258 (define_mode_iterator SX [SI SF])
259
260 ;; Duplicate of the above
261 (define_mode_iterator SX2 [SI SF])
262
263 ;; Single and double integer and float modes
264 (define_mode_iterator DSX [DF DI SF SI])
265
266
267 ;; Modes available for Advanced SIMD <f>mul lane operations.
239 (define_mode_iterator VMUL [V4HI V8HI V2SI V4SI 268 (define_mode_iterator VMUL [V4HI V8HI V2SI V4SI
240 (V4HF "TARGET_SIMD_F16INST") 269 (V4HF "TARGET_SIMD_F16INST")
241 (V8HF "TARGET_SIMD_F16INST") 270 (V8HF "TARGET_SIMD_F16INST")
242 V2SF V4SF V2DF]) 271 V2SF V4SF V2DF])
243 272
244 ;; Modes available for <f>mul lane operations changing lane count. 273 ;; Modes available for Advanced SIMD <f>mul lane operations changing lane
274 ;; count.
245 (define_mode_iterator VMUL_CHANGE_NLANES [V4HI V8HI V2SI V4SI V2SF V4SF]) 275 (define_mode_iterator VMUL_CHANGE_NLANES [V4HI V8HI V2SI V4SI V2SF V4SF])
276
277 ;; All SVE vector modes.
278 (define_mode_iterator SVE_ALL [VNx16QI VNx8HI VNx4SI VNx2DI
279 VNx8HF VNx4SF VNx2DF])
280
281 ;; All SVE vector structure modes.
282 (define_mode_iterator SVE_STRUCT [VNx32QI VNx16HI VNx8SI VNx4DI
283 VNx16HF VNx8SF VNx4DF
284 VNx48QI VNx24HI VNx12SI VNx6DI
285 VNx24HF VNx12SF VNx6DF
286 VNx64QI VNx32HI VNx16SI VNx8DI
287 VNx32HF VNx16SF VNx8DF])
288
289 ;; All SVE vector modes that have 8-bit or 16-bit elements.
290 (define_mode_iterator SVE_BH [VNx16QI VNx8HI VNx8HF])
291
292 ;; All SVE vector modes that have 8-bit, 16-bit or 32-bit elements.
293 (define_mode_iterator SVE_BHS [VNx16QI VNx8HI VNx4SI VNx8HF VNx4SF])
294
295 ;; All SVE integer vector modes that have 8-bit, 16-bit or 32-bit elements.
296 (define_mode_iterator SVE_BHSI [VNx16QI VNx8HI VNx4SI])
297
298 ;; All SVE integer vector modes that have 16-bit, 32-bit or 64-bit elements.
299 (define_mode_iterator SVE_HSDI [VNx16QI VNx8HI VNx4SI])
300
301 ;; All SVE floating-point vector modes that have 16-bit or 32-bit elements.
302 (define_mode_iterator SVE_HSF [VNx8HF VNx4SF])
303
304 ;; All SVE vector modes that have 32-bit or 64-bit elements.
305 (define_mode_iterator SVE_SD [VNx4SI VNx2DI VNx4SF VNx2DF])
306
307 ;; All SVE vector modes that have 32-bit elements.
308 (define_mode_iterator SVE_S [VNx4SI VNx4SF])
309
310 ;; All SVE vector modes that have 64-bit elements.
311 (define_mode_iterator SVE_D [VNx2DI VNx2DF])
312
313 ;; All SVE integer vector modes that have 32-bit or 64-bit elements.
314 (define_mode_iterator SVE_SDI [VNx4SI VNx2DI])
315
316 ;; All SVE integer vector modes.
317 (define_mode_iterator SVE_I [VNx16QI VNx8HI VNx4SI VNx2DI])
318
319 ;; All SVE floating-point vector modes.
320 (define_mode_iterator SVE_F [VNx8HF VNx4SF VNx2DF])
321
322 ;; All SVE predicate modes.
323 (define_mode_iterator PRED_ALL [VNx16BI VNx8BI VNx4BI VNx2BI])
324
325 ;; SVE predicate modes that control 8-bit, 16-bit or 32-bit elements.
326 (define_mode_iterator PRED_BHS [VNx16BI VNx8BI VNx4BI])
246 327
247 ;; ------------------------------------------------------------------ 328 ;; ------------------------------------------------------------------
248 ;; Unspec enumerations for Advance SIMD. These could well go into 329 ;; Unspec enumerations for Advance SIMD. These could well go into
249 ;; aarch64.md but for their use in int_iterators here. 330 ;; aarch64.md but for their use in int_iterators here.
250 ;; ------------------------------------------------------------------ 331 ;; ------------------------------------------------------------------
320 UNSPEC_USHLL ; Used in aarch64-simd.md. 401 UNSPEC_USHLL ; Used in aarch64-simd.md.
321 UNSPEC_ADDP ; Used in aarch64-simd.md. 402 UNSPEC_ADDP ; Used in aarch64-simd.md.
322 UNSPEC_TBL ; Used in vector permute patterns. 403 UNSPEC_TBL ; Used in vector permute patterns.
323 UNSPEC_TBX ; Used in vector permute patterns. 404 UNSPEC_TBX ; Used in vector permute patterns.
324 UNSPEC_CONCAT ; Used in vector permute patterns. 405 UNSPEC_CONCAT ; Used in vector permute patterns.
406
407 ;; The following permute unspecs are generated directly by
408 ;; aarch64_expand_vec_perm_const, so any changes to the underlying
409 ;; instructions would need a corresponding change there.
325 UNSPEC_ZIP1 ; Used in vector permute patterns. 410 UNSPEC_ZIP1 ; Used in vector permute patterns.
326 UNSPEC_ZIP2 ; Used in vector permute patterns. 411 UNSPEC_ZIP2 ; Used in vector permute patterns.
327 UNSPEC_UZP1 ; Used in vector permute patterns. 412 UNSPEC_UZP1 ; Used in vector permute patterns.
328 UNSPEC_UZP2 ; Used in vector permute patterns. 413 UNSPEC_UZP2 ; Used in vector permute patterns.
329 UNSPEC_TRN1 ; Used in vector permute patterns. 414 UNSPEC_TRN1 ; Used in vector permute patterns.
330 UNSPEC_TRN2 ; Used in vector permute patterns. 415 UNSPEC_TRN2 ; Used in vector permute patterns.
331 UNSPEC_EXT ; Used in aarch64-simd.md. 416 UNSPEC_EXT ; Used in vector permute patterns.
332 UNSPEC_REV64 ; Used in vector reverse patterns (permute). 417 UNSPEC_REV64 ; Used in vector reverse patterns (permute).
333 UNSPEC_REV32 ; Used in vector reverse patterns (permute). 418 UNSPEC_REV32 ; Used in vector reverse patterns (permute).
334 UNSPEC_REV16 ; Used in vector reverse patterns (permute). 419 UNSPEC_REV16 ; Used in vector reverse patterns (permute).
420
335 UNSPEC_AESE ; Used in aarch64-simd.md. 421 UNSPEC_AESE ; Used in aarch64-simd.md.
336 UNSPEC_AESD ; Used in aarch64-simd.md. 422 UNSPEC_AESD ; Used in aarch64-simd.md.
337 UNSPEC_AESMC ; Used in aarch64-simd.md. 423 UNSPEC_AESMC ; Used in aarch64-simd.md.
338 UNSPEC_AESIMC ; Used in aarch64-simd.md. 424 UNSPEC_AESIMC ; Used in aarch64-simd.md.
339 UNSPEC_SHA1C ; Used in aarch64-simd.md. 425 UNSPEC_SHA1C ; Used in aarch64-simd.md.
354 UNSPEC_SQRDMLSH ; Used in aarch64-simd.md. 440 UNSPEC_SQRDMLSH ; Used in aarch64-simd.md.
355 UNSPEC_FMAXNM ; Used in aarch64-simd.md. 441 UNSPEC_FMAXNM ; Used in aarch64-simd.md.
356 UNSPEC_FMINNM ; Used in aarch64-simd.md. 442 UNSPEC_FMINNM ; Used in aarch64-simd.md.
357 UNSPEC_SDOT ; Used in aarch64-simd.md. 443 UNSPEC_SDOT ; Used in aarch64-simd.md.
358 UNSPEC_UDOT ; Used in aarch64-simd.md. 444 UNSPEC_UDOT ; Used in aarch64-simd.md.
445 UNSPEC_SM3SS1 ; Used in aarch64-simd.md.
446 UNSPEC_SM3TT1A ; Used in aarch64-simd.md.
447 UNSPEC_SM3TT1B ; Used in aarch64-simd.md.
448 UNSPEC_SM3TT2A ; Used in aarch64-simd.md.
449 UNSPEC_SM3TT2B ; Used in aarch64-simd.md.
450 UNSPEC_SM3PARTW1 ; Used in aarch64-simd.md.
451 UNSPEC_SM3PARTW2 ; Used in aarch64-simd.md.
452 UNSPEC_SM4E ; Used in aarch64-simd.md.
453 UNSPEC_SM4EKEY ; Used in aarch64-simd.md.
454 UNSPEC_SHA512H ; Used in aarch64-simd.md.
455 UNSPEC_SHA512H2 ; Used in aarch64-simd.md.
456 UNSPEC_SHA512SU0 ; Used in aarch64-simd.md.
457 UNSPEC_SHA512SU1 ; Used in aarch64-simd.md.
458 UNSPEC_FMLAL ; Used in aarch64-simd.md.
459 UNSPEC_FMLSL ; Used in aarch64-simd.md.
460 UNSPEC_FMLAL2 ; Used in aarch64-simd.md.
461 UNSPEC_FMLSL2 ; Used in aarch64-simd.md.
462 UNSPEC_SEL ; Used in aarch64-sve.md.
463 UNSPEC_ANDV ; Used in aarch64-sve.md.
464 UNSPEC_IORV ; Used in aarch64-sve.md.
465 UNSPEC_XORV ; Used in aarch64-sve.md.
466 UNSPEC_ANDF ; Used in aarch64-sve.md.
467 UNSPEC_IORF ; Used in aarch64-sve.md.
468 UNSPEC_XORF ; Used in aarch64-sve.md.
469 UNSPEC_SMUL_HIGHPART ; Used in aarch64-sve.md.
470 UNSPEC_UMUL_HIGHPART ; Used in aarch64-sve.md.
471 UNSPEC_COND_ADD ; Used in aarch64-sve.md.
472 UNSPEC_COND_SUB ; Used in aarch64-sve.md.
473 UNSPEC_COND_MUL ; Used in aarch64-sve.md.
474 UNSPEC_COND_DIV ; Used in aarch64-sve.md.
475 UNSPEC_COND_MAX ; Used in aarch64-sve.md.
476 UNSPEC_COND_MIN ; Used in aarch64-sve.md.
477 UNSPEC_COND_FMLA ; Used in aarch64-sve.md.
478 UNSPEC_COND_FMLS ; Used in aarch64-sve.md.
479 UNSPEC_COND_FNMLA ; Used in aarch64-sve.md.
480 UNSPEC_COND_FNMLS ; Used in aarch64-sve.md.
481 UNSPEC_COND_LT ; Used in aarch64-sve.md.
482 UNSPEC_COND_LE ; Used in aarch64-sve.md.
483 UNSPEC_COND_EQ ; Used in aarch64-sve.md.
484 UNSPEC_COND_NE ; Used in aarch64-sve.md.
485 UNSPEC_COND_GE ; Used in aarch64-sve.md.
486 UNSPEC_COND_GT ; Used in aarch64-sve.md.
487 UNSPEC_LASTB ; Used in aarch64-sve.md.
359 ]) 488 ])
360 489
361 ;; ------------------------------------------------------------------ 490 ;; ------------------------------------------------------------------
362 ;; Unspec enumerations for Atomics. They are here so that they can be 491 ;; Unspec enumerations for Atomics. They are here so that they can be
363 ;; used in the int_iterators for atomic operations. 492 ;; used in the int_iterators for atomic operations.
396 525
397 ;; For inequal width int to float conversion 526 ;; For inequal width int to float conversion
398 (define_mode_attr w1 [(HF "w") (SF "w") (DF "x")]) 527 (define_mode_attr w1 [(HF "w") (SF "w") (DF "x")])
399 (define_mode_attr w2 [(HF "x") (SF "x") (DF "w")]) 528 (define_mode_attr w2 [(HF "x") (SF "x") (DF "w")])
400 529
530 ;; For width of fp registers in fcvt instruction
531 (define_mode_attr fpw [(DI "s") (SI "d")])
532
401 (define_mode_attr short_mask [(HI "65535") (QI "255")]) 533 (define_mode_attr short_mask [(HI "65535") (QI "255")])
402 534
403 ;; For constraints used in scalar immediate vector moves 535 ;; For constraints used in scalar immediate vector moves
404 (define_mode_attr hq [(HI "h") (QI "q")]) 536 (define_mode_attr hq [(HI "h") (QI "q")])
405 537
406 ;; For doubling width of an integer mode 538 ;; For doubling width of an integer mode
407 (define_mode_attr DWI [(QI "HI") (HI "SI") (SI "DI") (DI "TI")]) 539 (define_mode_attr DWI [(QI "HI") (HI "SI") (SI "DI") (DI "TI")])
540
541 (define_mode_attr fcvt_change_mode [(SI "df") (DI "sf")])
542
543 (define_mode_attr FCVT_CHANGE_MODE [(SI "DF") (DI "SF")])
408 544
409 ;; For scalar usage of vector/FP registers 545 ;; For scalar usage of vector/FP registers
410 (define_mode_attr v [(QI "b") (HI "h") (SI "s") (DI "d") 546 (define_mode_attr v [(QI "b") (HI "h") (SI "s") (DI "d")
411 (HF "h") (SF "s") (DF "d") 547 (HF "h") (SF "s") (DF "d")
412 (V8QI "") (V16QI "") 548 (V8QI "") (V16QI "")
436 ;; we are doing scalar for DI and SIMD for SI (ignoring all but 572 ;; we are doing scalar for DI and SIMD for SI (ignoring all but
437 ;; lane 0). 573 ;; lane 0).
438 (define_mode_attr rtn [(DI "d") (SI "")]) 574 (define_mode_attr rtn [(DI "d") (SI "")])
439 (define_mode_attr vas [(DI "") (SI ".2s")]) 575 (define_mode_attr vas [(DI "") (SI ".2s")])
440 576
441 ;; Map a floating point mode to the appropriate register name prefix 577 ;; Map a vector to the number of units in it, if the size of the mode
442 (define_mode_attr s [(HF "h") (SF "s") (DF "d")]) 578 ;; is constant.
579 (define_mode_attr nunits [(V8QI "8") (V16QI "16")
580 (V4HI "4") (V8HI "8")
581 (V2SI "2") (V4SI "4")
582 (V2DI "2")
583 (V4HF "4") (V8HF "8")
584 (V2SF "2") (V4SF "4")
585 (V1DF "1") (V2DF "2")
586 (DI "1") (DF "1")])
587
588 ;; Map a mode to the number of bits in it, if the size of the mode
589 ;; is constant.
590 (define_mode_attr bitsize [(V8QI "64") (V16QI "128")
591 (V4HI "64") (V8HI "128")
592 (V2SI "64") (V4SI "128")
593 (V2DI "128")])
594
595 ;; Map a floating point or integer mode to the appropriate register name prefix
596 (define_mode_attr s [(HF "h") (SF "s") (DF "d") (SI "s") (DI "d")])
443 597
444 ;; Give the length suffix letter for a sign- or zero-extension. 598 ;; Give the length suffix letter for a sign- or zero-extension.
445 (define_mode_attr size [(QI "b") (HI "h") (SI "w")]) 599 (define_mode_attr size [(QI "b") (HI "h") (SI "w")])
446 600
447 ;; Give the number of bits in the mode 601 ;; Give the number of bits in the mode
456 ;; Attribute to describe constants acceptable in logical and operations 610 ;; Attribute to describe constants acceptable in logical and operations
457 (define_mode_attr lconst2 [(SI "UsO") (DI "UsP")]) 611 (define_mode_attr lconst2 [(SI "UsO") (DI "UsP")])
458 612
459 ;; Map a mode to a specific constraint character. 613 ;; Map a mode to a specific constraint character.
460 (define_mode_attr cmode [(QI "q") (HI "h") (SI "s") (DI "d")]) 614 (define_mode_attr cmode [(QI "q") (HI "h") (SI "s") (DI "d")])
615
616 ;; Map modes to Usg and Usj constraints for SISD right shifts
617 (define_mode_attr cmode_simd [(SI "g") (DI "j")])
461 618
462 (define_mode_attr Vtype [(V8QI "8b") (V16QI "16b") 619 (define_mode_attr Vtype [(V8QI "8b") (V16QI "16b")
463 (V4HI "4h") (V8HI "8h") 620 (V4HI "4h") (V8HI "8h")
464 (V2SI "2s") (V4SI "4s") 621 (V2SI "2s") (V4SI "4s")
465 (DI "1d") (DF "1d") 622 (DI "1d") (DF "1d")
486 (V2DI ".2s") 643 (V2DI ".2s")
487 (DI "") (SI "") 644 (DI "") (SI "")
488 (HI "")]) 645 (HI "")])
489 646
490 ;; Mode-to-individual element type mapping. 647 ;; Mode-to-individual element type mapping.
491 (define_mode_attr Vetype [(V8QI "b") (V16QI "b") 648 (define_mode_attr Vetype [(V8QI "b") (V16QI "b") (VNx16QI "b") (VNx16BI "b")
492 (V4HI "h") (V8HI "h") 649 (V4HI "h") (V8HI "h") (VNx8HI "h") (VNx8BI "h")
493 (V2SI "s") (V4SI "s") 650 (V2SI "s") (V4SI "s") (VNx4SI "s") (VNx4BI "s")
494 (V2DI "d") (V4HF "h") 651 (V2DI "d") (VNx2DI "d") (VNx2BI "d")
495 (V8HF "h") (V2SF "s") 652 (V4HF "h") (V8HF "h") (VNx8HF "h")
496 (V4SF "s") (V2DF "d") 653 (V2SF "s") (V4SF "s") (VNx4SF "s")
654 (V2DF "d") (VNx2DF "d")
497 (HF "h") 655 (HF "h")
498 (SF "s") (DF "d") 656 (SF "s") (DF "d")
499 (QI "b") (HI "h") 657 (QI "b") (HI "h")
500 (SI "s") (DI "d")]) 658 (SI "s") (DI "d")])
659
660 ;; Equivalent of "size" for a vector element.
661 (define_mode_attr Vesize [(VNx16QI "b")
662 (VNx8HI "h") (VNx8HF "h")
663 (VNx4SI "w") (VNx4SF "w")
664 (VNx2DI "d") (VNx2DF "d")
665 (VNx32QI "b") (VNx48QI "b") (VNx64QI "b")
666 (VNx16HI "h") (VNx24HI "h") (VNx32HI "h")
667 (VNx16HF "h") (VNx24HF "h") (VNx32HF "h")
668 (VNx8SI "w") (VNx12SI "w") (VNx16SI "w")
669 (VNx8SF "w") (VNx12SF "w") (VNx16SF "w")
670 (VNx4DI "d") (VNx6DI "d") (VNx8DI "d")
671 (VNx4DF "d") (VNx6DF "d") (VNx8DF "d")])
501 672
502 ;; Vetype is used everywhere in scheduling type and assembly output, 673 ;; Vetype is used everywhere in scheduling type and assembly output,
503 ;; sometimes they are not the same, for example HF modes on some 674 ;; sometimes they are not the same, for example HF modes on some
504 ;; instructions. stype is defined to represent scheduling type 675 ;; instructions. stype is defined to represent scheduling type
505 ;; more accurately. 676 ;; more accurately.
518 (V4SF "16b") (V2DF "16b") 689 (V4SF "16b") (V2DF "16b")
519 (DI "8b") (DF "8b") 690 (DI "8b") (DF "8b")
520 (SI "8b")]) 691 (SI "8b")])
521 692
522 ;; Define element mode for each vector mode. 693 ;; Define element mode for each vector mode.
523 (define_mode_attr VEL [(V8QI "QI") (V16QI "QI") 694 (define_mode_attr VEL [(V8QI "QI") (V16QI "QI") (VNx16QI "QI")
524 (V4HI "HI") (V8HI "HI") 695 (V4HI "HI") (V8HI "HI") (VNx8HI "HI")
525 (V2SI "SI") (V4SI "SI") 696 (V2SI "SI") (V4SI "SI") (VNx4SI "SI")
526 (DI "DI") (V2DI "DI") 697 (DI "DI") (V2DI "DI") (VNx2DI "DI")
527 (V4HF "HF") (V8HF "HF") 698 (V4HF "HF") (V8HF "HF") (VNx8HF "HF")
528 (V2SF "SF") (V4SF "SF") 699 (V2SF "SF") (V4SF "SF") (VNx4SF "SF")
529 (V2DF "DF") (DF "DF") 700 (DF "DF") (V2DF "DF") (VNx2DF "DF")
530 (SI "SI") (HI "HI") 701 (SI "SI") (HI "HI")
531 (QI "QI")]) 702 (QI "QI")])
532 703
533 ;; Define element mode for each vector mode (lower case). 704 ;; Define element mode for each vector mode (lower case).
534 (define_mode_attr Vel [(V8QI "qi") (V16QI "qi") 705 (define_mode_attr Vel [(V8QI "qi") (V16QI "qi") (VNx16QI "qi")
535 (V4HI "hi") (V8HI "hi") 706 (V4HI "hi") (V8HI "hi") (VNx8HI "hi")
536 (V2SI "si") (V4SI "si") 707 (V2SI "si") (V4SI "si") (VNx4SI "si")
537 (DI "di") (V2DI "di") 708 (DI "di") (V2DI "di") (VNx2DI "di")
538 (V4HF "hf") (V8HF "hf") 709 (V4HF "hf") (V8HF "hf") (VNx8HF "hf")
539 (V2SF "sf") (V4SF "sf") 710 (V2SF "sf") (V4SF "sf") (VNx4SF "sf")
540 (V2DF "df") (DF "df") 711 (V2DF "df") (DF "df") (VNx2DF "df")
541 (SI "si") (HI "hi") 712 (SI "si") (HI "hi")
542 (QI "qi")]) 713 (QI "qi")])
714
715 ;; Element mode with floating-point values replaced by like-sized integers.
716 (define_mode_attr VEL_INT [(VNx16QI "QI")
717 (VNx8HI "HI") (VNx8HF "HI")
718 (VNx4SI "SI") (VNx4SF "SI")
719 (VNx2DI "DI") (VNx2DF "DI")])
720
721 ;; Gives the mode of the 128-bit lowpart of an SVE vector.
722 (define_mode_attr V128 [(VNx16QI "V16QI")
723 (VNx8HI "V8HI") (VNx8HF "V8HF")
724 (VNx4SI "V4SI") (VNx4SF "V4SF")
725 (VNx2DI "V2DI") (VNx2DF "V2DF")])
726
727 ;; ...and again in lower case.
728 (define_mode_attr v128 [(VNx16QI "v16qi")
729 (VNx8HI "v8hi") (VNx8HF "v8hf")
730 (VNx4SI "v4si") (VNx4SF "v4sf")
731 (VNx2DI "v2di") (VNx2DF "v2df")])
543 732
544 ;; 64-bit container modes the inner or scalar source mode. 733 ;; 64-bit container modes the inner or scalar source mode.
545 (define_mode_attr VCOND [(HI "V4HI") (SI "V2SI") 734 (define_mode_attr VCOND [(HI "V4HI") (SI "V2SI")
546 (V4HI "V4HI") (V8HI "V4HI") 735 (V4HI "V4HI") (V8HI "V4HI")
547 (V2SI "V2SI") (V4SI "V2SI") 736 (V2SI "V2SI") (V4SI "V2SI")
617 ;; Register suffix narrowed modes for VQN. 806 ;; Register suffix narrowed modes for VQN.
618 (define_mode_attr V2ntype [(V8HI "16b") (V4SI "8h") 807 (define_mode_attr V2ntype [(V8HI "16b") (V4SI "8h")
619 (V2DI "4s")]) 808 (V2DI "4s")])
620 809
621 ;; Widened modes of vector modes. 810 ;; Widened modes of vector modes.
622 (define_mode_attr VWIDE [(V8QI "V8HI") (V4HI "V4SI") 811 (define_mode_attr VWIDE [(V8QI "V8HI") (V4HI "V4SI")
623 (V2SI "V2DI") (V16QI "V8HI") 812 (V2SI "V2DI") (V16QI "V8HI")
624 (V8HI "V4SI") (V4SI "V2DI") 813 (V8HI "V4SI") (V4SI "V2DI")
625 (HI "SI") (SI "DI") 814 (HI "SI") (SI "DI")
626 (V8HF "V4SF") (V4SF "V2DF") 815 (V8HF "V4SF") (V4SF "V2DF")
627 (V4HF "V4SF") (V2SF "V2DF")] 816 (V4HF "V4SF") (V2SF "V2DF")
628 ) 817 (VNx8HF "VNx4SF") (VNx4SF "VNx2DF")
818 (VNx16QI "VNx8HI") (VNx8HI "VNx4SI")
819 (VNx4SI "VNx2DI")
820 (VNx16BI "VNx8BI") (VNx8BI "VNx4BI")
821 (VNx4BI "VNx2BI")])
822
823 ;; Predicate mode associated with VWIDE.
824 (define_mode_attr VWIDE_PRED [(VNx8HF "VNx4BI") (VNx4SF "VNx2BI")])
629 825
630 ;; Widened modes of vector modes, lowercase 826 ;; Widened modes of vector modes, lowercase
631 (define_mode_attr Vwide [(V2SF "v2df") (V4HF "v4sf")]) 827 (define_mode_attr Vwide [(V2SF "v2df") (V4HF "v4sf")
828 (VNx16QI "vnx8hi") (VNx8HI "vnx4si")
829 (VNx4SI "vnx2di")
830 (VNx8HF "vnx4sf") (VNx4SF "vnx2df")
831 (VNx16BI "vnx8bi") (VNx8BI "vnx4bi")
832 (VNx4BI "vnx2bi")])
632 833
633 ;; Widened mode register suffixes for VD_BHSI/VQW/VQ_HSF. 834 ;; Widened mode register suffixes for VD_BHSI/VQW/VQ_HSF.
634 (define_mode_attr Vwtype [(V8QI "8h") (V4HI "4s") 835 (define_mode_attr Vwtype [(V8QI "8h") (V4HI "4s")
635 (V2SI "2d") (V16QI "8h") 836 (V2SI "2d") (V16QI "8h")
636 (V8HI "4s") (V4SI "2d") 837 (V8HI "4s") (V4SI "2d")
637 (V8HF "4s") (V4SF "2d")]) 838 (V8HF "4s") (V4SF "2d")])
839
840 ;; SVE vector after widening
841 (define_mode_attr Vewtype [(VNx16QI "h")
842 (VNx8HI "s") (VNx8HF "s")
843 (VNx4SI "d") (VNx4SF "d")])
638 844
639 ;; Widened mode register suffixes for VDW/VQW. 845 ;; Widened mode register suffixes for VDW/VQW.
640 (define_mode_attr Vmwtype [(V8QI ".8h") (V4HI ".4s") 846 (define_mode_attr Vmwtype [(V8QI ".8h") (V4HI ".4s")
641 (V2SI ".2d") (V16QI ".8h") 847 (V2SI ".2d") (V16QI ".8h")
642 (V8HI ".4s") (V4SI ".2d") 848 (V8HI ".4s") (V4SI ".2d")
647 (define_mode_attr Vhalftype [(V16QI "8b") (V8HI "4h") 853 (define_mode_attr Vhalftype [(V16QI "8b") (V8HI "4h")
648 (V4SI "2s") (V8HF "4h") 854 (V4SI "2s") (V8HF "4h")
649 (V4SF "2s")]) 855 (V4SF "2s")])
650 856
651 ;; Define corresponding core/FP element mode for each vector mode. 857 ;; Define corresponding core/FP element mode for each vector mode.
652 (define_mode_attr vw [(V8QI "w") (V16QI "w") 858 (define_mode_attr vw [(V8QI "w") (V16QI "w") (VNx16QI "w")
653 (V4HI "w") (V8HI "w") 859 (V4HI "w") (V8HI "w") (VNx8HI "w")
654 (V2SI "w") (V4SI "w") 860 (V2SI "w") (V4SI "w") (VNx4SI "w")
655 (DI "x") (V2DI "x") 861 (DI "x") (V2DI "x") (VNx2DI "x")
656 (V2SF "s") (V4SF "s") 862 (VNx8HF "h")
657 (V2DF "d")]) 863 (V2SF "s") (V4SF "s") (VNx4SF "s")
864 (V2DF "d") (VNx2DF "d")])
658 865
659 ;; Corresponding core element mode for each vector mode. This is a 866 ;; Corresponding core element mode for each vector mode. This is a
660 ;; variation on <vw> mapping FP modes to GP regs. 867 ;; variation on <vw> mapping FP modes to GP regs.
661 (define_mode_attr vwcore [(V8QI "w") (V16QI "w") 868 (define_mode_attr vwcore [(V8QI "w") (V16QI "w") (VNx16QI "w")
662 (V4HI "w") (V8HI "w") 869 (V4HI "w") (V8HI "w") (VNx8HI "w")
663 (V2SI "w") (V4SI "w") 870 (V2SI "w") (V4SI "w") (VNx4SI "w")
664 (DI "x") (V2DI "x") 871 (DI "x") (V2DI "x") (VNx2DI "x")
665 (V4HF "w") (V8HF "w") 872 (V4HF "w") (V8HF "w") (VNx8HF "w")
666 (V2SF "w") (V4SF "w") 873 (V2SF "w") (V4SF "w") (VNx4SF "w")
667 (V2DF "x")]) 874 (V2DF "x") (VNx2DF "x")])
668 875
669 ;; Double vector types for ALLX. 876 ;; Double vector types for ALLX.
670 (define_mode_attr Vallxd [(QI "8b") (HI "4h") (SI "2s")]) 877 (define_mode_attr Vallxd [(QI "8b") (HI "4h") (SI "2s")])
671 878
672 ;; Mode with floating-point values replaced by like-sized integers. 879 ;; Mode with floating-point values replaced by like-sized integers.
674 (V4HI "V4HI") (V8HI "V8HI") 881 (V4HI "V4HI") (V8HI "V8HI")
675 (V2SI "V2SI") (V4SI "V4SI") 882 (V2SI "V2SI") (V4SI "V4SI")
676 (DI "DI") (V2DI "V2DI") 883 (DI "DI") (V2DI "V2DI")
677 (V4HF "V4HI") (V8HF "V8HI") 884 (V4HF "V4HI") (V8HF "V8HI")
678 (V2SF "V2SI") (V4SF "V4SI") 885 (V2SF "V2SI") (V4SF "V4SI")
679 (V2DF "V2DI") (DF "DI") 886 (DF "DI") (V2DF "V2DI")
680 (SF "SI") (HF "HI")]) 887 (SF "SI") (SI "SI")
888 (HF "HI")
889 (VNx16QI "VNx16QI")
890 (VNx8HI "VNx8HI") (VNx8HF "VNx8HI")
891 (VNx4SI "VNx4SI") (VNx4SF "VNx4SI")
892 (VNx2DI "VNx2DI") (VNx2DF "VNx2DI")
893 ])
681 894
682 ;; Lower case mode with floating-point values replaced by like-sized integers. 895 ;; Lower case mode with floating-point values replaced by like-sized integers.
683 (define_mode_attr v_int_equiv [(V8QI "v8qi") (V16QI "v16qi") 896 (define_mode_attr v_int_equiv [(V8QI "v8qi") (V16QI "v16qi")
684 (V4HI "v4hi") (V8HI "v8hi") 897 (V4HI "v4hi") (V8HI "v8hi")
685 (V2SI "v2si") (V4SI "v4si") 898 (V2SI "v2si") (V4SI "v4si")
686 (DI "di") (V2DI "v2di") 899 (DI "di") (V2DI "v2di")
687 (V4HF "v4hi") (V8HF "v8hi") 900 (V4HF "v4hi") (V8HF "v8hi")
688 (V2SF "v2si") (V4SF "v4si") 901 (V2SF "v2si") (V4SF "v4si")
689 (V2DF "v2di") (DF "di") 902 (DF "di") (V2DF "v2di")
690 (SF "si")]) 903 (SF "si")
904 (VNx16QI "vnx16qi")
905 (VNx8HI "vnx8hi") (VNx8HF "vnx8hi")
906 (VNx4SI "vnx4si") (VNx4SF "vnx4si")
907 (VNx2DI "vnx2di") (VNx2DF "vnx2di")
908 ])
909
910 ;; Floating-point equivalent of selected modes.
911 (define_mode_attr V_FP_EQUIV [(VNx4SI "VNx4SF") (VNx4SF "VNx4SF")
912 (VNx2DI "VNx2DF") (VNx2DF "VNx2DF")])
913 (define_mode_attr v_fp_equiv [(VNx4SI "vnx4sf") (VNx4SF "vnx4sf")
914 (VNx2DI "vnx2df") (VNx2DF "vnx2df")])
691 915
692 ;; Mode for vector conditional operations where the comparison has 916 ;; Mode for vector conditional operations where the comparison has
693 ;; different type from the lhs. 917 ;; different type from the lhs.
694 (define_mode_attr V_cmp_mixed [(V2SI "V2SF") (V4SI "V4SF") 918 (define_mode_attr V_cmp_mixed [(V2SI "V2SF") (V4SI "V4SF")
695 (V2DI "V2DF") (V2SF "V2SI") 919 (V2DI "V2DF") (V2SF "V2SI")
811 1035
812 ;; -fpic small model GOT reloc modifers: gotpage_lo15/lo14 for ILP64/32. 1036 ;; -fpic small model GOT reloc modifers: gotpage_lo15/lo14 for ILP64/32.
813 ;; No need of iterator for -fPIC as it use got_lo12 for both modes. 1037 ;; No need of iterator for -fPIC as it use got_lo12 for both modes.
814 (define_mode_attr got_modifier [(SI "gotpage_lo14") (DI "gotpage_lo15")]) 1038 (define_mode_attr got_modifier [(SI "gotpage_lo14") (DI "gotpage_lo15")])
815 1039
1040 ;; Width of 2nd and 3rd arguments to fp16 vector multiply add/sub
1041 (define_mode_attr VFMLA_W [(V2SF "V4HF") (V4SF "V8HF")])
1042
1043 (define_mode_attr VFMLA_SEL_W [(V2SF "V2HF") (V4SF "V4HF")])
1044
1045 (define_mode_attr f16quad [(V2SF "") (V4SF "q")])
1046
1047 (define_code_attr f16mac [(plus "a") (minus "s")])
1048
1049 ;; The number of subvectors in an SVE_STRUCT.
1050 (define_mode_attr vector_count [(VNx32QI "2") (VNx16HI "2")
1051 (VNx8SI "2") (VNx4DI "2")
1052 (VNx16HF "2") (VNx8SF "2") (VNx4DF "2")
1053 (VNx48QI "3") (VNx24HI "3")
1054 (VNx12SI "3") (VNx6DI "3")
1055 (VNx24HF "3") (VNx12SF "3") (VNx6DF "3")
1056 (VNx64QI "4") (VNx32HI "4")
1057 (VNx16SI "4") (VNx8DI "4")
1058 (VNx32HF "4") (VNx16SF "4") (VNx8DF "4")])
1059
1060 ;; The number of instruction bytes needed for an SVE_STRUCT move. This is
1061 ;; equal to vector_count * 4.
1062 (define_mode_attr insn_length [(VNx32QI "8") (VNx16HI "8")
1063 (VNx8SI "8") (VNx4DI "8")
1064 (VNx16HF "8") (VNx8SF "8") (VNx4DF "8")
1065 (VNx48QI "12") (VNx24HI "12")
1066 (VNx12SI "12") (VNx6DI "12")
1067 (VNx24HF "12") (VNx12SF "12") (VNx6DF "12")
1068 (VNx64QI "16") (VNx32HI "16")
1069 (VNx16SI "16") (VNx8DI "16")
1070 (VNx32HF "16") (VNx16SF "16") (VNx8DF "16")])
1071
1072 ;; The type of a subvector in an SVE_STRUCT.
1073 (define_mode_attr VSINGLE [(VNx32QI "VNx16QI")
1074 (VNx16HI "VNx8HI") (VNx16HF "VNx8HF")
1075 (VNx8SI "VNx4SI") (VNx8SF "VNx4SF")
1076 (VNx4DI "VNx2DI") (VNx4DF "VNx2DF")
1077 (VNx48QI "VNx16QI")
1078 (VNx24HI "VNx8HI") (VNx24HF "VNx8HF")
1079 (VNx12SI "VNx4SI") (VNx12SF "VNx4SF")
1080 (VNx6DI "VNx2DI") (VNx6DF "VNx2DF")
1081 (VNx64QI "VNx16QI")
1082 (VNx32HI "VNx8HI") (VNx32HF "VNx8HF")
1083 (VNx16SI "VNx4SI") (VNx16SF "VNx4SF")
1084 (VNx8DI "VNx2DI") (VNx8DF "VNx2DF")])
1085
1086 ;; ...and again in lower case.
1087 (define_mode_attr vsingle [(VNx32QI "vnx16qi")
1088 (VNx16HI "vnx8hi") (VNx16HF "vnx8hf")
1089 (VNx8SI "vnx4si") (VNx8SF "vnx4sf")
1090 (VNx4DI "vnx2di") (VNx4DF "vnx2df")
1091 (VNx48QI "vnx16qi")
1092 (VNx24HI "vnx8hi") (VNx24HF "vnx8hf")
1093 (VNx12SI "vnx4si") (VNx12SF "vnx4sf")
1094 (VNx6DI "vnx2di") (VNx6DF "vnx2df")
1095 (VNx64QI "vnx16qi")
1096 (VNx32HI "vnx8hi") (VNx32HF "vnx8hf")
1097 (VNx16SI "vnx4si") (VNx16SF "vnx4sf")
1098 (VNx8DI "vnx2di") (VNx8DF "vnx2df")])
1099
1100 ;; The predicate mode associated with an SVE data mode. For structure modes
1101 ;; this is equivalent to the <VPRED> of the subvector mode.
1102 (define_mode_attr VPRED [(VNx16QI "VNx16BI")
1103 (VNx8HI "VNx8BI") (VNx8HF "VNx8BI")
1104 (VNx4SI "VNx4BI") (VNx4SF "VNx4BI")
1105 (VNx2DI "VNx2BI") (VNx2DF "VNx2BI")
1106 (VNx32QI "VNx16BI")
1107 (VNx16HI "VNx8BI") (VNx16HF "VNx8BI")
1108 (VNx8SI "VNx4BI") (VNx8SF "VNx4BI")
1109 (VNx4DI "VNx2BI") (VNx4DF "VNx2BI")
1110 (VNx48QI "VNx16BI")
1111 (VNx24HI "VNx8BI") (VNx24HF "VNx8BI")
1112 (VNx12SI "VNx4BI") (VNx12SF "VNx4BI")
1113 (VNx6DI "VNx2BI") (VNx6DF "VNx2BI")
1114 (VNx64QI "VNx16BI")
1115 (VNx32HI "VNx8BI") (VNx32HF "VNx8BI")
1116 (VNx16SI "VNx4BI") (VNx16SF "VNx4BI")
1117 (VNx8DI "VNx2BI") (VNx8DF "VNx2BI")])
1118
1119 ;; ...and again in lower case.
1120 (define_mode_attr vpred [(VNx16QI "vnx16bi")
1121 (VNx8HI "vnx8bi") (VNx8HF "vnx8bi")
1122 (VNx4SI "vnx4bi") (VNx4SF "vnx4bi")
1123 (VNx2DI "vnx2bi") (VNx2DF "vnx2bi")
1124 (VNx32QI "vnx16bi")
1125 (VNx16HI "vnx8bi") (VNx16HF "vnx8bi")
1126 (VNx8SI "vnx4bi") (VNx8SF "vnx4bi")
1127 (VNx4DI "vnx2bi") (VNx4DF "vnx2bi")
1128 (VNx48QI "vnx16bi")
1129 (VNx24HI "vnx8bi") (VNx24HF "vnx8bi")
1130 (VNx12SI "vnx4bi") (VNx12SF "vnx4bi")
1131 (VNx6DI "vnx2bi") (VNx6DF "vnx2bi")
1132 (VNx64QI "vnx16bi")
1133 (VNx32HI "vnx8bi") (VNx32HF "vnx4bi")
1134 (VNx16SI "vnx4bi") (VNx16SF "vnx4bi")
1135 (VNx8DI "vnx2bi") (VNx8DF "vnx2bi")])
1136
816 ;; ------------------------------------------------------------------- 1137 ;; -------------------------------------------------------------------
817 ;; Code Iterators 1138 ;; Code Iterators
818 ;; ------------------------------------------------------------------- 1139 ;; -------------------------------------------------------------------
819 1140
820 ;; This code iterator allows the various shifts supported on the core 1141 ;; This code iterator allows the various shifts supported on the core
823 ;; This code iterator allows the shifts supported in arithmetic instructions 1144 ;; This code iterator allows the shifts supported in arithmetic instructions
824 (define_code_iterator ASHIFT [ashift ashiftrt lshiftrt]) 1145 (define_code_iterator ASHIFT [ashift ashiftrt lshiftrt])
825 1146
826 ;; Code iterator for logical operations 1147 ;; Code iterator for logical operations
827 (define_code_iterator LOGICAL [and ior xor]) 1148 (define_code_iterator LOGICAL [and ior xor])
1149
1150 ;; LOGICAL without AND.
1151 (define_code_iterator LOGICAL_OR [ior xor])
828 1152
829 ;; Code iterator for logical operations whose :nlogical works on SIMD registers. 1153 ;; Code iterator for logical operations whose :nlogical works on SIMD registers.
830 (define_code_iterator NLOGICAL [and ior]) 1154 (define_code_iterator NLOGICAL [and ior])
831 1155
832 ;; Code iterator for unary negate and bitwise complement. 1156 ;; Code iterator for unary negate and bitwise complement.
881 ;; Unsigned comparison operators. 1205 ;; Unsigned comparison operators.
882 (define_code_iterator UCOMPARISONS [ltu leu geu gtu]) 1206 (define_code_iterator UCOMPARISONS [ltu leu geu gtu])
883 1207
884 ;; Unsigned comparison operators. 1208 ;; Unsigned comparison operators.
885 (define_code_iterator FAC_COMPARISONS [lt le ge gt]) 1209 (define_code_iterator FAC_COMPARISONS [lt le ge gt])
1210
1211 ;; SVE integer unary operations.
1212 (define_code_iterator SVE_INT_UNARY [neg not popcount])
1213
1214 ;; SVE floating-point unary operations.
1215 (define_code_iterator SVE_FP_UNARY [neg abs sqrt])
1216
1217 ;; SVE integer binary operations.
1218 (define_code_iterator SVE_INT_BINARY [plus minus mult smax umax smin umin
1219 and ior xor])
1220
1221 ;; SVE integer binary division operations.
1222 (define_code_iterator SVE_INT_BINARY_SD [div udiv])
1223
1224 ;; SVE integer comparisons.
1225 (define_code_iterator SVE_INT_CMP [lt le eq ne ge gt ltu leu geu gtu])
1226
1227 ;; SVE floating-point comparisons.
1228 (define_code_iterator SVE_FP_CMP [lt le eq ne ge gt])
886 1229
887 ;; ------------------------------------------------------------------- 1230 ;; -------------------------------------------------------------------
888 ;; Code Attributes 1231 ;; Code Attributes
889 ;; ------------------------------------------------------------------- 1232 ;; -------------------------------------------------------------------
890 ;; Map rtl objects to optab names 1233 ;; Map rtl objects to optab names
898 (zero_extract "extzv") 1241 (zero_extract "extzv")
899 (fix "fix") 1242 (fix "fix")
900 (unsigned_fix "fixuns") 1243 (unsigned_fix "fixuns")
901 (float "float") 1244 (float "float")
902 (unsigned_float "floatuns") 1245 (unsigned_float "floatuns")
1246 (popcount "popcount")
903 (and "and") 1247 (and "and")
904 (ior "ior") 1248 (ior "ior")
905 (xor "xor") 1249 (xor "xor")
906 (not "one_cmpl") 1250 (not "one_cmpl")
907 (neg "neg") 1251 (neg "neg")
908 (plus "add") 1252 (plus "add")
909 (minus "sub") 1253 (minus "sub")
1254 (mult "mul")
1255 (div "div")
1256 (udiv "udiv")
910 (ss_plus "qadd") 1257 (ss_plus "qadd")
911 (us_plus "qadd") 1258 (us_plus "qadd")
912 (ss_minus "qsub") 1259 (ss_minus "qsub")
913 (us_minus "qsub") 1260 (us_minus "qsub")
914 (ss_neg "qneg") 1261 (ss_neg "qneg")
915 (ss_abs "qabs") 1262 (ss_abs "qabs")
1263 (smin "smin")
1264 (smax "smax")
1265 (umin "umin")
1266 (umax "umax")
916 (eq "eq") 1267 (eq "eq")
917 (ne "ne") 1268 (ne "ne")
918 (lt "lt") 1269 (lt "lt")
919 (ge "ge") 1270 (ge "ge")
920 (le "le") 1271 (le "le")
921 (gt "gt") 1272 (gt "gt")
922 (ltu "ltu") 1273 (ltu "ltu")
923 (leu "leu") 1274 (leu "leu")
924 (geu "geu") 1275 (geu "geu")
925 (gtu "gtu")]) 1276 (gtu "gtu")
1277 (abs "abs")
1278 (sqrt "sqrt")])
926 1279
927 ;; For comparison operators we use the FCM* and CM* instructions. 1280 ;; For comparison operators we use the FCM* and CM* instructions.
928 ;; As there are no CMLE or CMLT instructions which act on 3 vector 1281 ;; As there are no CMLE or CMLT instructions which act on 3 vector
929 ;; operands, we must use CMGE or CMGT and swap the order of the 1282 ;; operands, we must use CMGE or CMGT and swap the order of the
930 ;; source operands. 1283 ;; source operands.
937 (ltu "1") (leu "1") (geu "2") (gtu "2")]) 1290 (ltu "1") (leu "1") (geu "2") (gtu "2")])
938 1291
939 (define_code_attr CMP [(lt "LT") (le "LE") (eq "EQ") (ge "GE") (gt "GT") 1292 (define_code_attr CMP [(lt "LT") (le "LE") (eq "EQ") (ge "GE") (gt "GT")
940 (ltu "LTU") (leu "LEU") (ne "NE") (geu "GEU") 1293 (ltu "LTU") (leu "LEU") (ne "NE") (geu "GEU")
941 (gtu "GTU")]) 1294 (gtu "GTU")])
1295
1296 ;; The AArch64 condition associated with an rtl comparison code.
1297 (define_code_attr cmp_op [(lt "lt")
1298 (le "le")
1299 (eq "eq")
1300 (ne "ne")
1301 (ge "ge")
1302 (gt "gt")
1303 (ltu "lo")
1304 (leu "ls")
1305 (geu "hs")
1306 (gtu "hi")])
942 1307
943 (define_code_attr fix_trunc_optab [(fix "fix_trunc") 1308 (define_code_attr fix_trunc_optab [(fix "fix_trunc")
944 (unsigned_fix "fixuns_trunc")]) 1309 (unsigned_fix "fixuns_trunc")])
945 1310
946 ;; Optab prefix for sign/zero-extending operations 1311 ;; Optab prefix for sign/zero-extending operations
963 (define_code_attr logical [(and "and") (ior "orr") (xor "eor")]) 1328 (define_code_attr logical [(and "and") (ior "orr") (xor "eor")])
964 1329
965 ;; Operation names for negate and bitwise complement. 1330 ;; Operation names for negate and bitwise complement.
966 (define_code_attr neg_not_op [(neg "neg") (not "not")]) 1331 (define_code_attr neg_not_op [(neg "neg") (not "not")])
967 1332
968 ;; Similar, but when not(op) 1333 ;; Similar, but when the second operand is inverted.
969 (define_code_attr nlogical [(and "bic") (ior "orn") (xor "eon")]) 1334 (define_code_attr nlogical [(and "bic") (ior "orn") (xor "eon")])
1335
1336 ;; Similar, but when both operands are inverted.
1337 (define_code_attr logical_nn [(and "nor") (ior "nand")])
970 1338
971 ;; Sign- or zero-extending data-op 1339 ;; Sign- or zero-extending data-op
972 (define_code_attr su [(sign_extend "s") (zero_extend "u") 1340 (define_code_attr su [(sign_extend "s") (zero_extend "u")
973 (sign_extract "s") (zero_extract "u") 1341 (sign_extract "s") (zero_extract "u")
974 (fix "s") (unsigned_fix "u") 1342 (fix "s") (unsigned_fix "u")
975 (div "s") (udiv "u") 1343 (div "s") (udiv "u")
976 (smax "s") (umax "u") 1344 (smax "s") (umax "u")
977 (smin "s") (umin "u")]) 1345 (smin "s") (umin "u")])
978 1346
1347 ;; Whether a shift is left or right.
1348 (define_code_attr lr [(ashift "l") (ashiftrt "r") (lshiftrt "r")])
1349
979 ;; Emit conditional branch instructions. 1350 ;; Emit conditional branch instructions.
980 (define_code_attr bcond [(eq "beq") (ne "bne") (lt "bne") (ge "beq")]) 1351 (define_code_attr bcond [(eq "beq") (ne "bne") (lt "bne") (ge "beq")])
981 1352
982 ;; Emit cbz/cbnz depending on comparison type. 1353 ;; Emit cbz/cbnz depending on comparison type.
983 (define_code_attr cbz [(eq "cbz") (ne "cbnz") (lt "cbnz") (ge "cbz")]) 1354 (define_code_attr cbz [(eq "cbz") (ne "cbnz") (lt "cbnz") (ge "cbz")])
1019 (and "<lconst_atomic>")]) 1390 (and "<lconst_atomic>")])
1020 1391
1021 ;; Attribute to describe constants acceptable in atomic logical operations 1392 ;; Attribute to describe constants acceptable in atomic logical operations
1022 (define_mode_attr lconst_atomic [(QI "K") (HI "K") (SI "K") (DI "L")]) 1393 (define_mode_attr lconst_atomic [(QI "K") (HI "K") (SI "K") (DI "L")])
1023 1394
1395 ;; The integer SVE instruction that implements an rtx code.
1396 (define_code_attr sve_int_op [(plus "add")
1397 (minus "sub")
1398 (mult "mul")
1399 (div "sdiv")
1400 (udiv "udiv")
1401 (neg "neg")
1402 (smin "smin")
1403 (smax "smax")
1404 (umin "umin")
1405 (umax "umax")
1406 (and "and")
1407 (ior "orr")
1408 (xor "eor")
1409 (not "not")
1410 (popcount "cnt")])
1411
1412 (define_code_attr sve_int_op_rev [(plus "add")
1413 (minus "subr")
1414 (mult "mul")
1415 (div "sdivr")
1416 (udiv "udivr")
1417 (smin "smin")
1418 (smax "smax")
1419 (umin "umin")
1420 (umax "umax")
1421 (and "and")
1422 (ior "orr")
1423 (xor "eor")])
1424
1425 ;; The floating-point SVE instruction that implements an rtx code.
1426 (define_code_attr sve_fp_op [(plus "fadd")
1427 (neg "fneg")
1428 (abs "fabs")
1429 (sqrt "fsqrt")])
1430
1431 ;; The SVE immediate constraint to use for an rtl code.
1432 (define_code_attr sve_imm_con [(eq "vsc")
1433 (ne "vsc")
1434 (lt "vsc")
1435 (ge "vsc")
1436 (le "vsc")
1437 (gt "vsc")
1438 (ltu "vsd")
1439 (leu "vsd")
1440 (geu "vsd")
1441 (gtu "vsd")])
1442
1024 ;; ------------------------------------------------------------------- 1443 ;; -------------------------------------------------------------------
1025 ;; Int Iterators. 1444 ;; Int Iterators.
1026 ;; ------------------------------------------------------------------- 1445 ;; -------------------------------------------------------------------
1446
1447 ;; The unspec codes for the SABAL, UABAL AdvancedSIMD instructions.
1448 (define_int_iterator ABAL [UNSPEC_SABAL UNSPEC_UABAL])
1449
1450 ;; The unspec codes for the SABDL2, UABDL2 AdvancedSIMD instructions.
1451 (define_int_iterator ABDL2 [UNSPEC_SABDL2 UNSPEC_UABDL2])
1452
1453 ;; The unspec codes for the SADALP, UADALP AdvancedSIMD instructions.
1454 (define_int_iterator ADALP [UNSPEC_SADALP UNSPEC_UADALP])
1455
1027 (define_int_iterator MAXMINV [UNSPEC_UMAXV UNSPEC_UMINV 1456 (define_int_iterator MAXMINV [UNSPEC_UMAXV UNSPEC_UMINV
1028 UNSPEC_SMAXV UNSPEC_SMINV]) 1457 UNSPEC_SMAXV UNSPEC_SMINV])
1029 1458
1030 (define_int_iterator FMAXMINV [UNSPEC_FMAXV UNSPEC_FMINV 1459 (define_int_iterator FMAXMINV [UNSPEC_FMAXV UNSPEC_FMINV
1031 UNSPEC_FMAXNMV UNSPEC_FMINNMV]) 1460 UNSPEC_FMAXNMV UNSPEC_FMINNMV])
1461
1462 (define_int_iterator BITWISEV [UNSPEC_ANDV UNSPEC_IORV UNSPEC_XORV])
1463
1464 (define_int_iterator LOGICALF [UNSPEC_ANDF UNSPEC_IORF UNSPEC_XORF])
1032 1465
1033 (define_int_iterator HADDSUB [UNSPEC_SHADD UNSPEC_UHADD 1466 (define_int_iterator HADDSUB [UNSPEC_SHADD UNSPEC_UHADD
1034 UNSPEC_SRHADD UNSPEC_URHADD 1467 UNSPEC_SRHADD UNSPEC_URHADD
1035 UNSPEC_SHSUB UNSPEC_UHSUB 1468 UNSPEC_SHSUB UNSPEC_UHSUB
1036 UNSPEC_SRHSUB UNSPEC_URHSUB]) 1469 UNSPEC_SRHSUB UNSPEC_URHSUB])
1037 1470
1471 (define_int_iterator HADD [UNSPEC_SHADD UNSPEC_UHADD])
1472
1473 (define_int_iterator RHADD [UNSPEC_SRHADD UNSPEC_URHADD])
1474
1038 (define_int_iterator DOTPROD [UNSPEC_SDOT UNSPEC_UDOT]) 1475 (define_int_iterator DOTPROD [UNSPEC_SDOT UNSPEC_UDOT])
1039 1476
1040 (define_int_iterator ADDSUBHN [UNSPEC_ADDHN UNSPEC_RADDHN 1477 (define_int_iterator ADDSUBHN [UNSPEC_ADDHN UNSPEC_RADDHN
1041 UNSPEC_SUBHN UNSPEC_RSUBHN]) 1478 UNSPEC_SUBHN UNSPEC_RSUBHN])
1042 1479
1083 1520
1084 (define_int_iterator PERMUTE [UNSPEC_ZIP1 UNSPEC_ZIP2 1521 (define_int_iterator PERMUTE [UNSPEC_ZIP1 UNSPEC_ZIP2
1085 UNSPEC_TRN1 UNSPEC_TRN2 1522 UNSPEC_TRN1 UNSPEC_TRN2
1086 UNSPEC_UZP1 UNSPEC_UZP2]) 1523 UNSPEC_UZP1 UNSPEC_UZP2])
1087 1524
1525 (define_int_iterator OPTAB_PERMUTE [UNSPEC_ZIP1 UNSPEC_ZIP2
1526 UNSPEC_UZP1 UNSPEC_UZP2])
1527
1088 (define_int_iterator REVERSE [UNSPEC_REV64 UNSPEC_REV32 UNSPEC_REV16]) 1528 (define_int_iterator REVERSE [UNSPEC_REV64 UNSPEC_REV32 UNSPEC_REV16])
1089 1529
1090 (define_int_iterator FRINT [UNSPEC_FRINTZ UNSPEC_FRINTP UNSPEC_FRINTM 1530 (define_int_iterator FRINT [UNSPEC_FRINTZ UNSPEC_FRINTP UNSPEC_FRINTM
1091 UNSPEC_FRINTN UNSPEC_FRINTI UNSPEC_FRINTX 1531 UNSPEC_FRINTN UNSPEC_FRINTI UNSPEC_FRINTX
1092 UNSPEC_FRINTA]) 1532 UNSPEC_FRINTA])
1095 UNSPEC_FRINTA UNSPEC_FRINTN]) 1535 UNSPEC_FRINTA UNSPEC_FRINTN])
1096 1536
1097 (define_int_iterator FCVT_F2FIXED [UNSPEC_FCVTZS UNSPEC_FCVTZU]) 1537 (define_int_iterator FCVT_F2FIXED [UNSPEC_FCVTZS UNSPEC_FCVTZU])
1098 (define_int_iterator FCVT_FIXED2F [UNSPEC_SCVTF UNSPEC_UCVTF]) 1538 (define_int_iterator FCVT_FIXED2F [UNSPEC_SCVTF UNSPEC_UCVTF])
1099 1539
1100 (define_int_iterator FRECP [UNSPEC_FRECPE UNSPEC_FRECPX])
1101
1102 (define_int_iterator CRC [UNSPEC_CRC32B UNSPEC_CRC32H UNSPEC_CRC32W 1540 (define_int_iterator CRC [UNSPEC_CRC32B UNSPEC_CRC32H UNSPEC_CRC32W
1103 UNSPEC_CRC32X UNSPEC_CRC32CB UNSPEC_CRC32CH 1541 UNSPEC_CRC32X UNSPEC_CRC32CB UNSPEC_CRC32CH
1104 UNSPEC_CRC32CW UNSPEC_CRC32CX]) 1542 UNSPEC_CRC32CW UNSPEC_CRC32CX])
1105 1543
1106 (define_int_iterator CRYPTO_AES [UNSPEC_AESE UNSPEC_AESD]) 1544 (define_int_iterator CRYPTO_AES [UNSPEC_AESE UNSPEC_AESD])
1108 1546
1109 (define_int_iterator CRYPTO_SHA1 [UNSPEC_SHA1C UNSPEC_SHA1M UNSPEC_SHA1P]) 1547 (define_int_iterator CRYPTO_SHA1 [UNSPEC_SHA1C UNSPEC_SHA1M UNSPEC_SHA1P])
1110 1548
1111 (define_int_iterator CRYPTO_SHA256 [UNSPEC_SHA256H UNSPEC_SHA256H2]) 1549 (define_int_iterator CRYPTO_SHA256 [UNSPEC_SHA256H UNSPEC_SHA256H2])
1112 1550
1551 (define_int_iterator CRYPTO_SHA512 [UNSPEC_SHA512H UNSPEC_SHA512H2])
1552
1553 (define_int_iterator CRYPTO_SM3TT [UNSPEC_SM3TT1A UNSPEC_SM3TT1B
1554 UNSPEC_SM3TT2A UNSPEC_SM3TT2B])
1555
1556 (define_int_iterator CRYPTO_SM3PART [UNSPEC_SM3PARTW1 UNSPEC_SM3PARTW2])
1557
1558 ;; Iterators for fp16 operations
1559
1560 (define_int_iterator VFMLA16_LOW [UNSPEC_FMLAL UNSPEC_FMLSL])
1561
1562 (define_int_iterator VFMLA16_HIGH [UNSPEC_FMLAL2 UNSPEC_FMLSL2])
1563
1564 (define_int_iterator UNPACK [UNSPEC_UNPACKSHI UNSPEC_UNPACKUHI
1565 UNSPEC_UNPACKSLO UNSPEC_UNPACKULO])
1566
1567 (define_int_iterator UNPACK_UNSIGNED [UNSPEC_UNPACKULO UNSPEC_UNPACKUHI])
1568
1569 (define_int_iterator MUL_HIGHPART [UNSPEC_SMUL_HIGHPART UNSPEC_UMUL_HIGHPART])
1570
1571 (define_int_iterator SVE_COND_FP_BINARY [UNSPEC_COND_ADD UNSPEC_COND_SUB
1572 UNSPEC_COND_MUL UNSPEC_COND_DIV
1573 UNSPEC_COND_MAX UNSPEC_COND_MIN])
1574
1575 (define_int_iterator SVE_COND_FP_TERNARY [UNSPEC_COND_FMLA
1576 UNSPEC_COND_FMLS
1577 UNSPEC_COND_FNMLA
1578 UNSPEC_COND_FNMLS])
1579
1580 (define_int_iterator SVE_COND_FP_CMP [UNSPEC_COND_LT UNSPEC_COND_LE
1581 UNSPEC_COND_EQ UNSPEC_COND_NE
1582 UNSPEC_COND_GE UNSPEC_COND_GT])
1583
1113 ;; Iterators for atomic operations. 1584 ;; Iterators for atomic operations.
1114 1585
1115 (define_int_iterator ATOMIC_LDOP 1586 (define_int_iterator ATOMIC_LDOP
1116 [UNSPECV_ATOMIC_LDOP_OR UNSPECV_ATOMIC_LDOP_BIC 1587 [UNSPECV_ATOMIC_LDOP_OR UNSPECV_ATOMIC_LDOP_BIC
1117 UNSPECV_ATOMIC_LDOP_XOR UNSPECV_ATOMIC_LDOP_PLUS]) 1588 UNSPECV_ATOMIC_LDOP_XOR UNSPECV_ATOMIC_LDOP_PLUS])
1121 (UNSPECV_ATOMIC_LDOP_XOR "eor") (UNSPECV_ATOMIC_LDOP_PLUS "add")]) 1592 (UNSPECV_ATOMIC_LDOP_XOR "eor") (UNSPECV_ATOMIC_LDOP_PLUS "add")])
1122 1593
1123 ;; ------------------------------------------------------------------- 1594 ;; -------------------------------------------------------------------
1124 ;; Int Iterators Attributes. 1595 ;; Int Iterators Attributes.
1125 ;; ------------------------------------------------------------------- 1596 ;; -------------------------------------------------------------------
1597
1598 ;; The optab associated with an operation. Note that for ANDF, IORF
1599 ;; and XORF, the optab pattern is not actually defined; we just use this
1600 ;; name for consistency with the integer patterns.
1601 (define_int_attr optab [(UNSPEC_ANDF "and")
1602 (UNSPEC_IORF "ior")
1603 (UNSPEC_XORF "xor")
1604 (UNSPEC_ANDV "and")
1605 (UNSPEC_IORV "ior")
1606 (UNSPEC_XORV "xor")
1607 (UNSPEC_COND_ADD "add")
1608 (UNSPEC_COND_SUB "sub")
1609 (UNSPEC_COND_MUL "mul")
1610 (UNSPEC_COND_DIV "div")
1611 (UNSPEC_COND_MAX "smax")
1612 (UNSPEC_COND_MIN "smin")
1613 (UNSPEC_COND_FMLA "fma")
1614 (UNSPEC_COND_FMLS "fnma")
1615 (UNSPEC_COND_FNMLA "fnms")
1616 (UNSPEC_COND_FNMLS "fms")])
1617
1126 (define_int_attr maxmin_uns [(UNSPEC_UMAXV "umax") 1618 (define_int_attr maxmin_uns [(UNSPEC_UMAXV "umax")
1127 (UNSPEC_UMINV "umin") 1619 (UNSPEC_UMINV "umin")
1128 (UNSPEC_SMAXV "smax") 1620 (UNSPEC_SMAXV "smax")
1129 (UNSPEC_SMINV "smin") 1621 (UNSPEC_SMINV "smin")
1130 (UNSPEC_FMAX "smax_nan") 1622 (UNSPEC_FMAX "smax_nan")
1147 (UNSPEC_FMINNMV "fminnm") 1639 (UNSPEC_FMINNMV "fminnm")
1148 (UNSPEC_FMINV "fmin") 1640 (UNSPEC_FMINV "fmin")
1149 (UNSPEC_FMAXNM "fmaxnm") 1641 (UNSPEC_FMAXNM "fmaxnm")
1150 (UNSPEC_FMINNM "fminnm")]) 1642 (UNSPEC_FMINNM "fminnm")])
1151 1643
1644 (define_int_attr bit_reduc_op [(UNSPEC_ANDV "andv")
1645 (UNSPEC_IORV "orv")
1646 (UNSPEC_XORV "eorv")])
1647
1648 ;; The SVE logical instruction that implements an unspec.
1649 (define_int_attr logicalf_op [(UNSPEC_ANDF "and")
1650 (UNSPEC_IORF "orr")
1651 (UNSPEC_XORF "eor")])
1652
1653 ;; "s" for signed operations and "u" for unsigned ones.
1654 (define_int_attr su [(UNSPEC_UNPACKSHI "s")
1655 (UNSPEC_UNPACKUHI "u")
1656 (UNSPEC_UNPACKSLO "s")
1657 (UNSPEC_UNPACKULO "u")
1658 (UNSPEC_SMUL_HIGHPART "s")
1659 (UNSPEC_UMUL_HIGHPART "u")])
1660
1152 (define_int_attr sur [(UNSPEC_SHADD "s") (UNSPEC_UHADD "u") 1661 (define_int_attr sur [(UNSPEC_SHADD "s") (UNSPEC_UHADD "u")
1153 (UNSPEC_SRHADD "sr") (UNSPEC_URHADD "ur") 1662 (UNSPEC_SRHADD "sr") (UNSPEC_URHADD "ur")
1154 (UNSPEC_SHSUB "s") (UNSPEC_UHSUB "u") 1663 (UNSPEC_SHSUB "s") (UNSPEC_UHSUB "u")
1155 (UNSPEC_SRHSUB "sr") (UNSPEC_URHSUB "ur") 1664 (UNSPEC_SRHSUB "sr") (UNSPEC_URHSUB "ur")
1156 (UNSPEC_ADDHN "") (UNSPEC_RADDHN "r") 1665 (UNSPEC_ADDHN "") (UNSPEC_RADDHN "r")
1666 (UNSPEC_SABAL "s") (UNSPEC_UABAL "u")
1667 (UNSPEC_SABDL2 "s") (UNSPEC_UABDL2 "u")
1668 (UNSPEC_SADALP "s") (UNSPEC_UADALP "u")
1157 (UNSPEC_SUBHN "") (UNSPEC_RSUBHN "r") 1669 (UNSPEC_SUBHN "") (UNSPEC_RSUBHN "r")
1158 (UNSPEC_ADDHN2 "") (UNSPEC_RADDHN2 "r") 1670 (UNSPEC_ADDHN2 "") (UNSPEC_RADDHN2 "r")
1159 (UNSPEC_SUBHN2 "") (UNSPEC_RSUBHN2 "r") 1671 (UNSPEC_SUBHN2 "") (UNSPEC_RSUBHN2 "r")
1160 (UNSPEC_SQXTN "s") (UNSPEC_UQXTN "u") 1672 (UNSPEC_SQXTN "s") (UNSPEC_UQXTN "u")
1161 (UNSPEC_USQADD "us") (UNSPEC_SUQADD "su") 1673 (UNSPEC_USQADD "us") (UNSPEC_SUQADD "su")
1187 (define_int_attr lr [(UNSPEC_SSLI "l") (UNSPEC_USLI "l") 1699 (define_int_attr lr [(UNSPEC_SSLI "l") (UNSPEC_USLI "l")
1188 (UNSPEC_SSRI "r") (UNSPEC_USRI "r")]) 1700 (UNSPEC_SSRI "r") (UNSPEC_USRI "r")])
1189 1701
1190 (define_int_attr u [(UNSPEC_SQSHLU "u") (UNSPEC_SQSHL "") (UNSPEC_UQSHL "") 1702 (define_int_attr u [(UNSPEC_SQSHLU "u") (UNSPEC_SQSHL "") (UNSPEC_UQSHL "")
1191 (UNSPEC_SQSHRUN "u") (UNSPEC_SQRSHRUN "u") 1703 (UNSPEC_SQSHRUN "u") (UNSPEC_SQRSHRUN "u")
1192 (UNSPEC_SQSHRN "") (UNSPEC_UQSHRN "") 1704 (UNSPEC_SQSHRN "") (UNSPEC_UQSHRN "")
1193 (UNSPEC_SQRSHRN "") (UNSPEC_UQRSHRN "")]) 1705 (UNSPEC_SQRSHRN "") (UNSPEC_UQRSHRN "")
1706 (UNSPEC_SHADD "") (UNSPEC_UHADD "u")
1707 (UNSPEC_SRHADD "") (UNSPEC_URHADD "u")])
1194 1708
1195 (define_int_attr addsub [(UNSPEC_SHADD "add") 1709 (define_int_attr addsub [(UNSPEC_SHADD "add")
1196 (UNSPEC_UHADD "add") 1710 (UNSPEC_UHADD "add")
1197 (UNSPEC_SRHADD "add") 1711 (UNSPEC_SRHADD "add")
1198 (UNSPEC_URHADD "add") 1712 (UNSPEC_URHADD "add")
1257 (define_int_attr rev_op [(UNSPEC_REV64 "64") (UNSPEC_REV32 "32") 1771 (define_int_attr rev_op [(UNSPEC_REV64 "64") (UNSPEC_REV32 "32")
1258 (UNSPEC_REV16 "16")]) 1772 (UNSPEC_REV16 "16")])
1259 1773
1260 (define_int_attr perm_hilo [(UNSPEC_ZIP1 "1") (UNSPEC_ZIP2 "2") 1774 (define_int_attr perm_hilo [(UNSPEC_ZIP1 "1") (UNSPEC_ZIP2 "2")
1261 (UNSPEC_TRN1 "1") (UNSPEC_TRN2 "2") 1775 (UNSPEC_TRN1 "1") (UNSPEC_TRN2 "2")
1262 (UNSPEC_UZP1 "1") (UNSPEC_UZP2 "2")]) 1776 (UNSPEC_UZP1 "1") (UNSPEC_UZP2 "2")
1263 1777 (UNSPEC_UNPACKSHI "hi") (UNSPEC_UNPACKUHI "hi")
1264 (define_int_attr frecp_suffix [(UNSPEC_FRECPE "e") (UNSPEC_FRECPX "x")]) 1778 (UNSPEC_UNPACKSLO "lo") (UNSPEC_UNPACKULO "lo")])
1779
1780 ;; Return true if the associated optab refers to the high-numbered lanes,
1781 ;; false if it refers to the low-numbered lanes. The convention is for
1782 ;; "hi" to refer to the low-numbered lanes (the first ones in memory)
1783 ;; for big-endian.
1784 (define_int_attr hi_lanes_optab [(UNSPEC_UNPACKSHI "!BYTES_BIG_ENDIAN")
1785 (UNSPEC_UNPACKUHI "!BYTES_BIG_ENDIAN")
1786 (UNSPEC_UNPACKSLO "BYTES_BIG_ENDIAN")
1787 (UNSPEC_UNPACKULO "BYTES_BIG_ENDIAN")])
1265 1788
1266 (define_int_attr crc_variant [(UNSPEC_CRC32B "crc32b") (UNSPEC_CRC32H "crc32h") 1789 (define_int_attr crc_variant [(UNSPEC_CRC32B "crc32b") (UNSPEC_CRC32H "crc32h")
1267 (UNSPEC_CRC32W "crc32w") (UNSPEC_CRC32X "crc32x") 1790 (UNSPEC_CRC32W "crc32w") (UNSPEC_CRC32X "crc32x")
1268 (UNSPEC_CRC32CB "crc32cb") (UNSPEC_CRC32CH "crc32ch") 1791 (UNSPEC_CRC32CB "crc32cb") (UNSPEC_CRC32CH "crc32ch")
1269 (UNSPEC_CRC32CW "crc32cw") (UNSPEC_CRC32CX "crc32cx")]) 1792 (UNSPEC_CRC32CW "crc32cw") (UNSPEC_CRC32CX "crc32cx")])
1280 (UNSPEC_SHA1M "m")]) 1803 (UNSPEC_SHA1M "m")])
1281 1804
1282 (define_int_attr sha256_op [(UNSPEC_SHA256H "") (UNSPEC_SHA256H2 "2")]) 1805 (define_int_attr sha256_op [(UNSPEC_SHA256H "") (UNSPEC_SHA256H2 "2")])
1283 1806
1284 (define_int_attr rdma_as [(UNSPEC_SQRDMLAH "a") (UNSPEC_SQRDMLSH "s")]) 1807 (define_int_attr rdma_as [(UNSPEC_SQRDMLAH "a") (UNSPEC_SQRDMLSH "s")])
1808
1809 (define_int_attr sha512_op [(UNSPEC_SHA512H "") (UNSPEC_SHA512H2 "2")])
1810
1811 (define_int_attr sm3tt_op [(UNSPEC_SM3TT1A "1a") (UNSPEC_SM3TT1B "1b")
1812 (UNSPEC_SM3TT2A "2a") (UNSPEC_SM3TT2B "2b")])
1813
1814 (define_int_attr sm3part_op [(UNSPEC_SM3PARTW1 "1") (UNSPEC_SM3PARTW2 "2")])
1815
1816 (define_int_attr f16mac1 [(UNSPEC_FMLAL "a") (UNSPEC_FMLSL "s")
1817 (UNSPEC_FMLAL2 "a") (UNSPEC_FMLSL2 "s")])
1818
1819 ;; The condition associated with an UNSPEC_COND_<xx>.
1820 (define_int_attr cmp_op [(UNSPEC_COND_LT "lt")
1821 (UNSPEC_COND_LE "le")
1822 (UNSPEC_COND_EQ "eq")
1823 (UNSPEC_COND_NE "ne")
1824 (UNSPEC_COND_GE "ge")
1825 (UNSPEC_COND_GT "gt")])
1826
1827 (define_int_attr sve_fp_op [(UNSPEC_COND_ADD "fadd")
1828 (UNSPEC_COND_SUB "fsub")
1829 (UNSPEC_COND_MUL "fmul")
1830 (UNSPEC_COND_DIV "fdiv")
1831 (UNSPEC_COND_MAX "fmaxnm")
1832 (UNSPEC_COND_MIN "fminnm")])
1833
1834 (define_int_attr sve_fp_op_rev [(UNSPEC_COND_ADD "fadd")
1835 (UNSPEC_COND_SUB "fsubr")
1836 (UNSPEC_COND_MUL "fmul")
1837 (UNSPEC_COND_DIV "fdivr")
1838 (UNSPEC_COND_MAX "fmaxnm")
1839 (UNSPEC_COND_MIN "fminnm")])
1840
1841 (define_int_attr sve_fmla_op [(UNSPEC_COND_FMLA "fmla")
1842 (UNSPEC_COND_FMLS "fmls")
1843 (UNSPEC_COND_FNMLA "fnmla")
1844 (UNSPEC_COND_FNMLS "fnmls")])
1845
1846 (define_int_attr sve_fmad_op [(UNSPEC_COND_FMLA "fmad")
1847 (UNSPEC_COND_FMLS "fmsb")
1848 (UNSPEC_COND_FNMLA "fnmad")
1849 (UNSPEC_COND_FNMLS "fnmsb")])
1850
1851 (define_int_attr commutative [(UNSPEC_COND_ADD "true")
1852 (UNSPEC_COND_SUB "false")
1853 (UNSPEC_COND_MUL "true")
1854 (UNSPEC_COND_DIV "false")
1855 (UNSPEC_COND_MIN "true")
1856 (UNSPEC_COND_MAX "true")])