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1 ;; Machine description for AArch64 architecture.
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131
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2 ;; Copyright (C) 2009-2018 Free Software Foundation, Inc.
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3 ;; Contributed by ARM Ltd.
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4 ;;
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5 ;; This file is part of GCC.
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6 ;;
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7 ;; GCC is free software; you can redistribute it and/or modify it
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8 ;; under the terms of the GNU General Public License as published by
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9 ;; the Free Software Foundation; either version 3, or (at your option)
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10 ;; any later version.
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11 ;;
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12 ;; GCC is distributed in the hope that it will be useful, but
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13 ;; WITHOUT ANY WARRANTY; without even the implied warranty of
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14 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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15 ;; General Public License for more details.
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16 ;;
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17 ;; You should have received a copy of the GNU General Public License
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18 ;; along with GCC; see the file COPYING3. If not see
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19 ;; <http://www.gnu.org/licenses/>.
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20
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21 ;; -------------------------------------------------------------------
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22 ;; Mode Iterators
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23 ;; -------------------------------------------------------------------
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24
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25
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26 ;; Iterator for General Purpose Integer registers (32- and 64-bit modes)
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27 (define_mode_iterator GPI [SI DI])
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28
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29 ;; Iterator for HI, SI, DI, some instructions can only work on these modes.
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30 (define_mode_iterator GPI_I16 [(HI "AARCH64_ISA_F16") SI DI])
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31
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32 ;; Iterator for QI and HI modes
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33 (define_mode_iterator SHORT [QI HI])
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34
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35 ;; Iterator for all integer modes (up to 64-bit)
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36 (define_mode_iterator ALLI [QI HI SI DI])
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37
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131
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38 ;; Iterator for all integer modes (up to 128-bit)
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39 (define_mode_iterator ALLI_TI [QI HI SI DI TI])
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40
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111
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41 ;; Iterator for all integer modes that can be extended (up to 64-bit)
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42 (define_mode_iterator ALLX [QI HI SI])
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43
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44 ;; Iterator for General Purpose Floating-point registers (32- and 64-bit modes)
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45 (define_mode_iterator GPF [SF DF])
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46
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47 ;; Iterator for all scalar floating point modes (HF, SF, DF)
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48 (define_mode_iterator GPF_F16 [(HF "AARCH64_ISA_F16") SF DF])
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49
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50 ;; Iterator for all scalar floating point modes (HF, SF, DF)
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51 (define_mode_iterator GPF_HF [HF SF DF])
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52
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53 ;; Iterator for all scalar floating point modes (HF, SF, DF and TF)
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54 (define_mode_iterator GPF_TF_F16 [HF SF DF TF])
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55
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56 ;; Double vector modes.
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57 (define_mode_iterator VDF [V2SF V4HF])
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58
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59 ;; Iterator for all scalar floating point modes (SF, DF and TF)
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60 (define_mode_iterator GPF_TF [SF DF TF])
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61
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131
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62 ;; Integer Advanced SIMD modes.
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111
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63 (define_mode_iterator VDQ_I [V8QI V16QI V4HI V8HI V2SI V4SI V2DI])
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64
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131
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65 ;; Advanced SIMD and scalar, 64 & 128-bit container, all integer modes.
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111
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66 (define_mode_iterator VSDQ_I [V8QI V16QI V4HI V8HI V2SI V4SI V2DI QI HI SI DI])
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67
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131
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68 ;; Advanced SIMD and scalar, 64 & 128-bit container: all Advanced SIMD
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69 ;; integer modes; 64-bit scalar integer mode.
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111
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70 (define_mode_iterator VSDQ_I_DI [V8QI V16QI V4HI V8HI V2SI V4SI V2DI DI])
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71
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72 ;; Double vector modes.
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73 (define_mode_iterator VD [V8QI V4HI V4HF V2SI V2SF])
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74
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131
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75 ;; All modes stored in registers d0-d31.
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76 (define_mode_iterator DREG [V8QI V4HI V4HF V2SI V2SF DF])
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77
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78 ;; Copy of the above.
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79 (define_mode_iterator DREG2 [V8QI V4HI V4HF V2SI V2SF DF])
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80
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81 ;; Advanced SIMD, 64-bit container, all integer modes.
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82 (define_mode_iterator VD_BHSI [V8QI V4HI V2SI])
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83
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84 ;; 128 and 64-bit container; 8, 16, 32-bit vector integer modes
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85 (define_mode_iterator VDQ_BHSI [V8QI V16QI V4HI V8HI V2SI V4SI])
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86
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87 ;; Quad vector modes.
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88 (define_mode_iterator VQ [V16QI V8HI V4SI V2DI V8HF V4SF V2DF])
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89
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131
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90 ;; Copy of the above.
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91 (define_mode_iterator VQ2 [V16QI V8HI V4SI V2DI V8HF V4SF V2DF])
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92
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93 ;; Quad integer vector modes.
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94 (define_mode_iterator VQ_I [V16QI V8HI V4SI V2DI])
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95
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96 ;; VQ without 2 element modes.
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97 (define_mode_iterator VQ_NO2E [V16QI V8HI V4SI V8HF V4SF])
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98
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99 ;; Quad vector with only 2 element modes.
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100 (define_mode_iterator VQ_2E [V2DI V2DF])
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101
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102 ;; This mode iterator allows :P to be used for patterns that operate on
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103 ;; addresses in different modes. In LP64, only DI will match, while in
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104 ;; ILP32, either can match.
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105 (define_mode_iterator P [(SI "ptr_mode == SImode || Pmode == SImode")
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106 (DI "ptr_mode == DImode || Pmode == DImode")])
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107
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108 ;; This mode iterator allows :PTR to be used for patterns that operate on
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109 ;; pointer-sized quantities. Exactly one of the two alternatives will match.
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110 (define_mode_iterator PTR [(SI "ptr_mode == SImode") (DI "ptr_mode == DImode")])
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111
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131
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112 ;; Advanced SIMD Float modes suitable for moving, loading and storing.
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111
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113 (define_mode_iterator VDQF_F16 [V4HF V8HF V2SF V4SF V2DF])
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114
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131
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115 ;; Advanced SIMD Float modes.
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111
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116 (define_mode_iterator VDQF [V2SF V4SF V2DF])
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117 (define_mode_iterator VHSDF [(V4HF "TARGET_SIMD_F16INST")
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118 (V8HF "TARGET_SIMD_F16INST")
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119 V2SF V4SF V2DF])
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120
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131
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121 ;; Advanced SIMD Float modes, and DF.
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111
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122 (define_mode_iterator VHSDF_DF [(V4HF "TARGET_SIMD_F16INST")
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123 (V8HF "TARGET_SIMD_F16INST")
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124 V2SF V4SF V2DF DF])
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125 (define_mode_iterator VHSDF_HSDF [(V4HF "TARGET_SIMD_F16INST")
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126 (V8HF "TARGET_SIMD_F16INST")
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127 V2SF V4SF V2DF
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128 (HF "TARGET_SIMD_F16INST")
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129 SF DF])
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130
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131
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131 ;; Advanced SIMD single Float modes.
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111
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132 (define_mode_iterator VDQSF [V2SF V4SF])
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133
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134 ;; Quad vector Float modes with half/single elements.
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135 (define_mode_iterator VQ_HSF [V8HF V4SF])
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136
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137 ;; Modes suitable to use as the return type of a vcond expression.
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138 (define_mode_iterator VDQF_COND [V2SF V2SI V4SF V4SI V2DF V2DI])
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139
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131
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140 ;; All scalar and Advanced SIMD Float modes.
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111
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141 (define_mode_iterator VALLF [V2SF V4SF V2DF SF DF])
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142
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131
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143 ;; Advanced SIMD Float modes with 2 elements.
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111
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144 (define_mode_iterator V2F [V2SF V2DF])
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145
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131
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146 ;; All Advanced SIMD modes on which we support any arithmetic operations.
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111
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147 (define_mode_iterator VALL [V8QI V16QI V4HI V8HI V2SI V4SI V2DI V2SF V4SF V2DF])
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148
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131
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149 ;; All Advanced SIMD modes suitable for moving, loading, and storing.
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150 (define_mode_iterator VALL_F16 [V8QI V16QI V4HI V8HI V2SI V4SI V2DI
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151 V4HF V8HF V2SF V4SF V2DF])
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152
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153 ;; The VALL_F16 modes except the 128-bit 2-element ones.
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154 (define_mode_iterator VALL_F16_NO_V2Q [V8QI V16QI V4HI V8HI V2SI V4SI
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155 V4HF V8HF V2SF V4SF])
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156
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157 ;; All Advanced SIMD modes barring HF modes, plus DI.
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158 (define_mode_iterator VALLDI [V8QI V16QI V4HI V8HI V2SI V4SI V2DI V2SF V4SF V2DF DI])
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159
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160 ;; All Advanced SIMD modes and DI.
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111
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161 (define_mode_iterator VALLDI_F16 [V8QI V16QI V4HI V8HI V2SI V4SI V2DI
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162 V4HF V8HF V2SF V4SF V2DF DI])
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163
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164 ;; All Advanced SIMD modes, plus DI and DF.
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111
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165 (define_mode_iterator VALLDIF [V8QI V16QI V4HI V8HI V2SI V4SI
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166 V2DI V4HF V8HF V2SF V4SF V2DF DI DF])
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167
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168 ;; Advanced SIMD modes for Integer reduction across lanes.
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169 (define_mode_iterator VDQV [V8QI V16QI V4HI V8HI V4SI V2DI])
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170
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171 ;; Advanced SIMD modes (except V2DI) for Integer reduction across lanes.
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172 (define_mode_iterator VDQV_S [V8QI V16QI V4HI V8HI V4SI])
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173
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174 ;; All double integer narrow-able modes.
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175 (define_mode_iterator VDN [V4HI V2SI DI])
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176
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177 ;; All quad integer narrow-able modes.
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178 (define_mode_iterator VQN [V8HI V4SI V2DI])
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179
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180 ;; Advanced SIMD and scalar 128-bit container: narrowable 16, 32, 64-bit
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181 ;; integer modes
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182 (define_mode_iterator VSQN_HSDI [V8HI V4SI V2DI HI SI DI])
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183
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184 ;; All quad integer widen-able modes.
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185 (define_mode_iterator VQW [V16QI V8HI V4SI])
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186
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187 ;; Double vector modes for combines.
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188 (define_mode_iterator VDC [V8QI V4HI V4HF V2SI V2SF DI DF])
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189
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190 ;; Advanced SIMD modes except double int.
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191 (define_mode_iterator VDQIF [V8QI V16QI V4HI V8HI V2SI V4SI V2SF V4SF V2DF])
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192 (define_mode_iterator VDQIF_F16 [V8QI V16QI V4HI V8HI V2SI V4SI
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193 V4HF V8HF V2SF V4SF V2DF])
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194
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195 ;; Advanced SIMD modes for S type.
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111
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196 (define_mode_iterator VDQ_SI [V2SI V4SI])
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197
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131
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198 ;; Advanced SIMD modes for S and D.
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199 (define_mode_iterator VDQ_SDI [V2SI V4SI V2DI])
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200
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131
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201 ;; Advanced SIMD modes for H, S and D.
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202 (define_mode_iterator VDQ_HSDI [(V4HI "TARGET_SIMD_F16INST")
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203 (V8HI "TARGET_SIMD_F16INST")
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204 V2SI V4SI V2DI])
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205
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206 ;; Scalar and Advanced SIMD modes for S and D.
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111
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207 (define_mode_iterator VSDQ_SDI [V2SI V4SI V2DI SI DI])
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208
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209 ;; Scalar and Advanced SIMD modes for S and D, Advanced SIMD modes for H.
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210 (define_mode_iterator VSDQ_HSDI [(V4HI "TARGET_SIMD_F16INST")
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211 (V8HI "TARGET_SIMD_F16INST")
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212 V2SI V4SI V2DI
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213 (HI "TARGET_SIMD_F16INST")
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214 SI DI])
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215
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131
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216 ;; Advanced SIMD modes for Q and H types.
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111
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217 (define_mode_iterator VDQQH [V8QI V16QI V4HI V8HI])
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218
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219 ;; Advanced SIMD modes for H and S types.
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111
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220 (define_mode_iterator VDQHS [V4HI V8HI V2SI V4SI])
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221
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222 ;; Advanced SIMD modes for H, S and D types.
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111
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223 (define_mode_iterator VDQHSD [V4HI V8HI V2SI V4SI V2DI])
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224
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225 ;; Advanced SIMD and scalar integer modes for H and S.
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111
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226 (define_mode_iterator VSDQ_HSI [V4HI V8HI V2SI V4SI HI SI])
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227
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131
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228 ;; Advanced SIMD and scalar 64-bit container: 16, 32-bit integer modes.
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111
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229 (define_mode_iterator VSD_HSI [V4HI V2SI HI SI])
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230
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131
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231 ;; Advanced SIMD 64-bit container: 16, 32-bit integer modes.
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111
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232 (define_mode_iterator VD_HSI [V4HI V2SI])
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233
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234 ;; Scalar 64-bit container: 16, 32-bit integer modes
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235 (define_mode_iterator SD_HSI [HI SI])
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236
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131
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237 ;; Advanced SIMD 64-bit container: 16, 32-bit integer modes.
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111
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238 (define_mode_iterator VQ_HSI [V8HI V4SI])
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239
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240 ;; All byte modes.
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241 (define_mode_iterator VB [V8QI V16QI])
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242
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243 ;; 2 and 4 lane SI modes.
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244 (define_mode_iterator VS [V2SI V4SI])
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245
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246 (define_mode_iterator TX [TI TF])
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247
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131
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248 ;; Advanced SIMD opaque structure modes.
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111
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249 (define_mode_iterator VSTRUCT [OI CI XI])
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250
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251 ;; Double scalar modes
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252 (define_mode_iterator DX [DI DF])
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253
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131
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254 ;; Duplicate of the above
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255 (define_mode_iterator DX2 [DI DF])
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256
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257 ;; Single scalar modes
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258 (define_mode_iterator SX [SI SF])
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259
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260 ;; Duplicate of the above
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261 (define_mode_iterator SX2 [SI SF])
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262
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263 ;; Single and double integer and float modes
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264 (define_mode_iterator DSX [DF DI SF SI])
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265
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266
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267 ;; Modes available for Advanced SIMD <f>mul lane operations.
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111
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268 (define_mode_iterator VMUL [V4HI V8HI V2SI V4SI
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269 (V4HF "TARGET_SIMD_F16INST")
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270 (V8HF "TARGET_SIMD_F16INST")
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271 V2SF V4SF V2DF])
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272
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131
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273 ;; Modes available for Advanced SIMD <f>mul lane operations changing lane
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274 ;; count.
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111
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275 (define_mode_iterator VMUL_CHANGE_NLANES [V4HI V8HI V2SI V4SI V2SF V4SF])
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276
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131
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277 ;; All SVE vector modes.
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278 (define_mode_iterator SVE_ALL [VNx16QI VNx8HI VNx4SI VNx2DI
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279 VNx8HF VNx4SF VNx2DF])
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280
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281 ;; All SVE vector structure modes.
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282 (define_mode_iterator SVE_STRUCT [VNx32QI VNx16HI VNx8SI VNx4DI
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283 VNx16HF VNx8SF VNx4DF
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284 VNx48QI VNx24HI VNx12SI VNx6DI
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285 VNx24HF VNx12SF VNx6DF
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286 VNx64QI VNx32HI VNx16SI VNx8DI
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287 VNx32HF VNx16SF VNx8DF])
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288
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289 ;; All SVE vector modes that have 8-bit or 16-bit elements.
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290 (define_mode_iterator SVE_BH [VNx16QI VNx8HI VNx8HF])
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291
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292 ;; All SVE vector modes that have 8-bit, 16-bit or 32-bit elements.
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293 (define_mode_iterator SVE_BHS [VNx16QI VNx8HI VNx4SI VNx8HF VNx4SF])
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294
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295 ;; All SVE integer vector modes that have 8-bit, 16-bit or 32-bit elements.
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296 (define_mode_iterator SVE_BHSI [VNx16QI VNx8HI VNx4SI])
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297
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298 ;; All SVE integer vector modes that have 16-bit, 32-bit or 64-bit elements.
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299 (define_mode_iterator SVE_HSDI [VNx16QI VNx8HI VNx4SI])
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300
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301 ;; All SVE floating-point vector modes that have 16-bit or 32-bit elements.
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302 (define_mode_iterator SVE_HSF [VNx8HF VNx4SF])
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303
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304 ;; All SVE vector modes that have 32-bit or 64-bit elements.
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305 (define_mode_iterator SVE_SD [VNx4SI VNx2DI VNx4SF VNx2DF])
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306
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307 ;; All SVE vector modes that have 32-bit elements.
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308 (define_mode_iterator SVE_S [VNx4SI VNx4SF])
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309
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310 ;; All SVE vector modes that have 64-bit elements.
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311 (define_mode_iterator SVE_D [VNx2DI VNx2DF])
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312
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313 ;; All SVE integer vector modes that have 32-bit or 64-bit elements.
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314 (define_mode_iterator SVE_SDI [VNx4SI VNx2DI])
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315
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316 ;; All SVE integer vector modes.
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317 (define_mode_iterator SVE_I [VNx16QI VNx8HI VNx4SI VNx2DI])
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318
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319 ;; All SVE floating-point vector modes.
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320 (define_mode_iterator SVE_F [VNx8HF VNx4SF VNx2DF])
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321
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322 ;; All SVE predicate modes.
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323 (define_mode_iterator PRED_ALL [VNx16BI VNx8BI VNx4BI VNx2BI])
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324
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325 ;; SVE predicate modes that control 8-bit, 16-bit or 32-bit elements.
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326 (define_mode_iterator PRED_BHS [VNx16BI VNx8BI VNx4BI])
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327
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111
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328 ;; ------------------------------------------------------------------
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329 ;; Unspec enumerations for Advance SIMD. These could well go into
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330 ;; aarch64.md but for their use in int_iterators here.
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331 ;; ------------------------------------------------------------------
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332
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333 (define_c_enum "unspec"
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334 [
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335 UNSPEC_ASHIFT_SIGNED ; Used in aarch-simd.md.
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336 UNSPEC_ASHIFT_UNSIGNED ; Used in aarch64-simd.md.
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337 UNSPEC_ABS ; Used in aarch64-simd.md.
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338 UNSPEC_FMAX ; Used in aarch64-simd.md.
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339 UNSPEC_FMAXNMV ; Used in aarch64-simd.md.
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340 UNSPEC_FMAXV ; Used in aarch64-simd.md.
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341 UNSPEC_FMIN ; Used in aarch64-simd.md.
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342 UNSPEC_FMINNMV ; Used in aarch64-simd.md.
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343 UNSPEC_FMINV ; Used in aarch64-simd.md.
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344 UNSPEC_FADDV ; Used in aarch64-simd.md.
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345 UNSPEC_ADDV ; Used in aarch64-simd.md.
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346 UNSPEC_SMAXV ; Used in aarch64-simd.md.
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347 UNSPEC_SMINV ; Used in aarch64-simd.md.
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348 UNSPEC_UMAXV ; Used in aarch64-simd.md.
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349 UNSPEC_UMINV ; Used in aarch64-simd.md.
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350 UNSPEC_SHADD ; Used in aarch64-simd.md.
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351 UNSPEC_UHADD ; Used in aarch64-simd.md.
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352 UNSPEC_SRHADD ; Used in aarch64-simd.md.
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353 UNSPEC_URHADD ; Used in aarch64-simd.md.
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354 UNSPEC_SHSUB ; Used in aarch64-simd.md.
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355 UNSPEC_UHSUB ; Used in aarch64-simd.md.
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356 UNSPEC_SRHSUB ; Used in aarch64-simd.md.
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357 UNSPEC_URHSUB ; Used in aarch64-simd.md.
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358 UNSPEC_ADDHN ; Used in aarch64-simd.md.
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359 UNSPEC_RADDHN ; Used in aarch64-simd.md.
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360 UNSPEC_SUBHN ; Used in aarch64-simd.md.
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361 UNSPEC_RSUBHN ; Used in aarch64-simd.md.
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362 UNSPEC_ADDHN2 ; Used in aarch64-simd.md.
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363 UNSPEC_RADDHN2 ; Used in aarch64-simd.md.
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364 UNSPEC_SUBHN2 ; Used in aarch64-simd.md.
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365 UNSPEC_RSUBHN2 ; Used in aarch64-simd.md.
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366 UNSPEC_SQDMULH ; Used in aarch64-simd.md.
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367 UNSPEC_SQRDMULH ; Used in aarch64-simd.md.
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368 UNSPEC_PMUL ; Used in aarch64-simd.md.
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369 UNSPEC_FMULX ; Used in aarch64-simd.md.
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370 UNSPEC_USQADD ; Used in aarch64-simd.md.
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371 UNSPEC_SUQADD ; Used in aarch64-simd.md.
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372 UNSPEC_SQXTUN ; Used in aarch64-simd.md.
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373 UNSPEC_SQXTN ; Used in aarch64-simd.md.
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374 UNSPEC_UQXTN ; Used in aarch64-simd.md.
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375 UNSPEC_SSRA ; Used in aarch64-simd.md.
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376 UNSPEC_USRA ; Used in aarch64-simd.md.
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377 UNSPEC_SRSRA ; Used in aarch64-simd.md.
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378 UNSPEC_URSRA ; Used in aarch64-simd.md.
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379 UNSPEC_SRSHR ; Used in aarch64-simd.md.
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380 UNSPEC_URSHR ; Used in aarch64-simd.md.
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381 UNSPEC_SQSHLU ; Used in aarch64-simd.md.
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382 UNSPEC_SQSHL ; Used in aarch64-simd.md.
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383 UNSPEC_UQSHL ; Used in aarch64-simd.md.
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384 UNSPEC_SQSHRUN ; Used in aarch64-simd.md.
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385 UNSPEC_SQRSHRUN ; Used in aarch64-simd.md.
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386 UNSPEC_SQSHRN ; Used in aarch64-simd.md.
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387 UNSPEC_UQSHRN ; Used in aarch64-simd.md.
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388 UNSPEC_SQRSHRN ; Used in aarch64-simd.md.
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389 UNSPEC_UQRSHRN ; Used in aarch64-simd.md.
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390 UNSPEC_SSHL ; Used in aarch64-simd.md.
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391 UNSPEC_USHL ; Used in aarch64-simd.md.
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392 UNSPEC_SRSHL ; Used in aarch64-simd.md.
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393 UNSPEC_URSHL ; Used in aarch64-simd.md.
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394 UNSPEC_SQRSHL ; Used in aarch64-simd.md.
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395 UNSPEC_UQRSHL ; Used in aarch64-simd.md.
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396 UNSPEC_SSLI ; Used in aarch64-simd.md.
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397 UNSPEC_USLI ; Used in aarch64-simd.md.
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398 UNSPEC_SSRI ; Used in aarch64-simd.md.
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399 UNSPEC_USRI ; Used in aarch64-simd.md.
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400 UNSPEC_SSHLL ; Used in aarch64-simd.md.
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401 UNSPEC_USHLL ; Used in aarch64-simd.md.
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402 UNSPEC_ADDP ; Used in aarch64-simd.md.
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403 UNSPEC_TBL ; Used in vector permute patterns.
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404 UNSPEC_TBX ; Used in vector permute patterns.
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405 UNSPEC_CONCAT ; Used in vector permute patterns.
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131
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406
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407 ;; The following permute unspecs are generated directly by
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408 ;; aarch64_expand_vec_perm_const, so any changes to the underlying
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409 ;; instructions would need a corresponding change there.
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111
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410 UNSPEC_ZIP1 ; Used in vector permute patterns.
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411 UNSPEC_ZIP2 ; Used in vector permute patterns.
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412 UNSPEC_UZP1 ; Used in vector permute patterns.
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413 UNSPEC_UZP2 ; Used in vector permute patterns.
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414 UNSPEC_TRN1 ; Used in vector permute patterns.
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415 UNSPEC_TRN2 ; Used in vector permute patterns.
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131
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416 UNSPEC_EXT ; Used in vector permute patterns.
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111
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417 UNSPEC_REV64 ; Used in vector reverse patterns (permute).
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418 UNSPEC_REV32 ; Used in vector reverse patterns (permute).
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419 UNSPEC_REV16 ; Used in vector reverse patterns (permute).
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131
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420
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111
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421 UNSPEC_AESE ; Used in aarch64-simd.md.
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422 UNSPEC_AESD ; Used in aarch64-simd.md.
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423 UNSPEC_AESMC ; Used in aarch64-simd.md.
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424 UNSPEC_AESIMC ; Used in aarch64-simd.md.
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425 UNSPEC_SHA1C ; Used in aarch64-simd.md.
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426 UNSPEC_SHA1M ; Used in aarch64-simd.md.
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427 UNSPEC_SHA1P ; Used in aarch64-simd.md.
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428 UNSPEC_SHA1H ; Used in aarch64-simd.md.
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429 UNSPEC_SHA1SU0 ; Used in aarch64-simd.md.
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430 UNSPEC_SHA1SU1 ; Used in aarch64-simd.md.
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431 UNSPEC_SHA256H ; Used in aarch64-simd.md.
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432 UNSPEC_SHA256H2 ; Used in aarch64-simd.md.
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433 UNSPEC_SHA256SU0 ; Used in aarch64-simd.md.
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434 UNSPEC_SHA256SU1 ; Used in aarch64-simd.md.
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435 UNSPEC_PMULL ; Used in aarch64-simd.md.
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436 UNSPEC_PMULL2 ; Used in aarch64-simd.md.
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437 UNSPEC_REV_REGLIST ; Used in aarch64-simd.md.
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438 UNSPEC_VEC_SHR ; Used in aarch64-simd.md.
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439 UNSPEC_SQRDMLAH ; Used in aarch64-simd.md.
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440 UNSPEC_SQRDMLSH ; Used in aarch64-simd.md.
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441 UNSPEC_FMAXNM ; Used in aarch64-simd.md.
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442 UNSPEC_FMINNM ; Used in aarch64-simd.md.
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443 UNSPEC_SDOT ; Used in aarch64-simd.md.
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444 UNSPEC_UDOT ; Used in aarch64-simd.md.
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131
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445 UNSPEC_SM3SS1 ; Used in aarch64-simd.md.
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446 UNSPEC_SM3TT1A ; Used in aarch64-simd.md.
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447 UNSPEC_SM3TT1B ; Used in aarch64-simd.md.
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448 UNSPEC_SM3TT2A ; Used in aarch64-simd.md.
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449 UNSPEC_SM3TT2B ; Used in aarch64-simd.md.
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450 UNSPEC_SM3PARTW1 ; Used in aarch64-simd.md.
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451 UNSPEC_SM3PARTW2 ; Used in aarch64-simd.md.
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452 UNSPEC_SM4E ; Used in aarch64-simd.md.
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453 UNSPEC_SM4EKEY ; Used in aarch64-simd.md.
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454 UNSPEC_SHA512H ; Used in aarch64-simd.md.
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455 UNSPEC_SHA512H2 ; Used in aarch64-simd.md.
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456 UNSPEC_SHA512SU0 ; Used in aarch64-simd.md.
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457 UNSPEC_SHA512SU1 ; Used in aarch64-simd.md.
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458 UNSPEC_FMLAL ; Used in aarch64-simd.md.
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459 UNSPEC_FMLSL ; Used in aarch64-simd.md.
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460 UNSPEC_FMLAL2 ; Used in aarch64-simd.md.
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461 UNSPEC_FMLSL2 ; Used in aarch64-simd.md.
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462 UNSPEC_SEL ; Used in aarch64-sve.md.
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463 UNSPEC_ANDV ; Used in aarch64-sve.md.
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464 UNSPEC_IORV ; Used in aarch64-sve.md.
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465 UNSPEC_XORV ; Used in aarch64-sve.md.
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466 UNSPEC_ANDF ; Used in aarch64-sve.md.
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467 UNSPEC_IORF ; Used in aarch64-sve.md.
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468 UNSPEC_XORF ; Used in aarch64-sve.md.
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469 UNSPEC_SMUL_HIGHPART ; Used in aarch64-sve.md.
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470 UNSPEC_UMUL_HIGHPART ; Used in aarch64-sve.md.
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471 UNSPEC_COND_ADD ; Used in aarch64-sve.md.
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472 UNSPEC_COND_SUB ; Used in aarch64-sve.md.
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473 UNSPEC_COND_MUL ; Used in aarch64-sve.md.
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474 UNSPEC_COND_DIV ; Used in aarch64-sve.md.
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475 UNSPEC_COND_MAX ; Used in aarch64-sve.md.
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476 UNSPEC_COND_MIN ; Used in aarch64-sve.md.
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477 UNSPEC_COND_FMLA ; Used in aarch64-sve.md.
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478 UNSPEC_COND_FMLS ; Used in aarch64-sve.md.
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479 UNSPEC_COND_FNMLA ; Used in aarch64-sve.md.
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480 UNSPEC_COND_FNMLS ; Used in aarch64-sve.md.
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481 UNSPEC_COND_LT ; Used in aarch64-sve.md.
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482 UNSPEC_COND_LE ; Used in aarch64-sve.md.
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483 UNSPEC_COND_EQ ; Used in aarch64-sve.md.
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484 UNSPEC_COND_NE ; Used in aarch64-sve.md.
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485 UNSPEC_COND_GE ; Used in aarch64-sve.md.
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486 UNSPEC_COND_GT ; Used in aarch64-sve.md.
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487 UNSPEC_LASTB ; Used in aarch64-sve.md.
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111
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488 ])
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489
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490 ;; ------------------------------------------------------------------
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491 ;; Unspec enumerations for Atomics. They are here so that they can be
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492 ;; used in the int_iterators for atomic operations.
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493 ;; ------------------------------------------------------------------
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494
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495 (define_c_enum "unspecv"
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496 [
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497 UNSPECV_LX ; Represent a load-exclusive.
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498 UNSPECV_SX ; Represent a store-exclusive.
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499 UNSPECV_LDA ; Represent an atomic load or load-acquire.
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500 UNSPECV_STL ; Represent an atomic store or store-release.
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501 UNSPECV_ATOMIC_CMPSW ; Represent an atomic compare swap.
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502 UNSPECV_ATOMIC_EXCHG ; Represent an atomic exchange.
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503 UNSPECV_ATOMIC_CAS ; Represent an atomic CAS.
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504 UNSPECV_ATOMIC_SWP ; Represent an atomic SWP.
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505 UNSPECV_ATOMIC_OP ; Represent an atomic operation.
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506 UNSPECV_ATOMIC_LDOP ; Represent an atomic load-operation
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507 UNSPECV_ATOMIC_LDOP_OR ; Represent an atomic load-or
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508 UNSPECV_ATOMIC_LDOP_BIC ; Represent an atomic load-bic
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509 UNSPECV_ATOMIC_LDOP_XOR ; Represent an atomic load-xor
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510 UNSPECV_ATOMIC_LDOP_PLUS ; Represent an atomic load-add
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511 ])
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512
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513 ;; -------------------------------------------------------------------
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514 ;; Mode attributes
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515 ;; -------------------------------------------------------------------
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516
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517 ;; In GPI templates, a string like "%<w>0" will expand to "%w0" in the
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518 ;; 32-bit version and "%x0" in the 64-bit version.
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519 (define_mode_attr w [(QI "w") (HI "w") (SI "w") (DI "x") (SF "s") (DF "d")])
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520
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521 ;; The size of access, in bytes.
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522 (define_mode_attr ldst_sz [(SI "4") (DI "8")])
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523 ;; Likewise for load/store pair.
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|
524 (define_mode_attr ldpstp_sz [(SI "8") (DI "16")])
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525
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526 ;; For inequal width int to float conversion
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|
527 (define_mode_attr w1 [(HF "w") (SF "w") (DF "x")])
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528 (define_mode_attr w2 [(HF "x") (SF "x") (DF "w")])
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529
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131
|
530 ;; For width of fp registers in fcvt instruction
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|
|
531 (define_mode_attr fpw [(DI "s") (SI "d")])
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532
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|
111
|
533 (define_mode_attr short_mask [(HI "65535") (QI "255")])
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534
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535 ;; For constraints used in scalar immediate vector moves
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536 (define_mode_attr hq [(HI "h") (QI "q")])
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537
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538 ;; For doubling width of an integer mode
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539 (define_mode_attr DWI [(QI "HI") (HI "SI") (SI "DI") (DI "TI")])
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540
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|
131
|
541 (define_mode_attr fcvt_change_mode [(SI "df") (DI "sf")])
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542
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|
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543 (define_mode_attr FCVT_CHANGE_MODE [(SI "DF") (DI "SF")])
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|
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544
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111
|
545 ;; For scalar usage of vector/FP registers
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|
|
546 (define_mode_attr v [(QI "b") (HI "h") (SI "s") (DI "d")
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|
547 (HF "h") (SF "s") (DF "d")
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|
548 (V8QI "") (V16QI "")
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549 (V4HI "") (V8HI "")
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550 (V2SI "") (V4SI "")
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|
551 (V2DI "") (V2SF "")
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552 (V4SF "") (V4HF "")
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553 (V8HF "") (V2DF "")])
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554
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|
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555 ;; For scalar usage of vector/FP registers, narrowing
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556 (define_mode_attr vn2 [(QI "") (HI "b") (SI "h") (DI "s")
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557 (V8QI "") (V16QI "")
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558 (V4HI "") (V8HI "")
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559 (V2SI "") (V4SI "")
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|
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560 (V2DI "") (V2SF "")
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561 (V4SF "") (V2DF "")])
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|
562
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|
563 ;; For scalar usage of vector/FP registers, widening
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564 (define_mode_attr vw2 [(DI "") (QI "h") (HI "s") (SI "d")
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565 (V8QI "") (V16QI "")
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566 (V4HI "") (V8HI "")
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567 (V2SI "") (V4SI "")
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568 (V2DI "") (V2SF "")
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569 (V4SF "") (V2DF "")])
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570
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|
|
571 ;; Register Type Name and Vector Arrangement Specifier for when
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|
|
572 ;; we are doing scalar for DI and SIMD for SI (ignoring all but
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573 ;; lane 0).
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|
574 (define_mode_attr rtn [(DI "d") (SI "")])
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575 (define_mode_attr vas [(DI "") (SI ".2s")])
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576
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|
131
|
577 ;; Map a vector to the number of units in it, if the size of the mode
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|
|
578 ;; is constant.
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|
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579 (define_mode_attr nunits [(V8QI "8") (V16QI "16")
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|
580 (V4HI "4") (V8HI "8")
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|
|
581 (V2SI "2") (V4SI "4")
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582 (V2DI "2")
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|
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583 (V4HF "4") (V8HF "8")
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|
|
584 (V2SF "2") (V4SF "4")
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|
585 (V1DF "1") (V2DF "2")
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|
586 (DI "1") (DF "1")])
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|
|
587
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|
|
588 ;; Map a mode to the number of bits in it, if the size of the mode
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|
|
589 ;; is constant.
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|
590 (define_mode_attr bitsize [(V8QI "64") (V16QI "128")
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|
|
591 (V4HI "64") (V8HI "128")
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|
|
592 (V2SI "64") (V4SI "128")
|
|
|
593 (V2DI "128")])
|
|
|
594
|
|
|
595 ;; Map a floating point or integer mode to the appropriate register name prefix
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|
|
596 (define_mode_attr s [(HF "h") (SF "s") (DF "d") (SI "s") (DI "d")])
|
|
111
|
597
|
|
|
598 ;; Give the length suffix letter for a sign- or zero-extension.
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|
599 (define_mode_attr size [(QI "b") (HI "h") (SI "w")])
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|
|
600
|
|
|
601 ;; Give the number of bits in the mode
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|
|
602 (define_mode_attr sizen [(QI "8") (HI "16") (SI "32") (DI "64")])
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|
603
|
|
|
604 ;; Give the ordinal of the MSB in the mode
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|
|
605 (define_mode_attr sizem1 [(QI "#7") (HI "#15") (SI "#31") (DI "#63")])
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|
|
606
|
|
|
607 ;; Attribute to describe constants acceptable in logical operations
|
|
|
608 (define_mode_attr lconst [(SI "K") (DI "L")])
|
|
|
609
|
|
|
610 ;; Attribute to describe constants acceptable in logical and operations
|
|
|
611 (define_mode_attr lconst2 [(SI "UsO") (DI "UsP")])
|
|
|
612
|
|
|
613 ;; Map a mode to a specific constraint character.
|
|
|
614 (define_mode_attr cmode [(QI "q") (HI "h") (SI "s") (DI "d")])
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|
|
615
|
|
131
|
616 ;; Map modes to Usg and Usj constraints for SISD right shifts
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|
|
617 (define_mode_attr cmode_simd [(SI "g") (DI "j")])
|
|
|
618
|
|
111
|
619 (define_mode_attr Vtype [(V8QI "8b") (V16QI "16b")
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|
|
620 (V4HI "4h") (V8HI "8h")
|
|
|
621 (V2SI "2s") (V4SI "4s")
|
|
|
622 (DI "1d") (DF "1d")
|
|
|
623 (V2DI "2d") (V2SF "2s")
|
|
|
624 (V4SF "4s") (V2DF "2d")
|
|
|
625 (V4HF "4h") (V8HF "8h")])
|
|
|
626
|
|
|
627 (define_mode_attr Vrevsuff [(V4HI "16") (V8HI "16") (V2SI "32")
|
|
|
628 (V4SI "32") (V2DI "64")])
|
|
|
629
|
|
|
630 (define_mode_attr Vmtype [(V8QI ".8b") (V16QI ".16b")
|
|
|
631 (V4HI ".4h") (V8HI ".8h")
|
|
|
632 (V2SI ".2s") (V4SI ".4s")
|
|
|
633 (V2DI ".2d") (V4HF ".4h")
|
|
|
634 (V8HF ".8h") (V2SF ".2s")
|
|
|
635 (V4SF ".4s") (V2DF ".2d")
|
|
|
636 (DI "") (SI "")
|
|
|
637 (HI "") (QI "")
|
|
|
638 (TI "") (HF "")
|
|
|
639 (SF "") (DF "")])
|
|
|
640
|
|
|
641 ;; Register suffix narrowed modes for VQN.
|
|
|
642 (define_mode_attr Vmntype [(V8HI ".8b") (V4SI ".4h")
|
|
|
643 (V2DI ".2s")
|
|
|
644 (DI "") (SI "")
|
|
|
645 (HI "")])
|
|
|
646
|
|
|
647 ;; Mode-to-individual element type mapping.
|
|
131
|
648 (define_mode_attr Vetype [(V8QI "b") (V16QI "b") (VNx16QI "b") (VNx16BI "b")
|
|
|
649 (V4HI "h") (V8HI "h") (VNx8HI "h") (VNx8BI "h")
|
|
|
650 (V2SI "s") (V4SI "s") (VNx4SI "s") (VNx4BI "s")
|
|
|
651 (V2DI "d") (VNx2DI "d") (VNx2BI "d")
|
|
|
652 (V4HF "h") (V8HF "h") (VNx8HF "h")
|
|
|
653 (V2SF "s") (V4SF "s") (VNx4SF "s")
|
|
|
654 (V2DF "d") (VNx2DF "d")
|
|
111
|
655 (HF "h")
|
|
|
656 (SF "s") (DF "d")
|
|
|
657 (QI "b") (HI "h")
|
|
|
658 (SI "s") (DI "d")])
|
|
|
659
|
|
131
|
660 ;; Equivalent of "size" for a vector element.
|
|
|
661 (define_mode_attr Vesize [(VNx16QI "b")
|
|
|
662 (VNx8HI "h") (VNx8HF "h")
|
|
|
663 (VNx4SI "w") (VNx4SF "w")
|
|
|
664 (VNx2DI "d") (VNx2DF "d")
|
|
|
665 (VNx32QI "b") (VNx48QI "b") (VNx64QI "b")
|
|
|
666 (VNx16HI "h") (VNx24HI "h") (VNx32HI "h")
|
|
|
667 (VNx16HF "h") (VNx24HF "h") (VNx32HF "h")
|
|
|
668 (VNx8SI "w") (VNx12SI "w") (VNx16SI "w")
|
|
|
669 (VNx8SF "w") (VNx12SF "w") (VNx16SF "w")
|
|
|
670 (VNx4DI "d") (VNx6DI "d") (VNx8DI "d")
|
|
|
671 (VNx4DF "d") (VNx6DF "d") (VNx8DF "d")])
|
|
|
672
|
|
111
|
673 ;; Vetype is used everywhere in scheduling type and assembly output,
|
|
|
674 ;; sometimes they are not the same, for example HF modes on some
|
|
|
675 ;; instructions. stype is defined to represent scheduling type
|
|
|
676 ;; more accurately.
|
|
|
677 (define_mode_attr stype [(V8QI "b") (V16QI "b") (V4HI "s") (V8HI "s")
|
|
|
678 (V2SI "s") (V4SI "s") (V2DI "d") (V4HF "s")
|
|
|
679 (V8HF "s") (V2SF "s") (V4SF "s") (V2DF "d")
|
|
|
680 (HF "s") (SF "s") (DF "d") (QI "b") (HI "s")
|
|
|
681 (SI "s") (DI "d")])
|
|
|
682
|
|
|
683 ;; Mode-to-bitwise operation type mapping.
|
|
|
684 (define_mode_attr Vbtype [(V8QI "8b") (V16QI "16b")
|
|
|
685 (V4HI "8b") (V8HI "16b")
|
|
|
686 (V2SI "8b") (V4SI "16b")
|
|
|
687 (V2DI "16b") (V4HF "8b")
|
|
|
688 (V8HF "16b") (V2SF "8b")
|
|
|
689 (V4SF "16b") (V2DF "16b")
|
|
|
690 (DI "8b") (DF "8b")
|
|
|
691 (SI "8b")])
|
|
|
692
|
|
|
693 ;; Define element mode for each vector mode.
|
|
131
|
694 (define_mode_attr VEL [(V8QI "QI") (V16QI "QI") (VNx16QI "QI")
|
|
|
695 (V4HI "HI") (V8HI "HI") (VNx8HI "HI")
|
|
|
696 (V2SI "SI") (V4SI "SI") (VNx4SI "SI")
|
|
|
697 (DI "DI") (V2DI "DI") (VNx2DI "DI")
|
|
|
698 (V4HF "HF") (V8HF "HF") (VNx8HF "HF")
|
|
|
699 (V2SF "SF") (V4SF "SF") (VNx4SF "SF")
|
|
|
700 (DF "DF") (V2DF "DF") (VNx2DF "DF")
|
|
|
701 (SI "SI") (HI "HI")
|
|
111
|
702 (QI "QI")])
|
|
|
703
|
|
|
704 ;; Define element mode for each vector mode (lower case).
|
|
131
|
705 (define_mode_attr Vel [(V8QI "qi") (V16QI "qi") (VNx16QI "qi")
|
|
|
706 (V4HI "hi") (V8HI "hi") (VNx8HI "hi")
|
|
|
707 (V2SI "si") (V4SI "si") (VNx4SI "si")
|
|
|
708 (DI "di") (V2DI "di") (VNx2DI "di")
|
|
|
709 (V4HF "hf") (V8HF "hf") (VNx8HF "hf")
|
|
|
710 (V2SF "sf") (V4SF "sf") (VNx4SF "sf")
|
|
|
711 (V2DF "df") (DF "df") (VNx2DF "df")
|
|
111
|
712 (SI "si") (HI "hi")
|
|
|
713 (QI "qi")])
|
|
|
714
|
|
131
|
715 ;; Element mode with floating-point values replaced by like-sized integers.
|
|
|
716 (define_mode_attr VEL_INT [(VNx16QI "QI")
|
|
|
717 (VNx8HI "HI") (VNx8HF "HI")
|
|
|
718 (VNx4SI "SI") (VNx4SF "SI")
|
|
|
719 (VNx2DI "DI") (VNx2DF "DI")])
|
|
|
720
|
|
|
721 ;; Gives the mode of the 128-bit lowpart of an SVE vector.
|
|
|
722 (define_mode_attr V128 [(VNx16QI "V16QI")
|
|
|
723 (VNx8HI "V8HI") (VNx8HF "V8HF")
|
|
|
724 (VNx4SI "V4SI") (VNx4SF "V4SF")
|
|
|
725 (VNx2DI "V2DI") (VNx2DF "V2DF")])
|
|
|
726
|
|
|
727 ;; ...and again in lower case.
|
|
|
728 (define_mode_attr v128 [(VNx16QI "v16qi")
|
|
|
729 (VNx8HI "v8hi") (VNx8HF "v8hf")
|
|
|
730 (VNx4SI "v4si") (VNx4SF "v4sf")
|
|
|
731 (VNx2DI "v2di") (VNx2DF "v2df")])
|
|
|
732
|
|
111
|
733 ;; 64-bit container modes the inner or scalar source mode.
|
|
|
734 (define_mode_attr VCOND [(HI "V4HI") (SI "V2SI")
|
|
|
735 (V4HI "V4HI") (V8HI "V4HI")
|
|
|
736 (V2SI "V2SI") (V4SI "V2SI")
|
|
|
737 (DI "DI") (V2DI "DI")
|
|
|
738 (V2SF "V2SF") (V4SF "V2SF")
|
|
|
739 (V2DF "DF")])
|
|
|
740
|
|
|
741 ;; 128-bit container modes the inner or scalar source mode.
|
|
|
742 (define_mode_attr VCONQ [(V8QI "V16QI") (V16QI "V16QI")
|
|
|
743 (V4HI "V8HI") (V8HI "V8HI")
|
|
|
744 (V2SI "V4SI") (V4SI "V4SI")
|
|
|
745 (DI "V2DI") (V2DI "V2DI")
|
|
|
746 (V4HF "V8HF") (V8HF "V8HF")
|
|
|
747 (V2SF "V2SF") (V4SF "V4SF")
|
|
|
748 (V2DF "V2DF") (SI "V4SI")
|
|
|
749 (HI "V8HI") (QI "V16QI")])
|
|
|
750
|
|
|
751 ;; Half modes of all vector modes.
|
|
|
752 (define_mode_attr VHALF [(V8QI "V4QI") (V16QI "V8QI")
|
|
|
753 (V4HI "V2HI") (V8HI "V4HI")
|
|
|
754 (V2SI "SI") (V4SI "V2SI")
|
|
|
755 (V2DI "DI") (V2SF "SF")
|
|
|
756 (V4SF "V2SF") (V4HF "V2HF")
|
|
|
757 (V8HF "V4HF") (V2DF "DF")])
|
|
|
758
|
|
|
759 ;; Half modes of all vector modes, in lower-case.
|
|
|
760 (define_mode_attr Vhalf [(V8QI "v4qi") (V16QI "v8qi")
|
|
|
761 (V4HI "v2hi") (V8HI "v4hi")
|
|
|
762 (V2SI "si") (V4SI "v2si")
|
|
|
763 (V2DI "di") (V2SF "sf")
|
|
|
764 (V4SF "v2sf") (V2DF "df")])
|
|
|
765
|
|
|
766 ;; Double modes of vector modes.
|
|
|
767 (define_mode_attr VDBL [(V8QI "V16QI") (V4HI "V8HI")
|
|
|
768 (V4HF "V8HF")
|
|
|
769 (V2SI "V4SI") (V2SF "V4SF")
|
|
|
770 (SI "V2SI") (DI "V2DI")
|
|
|
771 (DF "V2DF")])
|
|
|
772
|
|
|
773 ;; Register suffix for double-length mode.
|
|
|
774 (define_mode_attr Vdtype [(V4HF "8h") (V2SF "4s")])
|
|
|
775
|
|
|
776 ;; Double modes of vector modes (lower case).
|
|
|
777 (define_mode_attr Vdbl [(V8QI "v16qi") (V4HI "v8hi")
|
|
|
778 (V4HF "v8hf")
|
|
|
779 (V2SI "v4si") (V2SF "v4sf")
|
|
|
780 (SI "v2si") (DI "v2di")
|
|
|
781 (DF "v2df")])
|
|
|
782
|
|
|
783 ;; Modes with double-width elements.
|
|
|
784 (define_mode_attr VDBLW [(V8QI "V4HI") (V16QI "V8HI")
|
|
|
785 (V4HI "V2SI") (V8HI "V4SI")
|
|
|
786 (V2SI "DI") (V4SI "V2DI")])
|
|
|
787
|
|
|
788 ;; Narrowed modes for VDN.
|
|
|
789 (define_mode_attr VNARROWD [(V4HI "V8QI") (V2SI "V4HI")
|
|
|
790 (DI "V2SI")])
|
|
|
791
|
|
|
792 ;; Narrowed double-modes for VQN (Used for XTN).
|
|
|
793 (define_mode_attr VNARROWQ [(V8HI "V8QI") (V4SI "V4HI")
|
|
|
794 (V2DI "V2SI")
|
|
|
795 (DI "SI") (SI "HI")
|
|
|
796 (HI "QI")])
|
|
|
797
|
|
|
798 ;; Narrowed quad-modes for VQN (Used for XTN2).
|
|
|
799 (define_mode_attr VNARROWQ2 [(V8HI "V16QI") (V4SI "V8HI")
|
|
|
800 (V2DI "V4SI")])
|
|
|
801
|
|
|
802 ;; Register suffix narrowed modes for VQN.
|
|
|
803 (define_mode_attr Vntype [(V8HI "8b") (V4SI "4h")
|
|
|
804 (V2DI "2s")])
|
|
|
805
|
|
|
806 ;; Register suffix narrowed modes for VQN.
|
|
|
807 (define_mode_attr V2ntype [(V8HI "16b") (V4SI "8h")
|
|
|
808 (V2DI "4s")])
|
|
|
809
|
|
|
810 ;; Widened modes of vector modes.
|
|
131
|
811 (define_mode_attr VWIDE [(V8QI "V8HI") (V4HI "V4SI")
|
|
|
812 (V2SI "V2DI") (V16QI "V8HI")
|
|
|
813 (V8HI "V4SI") (V4SI "V2DI")
|
|
|
814 (HI "SI") (SI "DI")
|
|
|
815 (V8HF "V4SF") (V4SF "V2DF")
|
|
|
816 (V4HF "V4SF") (V2SF "V2DF")
|
|
|
817 (VNx8HF "VNx4SF") (VNx4SF "VNx2DF")
|
|
|
818 (VNx16QI "VNx8HI") (VNx8HI "VNx4SI")
|
|
|
819 (VNx4SI "VNx2DI")
|
|
|
820 (VNx16BI "VNx8BI") (VNx8BI "VNx4BI")
|
|
|
821 (VNx4BI "VNx2BI")])
|
|
|
822
|
|
|
823 ;; Predicate mode associated with VWIDE.
|
|
|
824 (define_mode_attr VWIDE_PRED [(VNx8HF "VNx4BI") (VNx4SF "VNx2BI")])
|
|
111
|
825
|
|
|
826 ;; Widened modes of vector modes, lowercase
|
|
131
|
827 (define_mode_attr Vwide [(V2SF "v2df") (V4HF "v4sf")
|
|
|
828 (VNx16QI "vnx8hi") (VNx8HI "vnx4si")
|
|
|
829 (VNx4SI "vnx2di")
|
|
|
830 (VNx8HF "vnx4sf") (VNx4SF "vnx2df")
|
|
|
831 (VNx16BI "vnx8bi") (VNx8BI "vnx4bi")
|
|
|
832 (VNx4BI "vnx2bi")])
|
|
111
|
833
|
|
|
834 ;; Widened mode register suffixes for VD_BHSI/VQW/VQ_HSF.
|
|
|
835 (define_mode_attr Vwtype [(V8QI "8h") (V4HI "4s")
|
|
|
836 (V2SI "2d") (V16QI "8h")
|
|
|
837 (V8HI "4s") (V4SI "2d")
|
|
|
838 (V8HF "4s") (V4SF "2d")])
|
|
|
839
|
|
131
|
840 ;; SVE vector after widening
|
|
|
841 (define_mode_attr Vewtype [(VNx16QI "h")
|
|
|
842 (VNx8HI "s") (VNx8HF "s")
|
|
|
843 (VNx4SI "d") (VNx4SF "d")])
|
|
|
844
|
|
111
|
845 ;; Widened mode register suffixes for VDW/VQW.
|
|
|
846 (define_mode_attr Vmwtype [(V8QI ".8h") (V4HI ".4s")
|
|
|
847 (V2SI ".2d") (V16QI ".8h")
|
|
|
848 (V8HI ".4s") (V4SI ".2d")
|
|
|
849 (V4HF ".4s") (V2SF ".2d")
|
|
|
850 (SI "") (HI "")])
|
|
|
851
|
|
|
852 ;; Lower part register suffixes for VQW/VQ_HSF.
|
|
|
853 (define_mode_attr Vhalftype [(V16QI "8b") (V8HI "4h")
|
|
|
854 (V4SI "2s") (V8HF "4h")
|
|
|
855 (V4SF "2s")])
|
|
|
856
|
|
|
857 ;; Define corresponding core/FP element mode for each vector mode.
|
|
131
|
858 (define_mode_attr vw [(V8QI "w") (V16QI "w") (VNx16QI "w")
|
|
|
859 (V4HI "w") (V8HI "w") (VNx8HI "w")
|
|
|
860 (V2SI "w") (V4SI "w") (VNx4SI "w")
|
|
|
861 (DI "x") (V2DI "x") (VNx2DI "x")
|
|
|
862 (VNx8HF "h")
|
|
|
863 (V2SF "s") (V4SF "s") (VNx4SF "s")
|
|
|
864 (V2DF "d") (VNx2DF "d")])
|
|
111
|
865
|
|
|
866 ;; Corresponding core element mode for each vector mode. This is a
|
|
|
867 ;; variation on <vw> mapping FP modes to GP regs.
|
|
131
|
868 (define_mode_attr vwcore [(V8QI "w") (V16QI "w") (VNx16QI "w")
|
|
|
869 (V4HI "w") (V8HI "w") (VNx8HI "w")
|
|
|
870 (V2SI "w") (V4SI "w") (VNx4SI "w")
|
|
|
871 (DI "x") (V2DI "x") (VNx2DI "x")
|
|
|
872 (V4HF "w") (V8HF "w") (VNx8HF "w")
|
|
|
873 (V2SF "w") (V4SF "w") (VNx4SF "w")
|
|
|
874 (V2DF "x") (VNx2DF "x")])
|
|
111
|
875
|
|
|
876 ;; Double vector types for ALLX.
|
|
|
877 (define_mode_attr Vallxd [(QI "8b") (HI "4h") (SI "2s")])
|
|
|
878
|
|
|
879 ;; Mode with floating-point values replaced by like-sized integers.
|
|
|
880 (define_mode_attr V_INT_EQUIV [(V8QI "V8QI") (V16QI "V16QI")
|
|
|
881 (V4HI "V4HI") (V8HI "V8HI")
|
|
|
882 (V2SI "V2SI") (V4SI "V4SI")
|
|
|
883 (DI "DI") (V2DI "V2DI")
|
|
|
884 (V4HF "V4HI") (V8HF "V8HI")
|
|
|
885 (V2SF "V2SI") (V4SF "V4SI")
|
|
131
|
886 (DF "DI") (V2DF "V2DI")
|
|
|
887 (SF "SI") (SI "SI")
|
|
|
888 (HF "HI")
|
|
|
889 (VNx16QI "VNx16QI")
|
|
|
890 (VNx8HI "VNx8HI") (VNx8HF "VNx8HI")
|
|
|
891 (VNx4SI "VNx4SI") (VNx4SF "VNx4SI")
|
|
|
892 (VNx2DI "VNx2DI") (VNx2DF "VNx2DI")
|
|
|
893 ])
|
|
111
|
894
|
|
|
895 ;; Lower case mode with floating-point values replaced by like-sized integers.
|
|
|
896 (define_mode_attr v_int_equiv [(V8QI "v8qi") (V16QI "v16qi")
|
|
|
897 (V4HI "v4hi") (V8HI "v8hi")
|
|
|
898 (V2SI "v2si") (V4SI "v4si")
|
|
|
899 (DI "di") (V2DI "v2di")
|
|
|
900 (V4HF "v4hi") (V8HF "v8hi")
|
|
|
901 (V2SF "v2si") (V4SF "v4si")
|
|
131
|
902 (DF "di") (V2DF "v2di")
|
|
|
903 (SF "si")
|
|
|
904 (VNx16QI "vnx16qi")
|
|
|
905 (VNx8HI "vnx8hi") (VNx8HF "vnx8hi")
|
|
|
906 (VNx4SI "vnx4si") (VNx4SF "vnx4si")
|
|
|
907 (VNx2DI "vnx2di") (VNx2DF "vnx2di")
|
|
|
908 ])
|
|
|
909
|
|
|
910 ;; Floating-point equivalent of selected modes.
|
|
|
911 (define_mode_attr V_FP_EQUIV [(VNx4SI "VNx4SF") (VNx4SF "VNx4SF")
|
|
|
912 (VNx2DI "VNx2DF") (VNx2DF "VNx2DF")])
|
|
|
913 (define_mode_attr v_fp_equiv [(VNx4SI "vnx4sf") (VNx4SF "vnx4sf")
|
|
|
914 (VNx2DI "vnx2df") (VNx2DF "vnx2df")])
|
|
111
|
915
|
|
|
916 ;; Mode for vector conditional operations where the comparison has
|
|
|
917 ;; different type from the lhs.
|
|
|
918 (define_mode_attr V_cmp_mixed [(V2SI "V2SF") (V4SI "V4SF")
|
|
|
919 (V2DI "V2DF") (V2SF "V2SI")
|
|
|
920 (V4SF "V4SI") (V2DF "V2DI")])
|
|
|
921
|
|
|
922 (define_mode_attr v_cmp_mixed [(V2SI "v2sf") (V4SI "v4sf")
|
|
|
923 (V2DI "v2df") (V2SF "v2si")
|
|
|
924 (V4SF "v4si") (V2DF "v2di")])
|
|
|
925
|
|
|
926 ;; Lower case element modes (as used in shift immediate patterns).
|
|
|
927 (define_mode_attr ve_mode [(V8QI "qi") (V16QI "qi")
|
|
|
928 (V4HI "hi") (V8HI "hi")
|
|
|
929 (V2SI "si") (V4SI "si")
|
|
|
930 (DI "di") (V2DI "di")
|
|
|
931 (QI "qi") (HI "hi")
|
|
|
932 (SI "si")])
|
|
|
933
|
|
|
934 ;; Vm for lane instructions is restricted to FP_LO_REGS.
|
|
|
935 (define_mode_attr vwx [(V4HI "x") (V8HI "x") (HI "x")
|
|
|
936 (V2SI "w") (V4SI "w") (SI "w")])
|
|
|
937
|
|
|
938 (define_mode_attr Vendreg [(OI "T") (CI "U") (XI "V")])
|
|
|
939
|
|
|
940 ;; This is both the number of Q-Registers needed to hold the corresponding
|
|
|
941 ;; opaque large integer mode, and the number of elements touched by the
|
|
|
942 ;; ld..._lane and st..._lane operations.
|
|
|
943 (define_mode_attr nregs [(OI "2") (CI "3") (XI "4")])
|
|
|
944
|
|
|
945 ;; Mode for atomic operation suffixes
|
|
|
946 (define_mode_attr atomic_sfx
|
|
|
947 [(QI "b") (HI "h") (SI "") (DI "")])
|
|
|
948
|
|
|
949 (define_mode_attr fcvt_target [(V2DF "v2di") (V4SF "v4si") (V2SF "v2si")
|
|
|
950 (V2DI "v2df") (V4SI "v4sf") (V2SI "v2sf")
|
|
|
951 (SF "si") (DF "di") (SI "sf") (DI "df")
|
|
|
952 (V4HF "v4hi") (V8HF "v8hi") (V4HI "v4hf")
|
|
|
953 (V8HI "v8hf") (HF "hi") (HI "hf")])
|
|
|
954 (define_mode_attr FCVT_TARGET [(V2DF "V2DI") (V4SF "V4SI") (V2SF "V2SI")
|
|
|
955 (V2DI "V2DF") (V4SI "V4SF") (V2SI "V2SF")
|
|
|
956 (SF "SI") (DF "DI") (SI "SF") (DI "DF")
|
|
|
957 (V4HF "V4HI") (V8HF "V8HI") (V4HI "V4HF")
|
|
|
958 (V8HI "V8HF") (HF "HI") (HI "HF")])
|
|
|
959
|
|
|
960
|
|
|
961 ;; for the inequal width integer to fp conversions
|
|
|
962 (define_mode_attr fcvt_iesize [(HF "di") (SF "di") (DF "si")])
|
|
|
963 (define_mode_attr FCVT_IESIZE [(HF "DI") (SF "DI") (DF "SI")])
|
|
|
964
|
|
|
965 (define_mode_attr VSWAP_WIDTH [(V8QI "V16QI") (V16QI "V8QI")
|
|
|
966 (V4HI "V8HI") (V8HI "V4HI")
|
|
|
967 (V2SI "V4SI") (V4SI "V2SI")
|
|
|
968 (DI "V2DI") (V2DI "DI")
|
|
|
969 (V2SF "V4SF") (V4SF "V2SF")
|
|
|
970 (V4HF "V8HF") (V8HF "V4HF")
|
|
|
971 (DF "V2DF") (V2DF "DF")])
|
|
|
972
|
|
|
973 (define_mode_attr vswap_width_name [(V8QI "to_128") (V16QI "to_64")
|
|
|
974 (V4HI "to_128") (V8HI "to_64")
|
|
|
975 (V2SI "to_128") (V4SI "to_64")
|
|
|
976 (DI "to_128") (V2DI "to_64")
|
|
|
977 (V4HF "to_128") (V8HF "to_64")
|
|
|
978 (V2SF "to_128") (V4SF "to_64")
|
|
|
979 (DF "to_128") (V2DF "to_64")])
|
|
|
980
|
|
|
981 ;; For certain vector-by-element multiplication instructions we must
|
|
|
982 ;; constrain the 16-bit cases to use only V0-V15. This is covered by
|
|
|
983 ;; the 'x' constraint. All other modes may use the 'w' constraint.
|
|
|
984 (define_mode_attr h_con [(V2SI "w") (V4SI "w")
|
|
|
985 (V4HI "x") (V8HI "x")
|
|
|
986 (V4HF "x") (V8HF "x")
|
|
|
987 (V2SF "w") (V4SF "w")
|
|
|
988 (V2DF "w") (DF "w")])
|
|
|
989
|
|
|
990 ;; Defined to 'f' for types whose element type is a float type.
|
|
|
991 (define_mode_attr f [(V8QI "") (V16QI "")
|
|
|
992 (V4HI "") (V8HI "")
|
|
|
993 (V2SI "") (V4SI "")
|
|
|
994 (DI "") (V2DI "")
|
|
|
995 (V4HF "f") (V8HF "f")
|
|
|
996 (V2SF "f") (V4SF "f")
|
|
|
997 (V2DF "f") (DF "f")])
|
|
|
998
|
|
|
999 ;; Defined to '_fp' for types whose element type is a float type.
|
|
|
1000 (define_mode_attr fp [(V8QI "") (V16QI "")
|
|
|
1001 (V4HI "") (V8HI "")
|
|
|
1002 (V2SI "") (V4SI "")
|
|
|
1003 (DI "") (V2DI "")
|
|
|
1004 (V4HF "_fp") (V8HF "_fp")
|
|
|
1005 (V2SF "_fp") (V4SF "_fp")
|
|
|
1006 (V2DF "_fp") (DF "_fp")
|
|
|
1007 (SF "_fp")])
|
|
|
1008
|
|
|
1009 ;; Defined to '_q' for 128-bit types.
|
|
|
1010 (define_mode_attr q [(V8QI "") (V16QI "_q")
|
|
|
1011 (V4HI "") (V8HI "_q")
|
|
|
1012 (V2SI "") (V4SI "_q")
|
|
|
1013 (DI "") (V2DI "_q")
|
|
|
1014 (V4HF "") (V8HF "_q")
|
|
|
1015 (V2SF "") (V4SF "_q")
|
|
|
1016 (V2DF "_q")
|
|
|
1017 (QI "") (HI "") (SI "") (DI "") (HF "") (SF "") (DF "")])
|
|
|
1018
|
|
|
1019 (define_mode_attr vp [(V8QI "v") (V16QI "v")
|
|
|
1020 (V4HI "v") (V8HI "v")
|
|
|
1021 (V2SI "p") (V4SI "v")
|
|
|
1022 (V2DI "p") (V2DF "p")
|
|
|
1023 (V2SF "p") (V4SF "v")
|
|
|
1024 (V4HF "v") (V8HF "v")])
|
|
|
1025
|
|
|
1026 (define_mode_attr vsi2qi [(V2SI "v8qi") (V4SI "v16qi")])
|
|
|
1027 (define_mode_attr VSI2QI [(V2SI "V8QI") (V4SI "V16QI")])
|
|
|
1028
|
|
|
1029
|
|
|
1030 ;; Register suffix for DOTPROD input types from the return type.
|
|
|
1031 (define_mode_attr Vdottype [(V2SI "8b") (V4SI "16b")])
|
|
|
1032
|
|
|
1033 ;; Sum of lengths of instructions needed to move vector registers of a mode.
|
|
|
1034 (define_mode_attr insn_count [(OI "8") (CI "12") (XI "16")])
|
|
|
1035
|
|
|
1036 ;; -fpic small model GOT reloc modifers: gotpage_lo15/lo14 for ILP64/32.
|
|
|
1037 ;; No need of iterator for -fPIC as it use got_lo12 for both modes.
|
|
|
1038 (define_mode_attr got_modifier [(SI "gotpage_lo14") (DI "gotpage_lo15")])
|
|
|
1039
|
|
131
|
1040 ;; Width of 2nd and 3rd arguments to fp16 vector multiply add/sub
|
|
|
1041 (define_mode_attr VFMLA_W [(V2SF "V4HF") (V4SF "V8HF")])
|
|
|
1042
|
|
|
1043 (define_mode_attr VFMLA_SEL_W [(V2SF "V2HF") (V4SF "V4HF")])
|
|
|
1044
|
|
|
1045 (define_mode_attr f16quad [(V2SF "") (V4SF "q")])
|
|
|
1046
|
|
|
1047 (define_code_attr f16mac [(plus "a") (minus "s")])
|
|
|
1048
|
|
|
1049 ;; The number of subvectors in an SVE_STRUCT.
|
|
|
1050 (define_mode_attr vector_count [(VNx32QI "2") (VNx16HI "2")
|
|
|
1051 (VNx8SI "2") (VNx4DI "2")
|
|
|
1052 (VNx16HF "2") (VNx8SF "2") (VNx4DF "2")
|
|
|
1053 (VNx48QI "3") (VNx24HI "3")
|
|
|
1054 (VNx12SI "3") (VNx6DI "3")
|
|
|
1055 (VNx24HF "3") (VNx12SF "3") (VNx6DF "3")
|
|
|
1056 (VNx64QI "4") (VNx32HI "4")
|
|
|
1057 (VNx16SI "4") (VNx8DI "4")
|
|
|
1058 (VNx32HF "4") (VNx16SF "4") (VNx8DF "4")])
|
|
|
1059
|
|
|
1060 ;; The number of instruction bytes needed for an SVE_STRUCT move. This is
|
|
|
1061 ;; equal to vector_count * 4.
|
|
|
1062 (define_mode_attr insn_length [(VNx32QI "8") (VNx16HI "8")
|
|
|
1063 (VNx8SI "8") (VNx4DI "8")
|
|
|
1064 (VNx16HF "8") (VNx8SF "8") (VNx4DF "8")
|
|
|
1065 (VNx48QI "12") (VNx24HI "12")
|
|
|
1066 (VNx12SI "12") (VNx6DI "12")
|
|
|
1067 (VNx24HF "12") (VNx12SF "12") (VNx6DF "12")
|
|
|
1068 (VNx64QI "16") (VNx32HI "16")
|
|
|
1069 (VNx16SI "16") (VNx8DI "16")
|
|
|
1070 (VNx32HF "16") (VNx16SF "16") (VNx8DF "16")])
|
|
|
1071
|
|
|
1072 ;; The type of a subvector in an SVE_STRUCT.
|
|
|
1073 (define_mode_attr VSINGLE [(VNx32QI "VNx16QI")
|
|
|
1074 (VNx16HI "VNx8HI") (VNx16HF "VNx8HF")
|
|
|
1075 (VNx8SI "VNx4SI") (VNx8SF "VNx4SF")
|
|
|
1076 (VNx4DI "VNx2DI") (VNx4DF "VNx2DF")
|
|
|
1077 (VNx48QI "VNx16QI")
|
|
|
1078 (VNx24HI "VNx8HI") (VNx24HF "VNx8HF")
|
|
|
1079 (VNx12SI "VNx4SI") (VNx12SF "VNx4SF")
|
|
|
1080 (VNx6DI "VNx2DI") (VNx6DF "VNx2DF")
|
|
|
1081 (VNx64QI "VNx16QI")
|
|
|
1082 (VNx32HI "VNx8HI") (VNx32HF "VNx8HF")
|
|
|
1083 (VNx16SI "VNx4SI") (VNx16SF "VNx4SF")
|
|
|
1084 (VNx8DI "VNx2DI") (VNx8DF "VNx2DF")])
|
|
|
1085
|
|
|
1086 ;; ...and again in lower case.
|
|
|
1087 (define_mode_attr vsingle [(VNx32QI "vnx16qi")
|
|
|
1088 (VNx16HI "vnx8hi") (VNx16HF "vnx8hf")
|
|
|
1089 (VNx8SI "vnx4si") (VNx8SF "vnx4sf")
|
|
|
1090 (VNx4DI "vnx2di") (VNx4DF "vnx2df")
|
|
|
1091 (VNx48QI "vnx16qi")
|
|
|
1092 (VNx24HI "vnx8hi") (VNx24HF "vnx8hf")
|
|
|
1093 (VNx12SI "vnx4si") (VNx12SF "vnx4sf")
|
|
|
1094 (VNx6DI "vnx2di") (VNx6DF "vnx2df")
|
|
|
1095 (VNx64QI "vnx16qi")
|
|
|
1096 (VNx32HI "vnx8hi") (VNx32HF "vnx8hf")
|
|
|
1097 (VNx16SI "vnx4si") (VNx16SF "vnx4sf")
|
|
|
1098 (VNx8DI "vnx2di") (VNx8DF "vnx2df")])
|
|
|
1099
|
|
|
1100 ;; The predicate mode associated with an SVE data mode. For structure modes
|
|
|
1101 ;; this is equivalent to the <VPRED> of the subvector mode.
|
|
|
1102 (define_mode_attr VPRED [(VNx16QI "VNx16BI")
|
|
|
1103 (VNx8HI "VNx8BI") (VNx8HF "VNx8BI")
|
|
|
1104 (VNx4SI "VNx4BI") (VNx4SF "VNx4BI")
|
|
|
1105 (VNx2DI "VNx2BI") (VNx2DF "VNx2BI")
|
|
|
1106 (VNx32QI "VNx16BI")
|
|
|
1107 (VNx16HI "VNx8BI") (VNx16HF "VNx8BI")
|
|
|
1108 (VNx8SI "VNx4BI") (VNx8SF "VNx4BI")
|
|
|
1109 (VNx4DI "VNx2BI") (VNx4DF "VNx2BI")
|
|
|
1110 (VNx48QI "VNx16BI")
|
|
|
1111 (VNx24HI "VNx8BI") (VNx24HF "VNx8BI")
|
|
|
1112 (VNx12SI "VNx4BI") (VNx12SF "VNx4BI")
|
|
|
1113 (VNx6DI "VNx2BI") (VNx6DF "VNx2BI")
|
|
|
1114 (VNx64QI "VNx16BI")
|
|
|
1115 (VNx32HI "VNx8BI") (VNx32HF "VNx8BI")
|
|
|
1116 (VNx16SI "VNx4BI") (VNx16SF "VNx4BI")
|
|
|
1117 (VNx8DI "VNx2BI") (VNx8DF "VNx2BI")])
|
|
|
1118
|
|
|
1119 ;; ...and again in lower case.
|
|
|
1120 (define_mode_attr vpred [(VNx16QI "vnx16bi")
|
|
|
1121 (VNx8HI "vnx8bi") (VNx8HF "vnx8bi")
|
|
|
1122 (VNx4SI "vnx4bi") (VNx4SF "vnx4bi")
|
|
|
1123 (VNx2DI "vnx2bi") (VNx2DF "vnx2bi")
|
|
|
1124 (VNx32QI "vnx16bi")
|
|
|
1125 (VNx16HI "vnx8bi") (VNx16HF "vnx8bi")
|
|
|
1126 (VNx8SI "vnx4bi") (VNx8SF "vnx4bi")
|
|
|
1127 (VNx4DI "vnx2bi") (VNx4DF "vnx2bi")
|
|
|
1128 (VNx48QI "vnx16bi")
|
|
|
1129 (VNx24HI "vnx8bi") (VNx24HF "vnx8bi")
|
|
|
1130 (VNx12SI "vnx4bi") (VNx12SF "vnx4bi")
|
|
|
1131 (VNx6DI "vnx2bi") (VNx6DF "vnx2bi")
|
|
|
1132 (VNx64QI "vnx16bi")
|
|
|
1133 (VNx32HI "vnx8bi") (VNx32HF "vnx4bi")
|
|
|
1134 (VNx16SI "vnx4bi") (VNx16SF "vnx4bi")
|
|
|
1135 (VNx8DI "vnx2bi") (VNx8DF "vnx2bi")])
|
|
|
1136
|
|
111
|
1137 ;; -------------------------------------------------------------------
|
|
|
1138 ;; Code Iterators
|
|
|
1139 ;; -------------------------------------------------------------------
|
|
|
1140
|
|
|
1141 ;; This code iterator allows the various shifts supported on the core
|
|
|
1142 (define_code_iterator SHIFT [ashift ashiftrt lshiftrt rotatert])
|
|
|
1143
|
|
|
1144 ;; This code iterator allows the shifts supported in arithmetic instructions
|
|
|
1145 (define_code_iterator ASHIFT [ashift ashiftrt lshiftrt])
|
|
|
1146
|
|
|
1147 ;; Code iterator for logical operations
|
|
|
1148 (define_code_iterator LOGICAL [and ior xor])
|
|
|
1149
|
|
131
|
1150 ;; LOGICAL without AND.
|
|
|
1151 (define_code_iterator LOGICAL_OR [ior xor])
|
|
|
1152
|
|
111
|
1153 ;; Code iterator for logical operations whose :nlogical works on SIMD registers.
|
|
|
1154 (define_code_iterator NLOGICAL [and ior])
|
|
|
1155
|
|
|
1156 ;; Code iterator for unary negate and bitwise complement.
|
|
|
1157 (define_code_iterator NEG_NOT [neg not])
|
|
|
1158
|
|
|
1159 ;; Code iterator for sign/zero extension
|
|
|
1160 (define_code_iterator ANY_EXTEND [sign_extend zero_extend])
|
|
|
1161
|
|
|
1162 ;; All division operations (signed/unsigned)
|
|
|
1163 (define_code_iterator ANY_DIV [div udiv])
|
|
|
1164
|
|
|
1165 ;; Code iterator for sign/zero extraction
|
|
|
1166 (define_code_iterator ANY_EXTRACT [sign_extract zero_extract])
|
|
|
1167
|
|
|
1168 ;; Code iterator for equality comparisons
|
|
|
1169 (define_code_iterator EQL [eq ne])
|
|
|
1170
|
|
|
1171 ;; Code iterator for less-than and greater/equal-to
|
|
|
1172 (define_code_iterator LTGE [lt ge])
|
|
|
1173
|
|
|
1174 ;; Iterator for __sync_<op> operations that where the operation can be
|
|
|
1175 ;; represented directly RTL. This is all of the sync operations bar
|
|
|
1176 ;; nand.
|
|
|
1177 (define_code_iterator atomic_op [plus minus ior xor and])
|
|
|
1178
|
|
|
1179 ;; Iterator for integer conversions
|
|
|
1180 (define_code_iterator FIXUORS [fix unsigned_fix])
|
|
|
1181
|
|
|
1182 ;; Iterator for float conversions
|
|
|
1183 (define_code_iterator FLOATUORS [float unsigned_float])
|
|
|
1184
|
|
|
1185 ;; Code iterator for variants of vector max and min.
|
|
|
1186 (define_code_iterator MAXMIN [smax smin umax umin])
|
|
|
1187
|
|
|
1188 (define_code_iterator FMAXMIN [smax smin])
|
|
|
1189
|
|
|
1190 ;; Code iterator for variants of vector max and min.
|
|
|
1191 (define_code_iterator ADDSUB [plus minus])
|
|
|
1192
|
|
|
1193 ;; Code iterator for variants of vector saturating binary ops.
|
|
|
1194 (define_code_iterator BINQOPS [ss_plus us_plus ss_minus us_minus])
|
|
|
1195
|
|
|
1196 ;; Code iterator for variants of vector saturating unary ops.
|
|
|
1197 (define_code_iterator UNQOPS [ss_neg ss_abs])
|
|
|
1198
|
|
|
1199 ;; Code iterator for signed variants of vector saturating binary ops.
|
|
|
1200 (define_code_iterator SBINQOPS [ss_plus ss_minus])
|
|
|
1201
|
|
|
1202 ;; Comparison operators for <F>CM.
|
|
|
1203 (define_code_iterator COMPARISONS [lt le eq ge gt])
|
|
|
1204
|
|
|
1205 ;; Unsigned comparison operators.
|
|
|
1206 (define_code_iterator UCOMPARISONS [ltu leu geu gtu])
|
|
|
1207
|
|
|
1208 ;; Unsigned comparison operators.
|
|
|
1209 (define_code_iterator FAC_COMPARISONS [lt le ge gt])
|
|
|
1210
|
|
131
|
1211 ;; SVE integer unary operations.
|
|
|
1212 (define_code_iterator SVE_INT_UNARY [neg not popcount])
|
|
|
1213
|
|
|
1214 ;; SVE floating-point unary operations.
|
|
|
1215 (define_code_iterator SVE_FP_UNARY [neg abs sqrt])
|
|
|
1216
|
|
|
1217 ;; SVE integer binary operations.
|
|
|
1218 (define_code_iterator SVE_INT_BINARY [plus minus mult smax umax smin umin
|
|
|
1219 and ior xor])
|
|
|
1220
|
|
|
1221 ;; SVE integer binary division operations.
|
|
|
1222 (define_code_iterator SVE_INT_BINARY_SD [div udiv])
|
|
|
1223
|
|
|
1224 ;; SVE integer comparisons.
|
|
|
1225 (define_code_iterator SVE_INT_CMP [lt le eq ne ge gt ltu leu geu gtu])
|
|
|
1226
|
|
|
1227 ;; SVE floating-point comparisons.
|
|
|
1228 (define_code_iterator SVE_FP_CMP [lt le eq ne ge gt])
|
|
|
1229
|
|
111
|
1230 ;; -------------------------------------------------------------------
|
|
|
1231 ;; Code Attributes
|
|
|
1232 ;; -------------------------------------------------------------------
|
|
|
1233 ;; Map rtl objects to optab names
|
|
|
1234 (define_code_attr optab [(ashift "ashl")
|
|
|
1235 (ashiftrt "ashr")
|
|
|
1236 (lshiftrt "lshr")
|
|
|
1237 (rotatert "rotr")
|
|
|
1238 (sign_extend "extend")
|
|
|
1239 (zero_extend "zero_extend")
|
|
|
1240 (sign_extract "extv")
|
|
|
1241 (zero_extract "extzv")
|
|
|
1242 (fix "fix")
|
|
|
1243 (unsigned_fix "fixuns")
|
|
|
1244 (float "float")
|
|
|
1245 (unsigned_float "floatuns")
|
|
131
|
1246 (popcount "popcount")
|
|
111
|
1247 (and "and")
|
|
|
1248 (ior "ior")
|
|
|
1249 (xor "xor")
|
|
|
1250 (not "one_cmpl")
|
|
|
1251 (neg "neg")
|
|
|
1252 (plus "add")
|
|
|
1253 (minus "sub")
|
|
131
|
1254 (mult "mul")
|
|
|
1255 (div "div")
|
|
|
1256 (udiv "udiv")
|
|
111
|
1257 (ss_plus "qadd")
|
|
|
1258 (us_plus "qadd")
|
|
|
1259 (ss_minus "qsub")
|
|
|
1260 (us_minus "qsub")
|
|
|
1261 (ss_neg "qneg")
|
|
|
1262 (ss_abs "qabs")
|
|
131
|
1263 (smin "smin")
|
|
|
1264 (smax "smax")
|
|
|
1265 (umin "umin")
|
|
|
1266 (umax "umax")
|
|
111
|
1267 (eq "eq")
|
|
|
1268 (ne "ne")
|
|
|
1269 (lt "lt")
|
|
|
1270 (ge "ge")
|
|
|
1271 (le "le")
|
|
|
1272 (gt "gt")
|
|
|
1273 (ltu "ltu")
|
|
|
1274 (leu "leu")
|
|
|
1275 (geu "geu")
|
|
131
|
1276 (gtu "gtu")
|
|
|
1277 (abs "abs")
|
|
|
1278 (sqrt "sqrt")])
|
|
111
|
1279
|
|
|
1280 ;; For comparison operators we use the FCM* and CM* instructions.
|
|
|
1281 ;; As there are no CMLE or CMLT instructions which act on 3 vector
|
|
|
1282 ;; operands, we must use CMGE or CMGT and swap the order of the
|
|
|
1283 ;; source operands.
|
|
|
1284
|
|
|
1285 (define_code_attr n_optab [(lt "gt") (le "ge") (eq "eq") (ge "ge") (gt "gt")
|
|
|
1286 (ltu "hi") (leu "hs") (geu "hs") (gtu "hi")])
|
|
|
1287 (define_code_attr cmp_1 [(lt "2") (le "2") (eq "1") (ge "1") (gt "1")
|
|
|
1288 (ltu "2") (leu "2") (geu "1") (gtu "1")])
|
|
|
1289 (define_code_attr cmp_2 [(lt "1") (le "1") (eq "2") (ge "2") (gt "2")
|
|
|
1290 (ltu "1") (leu "1") (geu "2") (gtu "2")])
|
|
|
1291
|
|
|
1292 (define_code_attr CMP [(lt "LT") (le "LE") (eq "EQ") (ge "GE") (gt "GT")
|
|
|
1293 (ltu "LTU") (leu "LEU") (ne "NE") (geu "GEU")
|
|
|
1294 (gtu "GTU")])
|
|
|
1295
|
|
131
|
1296 ;; The AArch64 condition associated with an rtl comparison code.
|
|
|
1297 (define_code_attr cmp_op [(lt "lt")
|
|
|
1298 (le "le")
|
|
|
1299 (eq "eq")
|
|
|
1300 (ne "ne")
|
|
|
1301 (ge "ge")
|
|
|
1302 (gt "gt")
|
|
|
1303 (ltu "lo")
|
|
|
1304 (leu "ls")
|
|
|
1305 (geu "hs")
|
|
|
1306 (gtu "hi")])
|
|
|
1307
|
|
111
|
1308 (define_code_attr fix_trunc_optab [(fix "fix_trunc")
|
|
|
1309 (unsigned_fix "fixuns_trunc")])
|
|
|
1310
|
|
|
1311 ;; Optab prefix for sign/zero-extending operations
|
|
|
1312 (define_code_attr su_optab [(sign_extend "") (zero_extend "u")
|
|
|
1313 (div "") (udiv "u")
|
|
|
1314 (fix "") (unsigned_fix "u")
|
|
|
1315 (float "s") (unsigned_float "u")
|
|
|
1316 (ss_plus "s") (us_plus "u")
|
|
|
1317 (ss_minus "s") (us_minus "u")])
|
|
|
1318
|
|
|
1319 ;; Similar for the instruction mnemonics
|
|
|
1320 (define_code_attr shift [(ashift "lsl") (ashiftrt "asr")
|
|
|
1321 (lshiftrt "lsr") (rotatert "ror")])
|
|
|
1322
|
|
|
1323 ;; Map shift operators onto underlying bit-field instructions
|
|
|
1324 (define_code_attr bfshift [(ashift "ubfiz") (ashiftrt "sbfx")
|
|
|
1325 (lshiftrt "ubfx") (rotatert "extr")])
|
|
|
1326
|
|
|
1327 ;; Logical operator instruction mnemonics
|
|
|
1328 (define_code_attr logical [(and "and") (ior "orr") (xor "eor")])
|
|
|
1329
|
|
|
1330 ;; Operation names for negate and bitwise complement.
|
|
|
1331 (define_code_attr neg_not_op [(neg "neg") (not "not")])
|
|
|
1332
|
|
131
|
1333 ;; Similar, but when the second operand is inverted.
|
|
111
|
1334 (define_code_attr nlogical [(and "bic") (ior "orn") (xor "eon")])
|
|
|
1335
|
|
131
|
1336 ;; Similar, but when both operands are inverted.
|
|
|
1337 (define_code_attr logical_nn [(and "nor") (ior "nand")])
|
|
|
1338
|
|
111
|
1339 ;; Sign- or zero-extending data-op
|
|
|
1340 (define_code_attr su [(sign_extend "s") (zero_extend "u")
|
|
|
1341 (sign_extract "s") (zero_extract "u")
|
|
|
1342 (fix "s") (unsigned_fix "u")
|
|
|
1343 (div "s") (udiv "u")
|
|
|
1344 (smax "s") (umax "u")
|
|
|
1345 (smin "s") (umin "u")])
|
|
|
1346
|
|
131
|
1347 ;; Whether a shift is left or right.
|
|
|
1348 (define_code_attr lr [(ashift "l") (ashiftrt "r") (lshiftrt "r")])
|
|
|
1349
|
|
111
|
1350 ;; Emit conditional branch instructions.
|
|
|
1351 (define_code_attr bcond [(eq "beq") (ne "bne") (lt "bne") (ge "beq")])
|
|
|
1352
|
|
|
1353 ;; Emit cbz/cbnz depending on comparison type.
|
|
|
1354 (define_code_attr cbz [(eq "cbz") (ne "cbnz") (lt "cbnz") (ge "cbz")])
|
|
|
1355
|
|
|
1356 ;; Emit inverted cbz/cbnz depending on comparison type.
|
|
|
1357 (define_code_attr inv_cb [(eq "cbnz") (ne "cbz") (lt "cbz") (ge "cbnz")])
|
|
|
1358
|
|
|
1359 ;; Emit tbz/tbnz depending on comparison type.
|
|
|
1360 (define_code_attr tbz [(eq "tbz") (ne "tbnz") (lt "tbnz") (ge "tbz")])
|
|
|
1361
|
|
|
1362 ;; Emit inverted tbz/tbnz depending on comparison type.
|
|
|
1363 (define_code_attr inv_tb [(eq "tbnz") (ne "tbz") (lt "tbz") (ge "tbnz")])
|
|
|
1364
|
|
|
1365 ;; Max/min attributes.
|
|
|
1366 (define_code_attr maxmin [(smax "max")
|
|
|
1367 (smin "min")
|
|
|
1368 (umax "max")
|
|
|
1369 (umin "min")])
|
|
|
1370
|
|
|
1371 ;; MLA/MLS attributes.
|
|
|
1372 (define_code_attr as [(ss_plus "a") (ss_minus "s")])
|
|
|
1373
|
|
|
1374 ;; Atomic operations
|
|
|
1375 (define_code_attr atomic_optab
|
|
|
1376 [(ior "or") (xor "xor") (and "and") (plus "add") (minus "sub")])
|
|
|
1377
|
|
|
1378 (define_code_attr atomic_op_operand
|
|
|
1379 [(ior "aarch64_logical_operand")
|
|
|
1380 (xor "aarch64_logical_operand")
|
|
|
1381 (and "aarch64_logical_operand")
|
|
|
1382 (plus "aarch64_plus_operand")
|
|
|
1383 (minus "aarch64_plus_operand")])
|
|
|
1384
|
|
|
1385 ;; Constants acceptable for atomic operations.
|
|
|
1386 ;; This definition must appear in this file before the iterators it refers to.
|
|
|
1387 (define_code_attr const_atomic
|
|
|
1388 [(plus "IJ") (minus "IJ")
|
|
|
1389 (xor "<lconst_atomic>") (ior "<lconst_atomic>")
|
|
|
1390 (and "<lconst_atomic>")])
|
|
|
1391
|
|
|
1392 ;; Attribute to describe constants acceptable in atomic logical operations
|
|
|
1393 (define_mode_attr lconst_atomic [(QI "K") (HI "K") (SI "K") (DI "L")])
|
|
|
1394
|
|
131
|
1395 ;; The integer SVE instruction that implements an rtx code.
|
|
|
1396 (define_code_attr sve_int_op [(plus "add")
|
|
|
1397 (minus "sub")
|
|
|
1398 (mult "mul")
|
|
|
1399 (div "sdiv")
|
|
|
1400 (udiv "udiv")
|
|
|
1401 (neg "neg")
|
|
|
1402 (smin "smin")
|
|
|
1403 (smax "smax")
|
|
|
1404 (umin "umin")
|
|
|
1405 (umax "umax")
|
|
|
1406 (and "and")
|
|
|
1407 (ior "orr")
|
|
|
1408 (xor "eor")
|
|
|
1409 (not "not")
|
|
|
1410 (popcount "cnt")])
|
|
|
1411
|
|
|
1412 (define_code_attr sve_int_op_rev [(plus "add")
|
|
|
1413 (minus "subr")
|
|
|
1414 (mult "mul")
|
|
|
1415 (div "sdivr")
|
|
|
1416 (udiv "udivr")
|
|
|
1417 (smin "smin")
|
|
|
1418 (smax "smax")
|
|
|
1419 (umin "umin")
|
|
|
1420 (umax "umax")
|
|
|
1421 (and "and")
|
|
|
1422 (ior "orr")
|
|
|
1423 (xor "eor")])
|
|
|
1424
|
|
|
1425 ;; The floating-point SVE instruction that implements an rtx code.
|
|
|
1426 (define_code_attr sve_fp_op [(plus "fadd")
|
|
|
1427 (neg "fneg")
|
|
|
1428 (abs "fabs")
|
|
|
1429 (sqrt "fsqrt")])
|
|
|
1430
|
|
|
1431 ;; The SVE immediate constraint to use for an rtl code.
|
|
|
1432 (define_code_attr sve_imm_con [(eq "vsc")
|
|
|
1433 (ne "vsc")
|
|
|
1434 (lt "vsc")
|
|
|
1435 (ge "vsc")
|
|
|
1436 (le "vsc")
|
|
|
1437 (gt "vsc")
|
|
|
1438 (ltu "vsd")
|
|
|
1439 (leu "vsd")
|
|
|
1440 (geu "vsd")
|
|
|
1441 (gtu "vsd")])
|
|
|
1442
|
|
111
|
1443 ;; -------------------------------------------------------------------
|
|
|
1444 ;; Int Iterators.
|
|
|
1445 ;; -------------------------------------------------------------------
|
|
131
|
1446
|
|
|
1447 ;; The unspec codes for the SABAL, UABAL AdvancedSIMD instructions.
|
|
|
1448 (define_int_iterator ABAL [UNSPEC_SABAL UNSPEC_UABAL])
|
|
|
1449
|
|
|
1450 ;; The unspec codes for the SABDL2, UABDL2 AdvancedSIMD instructions.
|
|
|
1451 (define_int_iterator ABDL2 [UNSPEC_SABDL2 UNSPEC_UABDL2])
|
|
|
1452
|
|
|
1453 ;; The unspec codes for the SADALP, UADALP AdvancedSIMD instructions.
|
|
|
1454 (define_int_iterator ADALP [UNSPEC_SADALP UNSPEC_UADALP])
|
|
|
1455
|
|
111
|
1456 (define_int_iterator MAXMINV [UNSPEC_UMAXV UNSPEC_UMINV
|
|
|
1457 UNSPEC_SMAXV UNSPEC_SMINV])
|
|
|
1458
|
|
|
1459 (define_int_iterator FMAXMINV [UNSPEC_FMAXV UNSPEC_FMINV
|
|
|
1460 UNSPEC_FMAXNMV UNSPEC_FMINNMV])
|
|
|
1461
|
|
131
|
1462 (define_int_iterator BITWISEV [UNSPEC_ANDV UNSPEC_IORV UNSPEC_XORV])
|
|
|
1463
|
|
|
1464 (define_int_iterator LOGICALF [UNSPEC_ANDF UNSPEC_IORF UNSPEC_XORF])
|
|
|
1465
|
|
111
|
1466 (define_int_iterator HADDSUB [UNSPEC_SHADD UNSPEC_UHADD
|
|
|
1467 UNSPEC_SRHADD UNSPEC_URHADD
|
|
|
1468 UNSPEC_SHSUB UNSPEC_UHSUB
|
|
|
1469 UNSPEC_SRHSUB UNSPEC_URHSUB])
|
|
|
1470
|
|
131
|
1471 (define_int_iterator HADD [UNSPEC_SHADD UNSPEC_UHADD])
|
|
|
1472
|
|
|
1473 (define_int_iterator RHADD [UNSPEC_SRHADD UNSPEC_URHADD])
|
|
|
1474
|
|
111
|
1475 (define_int_iterator DOTPROD [UNSPEC_SDOT UNSPEC_UDOT])
|
|
|
1476
|
|
|
1477 (define_int_iterator ADDSUBHN [UNSPEC_ADDHN UNSPEC_RADDHN
|
|
|
1478 UNSPEC_SUBHN UNSPEC_RSUBHN])
|
|
|
1479
|
|
|
1480 (define_int_iterator ADDSUBHN2 [UNSPEC_ADDHN2 UNSPEC_RADDHN2
|
|
|
1481 UNSPEC_SUBHN2 UNSPEC_RSUBHN2])
|
|
|
1482
|
|
|
1483 (define_int_iterator FMAXMIN_UNS [UNSPEC_FMAX UNSPEC_FMIN
|
|
|
1484 UNSPEC_FMAXNM UNSPEC_FMINNM])
|
|
|
1485
|
|
|
1486 (define_int_iterator PAUTH_LR_SP [UNSPEC_PACISP UNSPEC_AUTISP])
|
|
|
1487
|
|
|
1488 (define_int_iterator PAUTH_17_16 [UNSPEC_PACI1716 UNSPEC_AUTI1716])
|
|
|
1489
|
|
|
1490 (define_int_iterator VQDMULH [UNSPEC_SQDMULH UNSPEC_SQRDMULH])
|
|
|
1491
|
|
|
1492 (define_int_iterator USSUQADD [UNSPEC_SUQADD UNSPEC_USQADD])
|
|
|
1493
|
|
|
1494 (define_int_iterator SUQMOVN [UNSPEC_SQXTN UNSPEC_UQXTN])
|
|
|
1495
|
|
|
1496 (define_int_iterator VSHL [UNSPEC_SSHL UNSPEC_USHL
|
|
|
1497 UNSPEC_SRSHL UNSPEC_URSHL])
|
|
|
1498
|
|
|
1499 (define_int_iterator VSHLL [UNSPEC_SSHLL UNSPEC_USHLL])
|
|
|
1500
|
|
|
1501 (define_int_iterator VQSHL [UNSPEC_SQSHL UNSPEC_UQSHL
|
|
|
1502 UNSPEC_SQRSHL UNSPEC_UQRSHL])
|
|
|
1503
|
|
|
1504 (define_int_iterator VSRA [UNSPEC_SSRA UNSPEC_USRA
|
|
|
1505 UNSPEC_SRSRA UNSPEC_URSRA])
|
|
|
1506
|
|
|
1507 (define_int_iterator VSLRI [UNSPEC_SSLI UNSPEC_USLI
|
|
|
1508 UNSPEC_SSRI UNSPEC_USRI])
|
|
|
1509
|
|
|
1510
|
|
|
1511 (define_int_iterator VRSHR_N [UNSPEC_SRSHR UNSPEC_URSHR])
|
|
|
1512
|
|
|
1513 (define_int_iterator VQSHL_N [UNSPEC_SQSHLU UNSPEC_SQSHL UNSPEC_UQSHL])
|
|
|
1514
|
|
|
1515 (define_int_iterator VQSHRN_N [UNSPEC_SQSHRUN UNSPEC_SQRSHRUN
|
|
|
1516 UNSPEC_SQSHRN UNSPEC_UQSHRN
|
|
|
1517 UNSPEC_SQRSHRN UNSPEC_UQRSHRN])
|
|
|
1518
|
|
|
1519 (define_int_iterator SQRDMLH_AS [UNSPEC_SQRDMLAH UNSPEC_SQRDMLSH])
|
|
|
1520
|
|
|
1521 (define_int_iterator PERMUTE [UNSPEC_ZIP1 UNSPEC_ZIP2
|
|
|
1522 UNSPEC_TRN1 UNSPEC_TRN2
|
|
|
1523 UNSPEC_UZP1 UNSPEC_UZP2])
|
|
|
1524
|
|
131
|
1525 (define_int_iterator OPTAB_PERMUTE [UNSPEC_ZIP1 UNSPEC_ZIP2
|
|
|
1526 UNSPEC_UZP1 UNSPEC_UZP2])
|
|
|
1527
|
|
111
|
1528 (define_int_iterator REVERSE [UNSPEC_REV64 UNSPEC_REV32 UNSPEC_REV16])
|
|
|
1529
|
|
|
1530 (define_int_iterator FRINT [UNSPEC_FRINTZ UNSPEC_FRINTP UNSPEC_FRINTM
|
|
|
1531 UNSPEC_FRINTN UNSPEC_FRINTI UNSPEC_FRINTX
|
|
|
1532 UNSPEC_FRINTA])
|
|
|
1533
|
|
|
1534 (define_int_iterator FCVT [UNSPEC_FRINTZ UNSPEC_FRINTP UNSPEC_FRINTM
|
|
|
1535 UNSPEC_FRINTA UNSPEC_FRINTN])
|
|
|
1536
|
|
|
1537 (define_int_iterator FCVT_F2FIXED [UNSPEC_FCVTZS UNSPEC_FCVTZU])
|
|
|
1538 (define_int_iterator FCVT_FIXED2F [UNSPEC_SCVTF UNSPEC_UCVTF])
|
|
|
1539
|
|
|
1540 (define_int_iterator CRC [UNSPEC_CRC32B UNSPEC_CRC32H UNSPEC_CRC32W
|
|
|
1541 UNSPEC_CRC32X UNSPEC_CRC32CB UNSPEC_CRC32CH
|
|
|
1542 UNSPEC_CRC32CW UNSPEC_CRC32CX])
|
|
|
1543
|
|
|
1544 (define_int_iterator CRYPTO_AES [UNSPEC_AESE UNSPEC_AESD])
|
|
|
1545 (define_int_iterator CRYPTO_AESMC [UNSPEC_AESMC UNSPEC_AESIMC])
|
|
|
1546
|
|
|
1547 (define_int_iterator CRYPTO_SHA1 [UNSPEC_SHA1C UNSPEC_SHA1M UNSPEC_SHA1P])
|
|
|
1548
|
|
|
1549 (define_int_iterator CRYPTO_SHA256 [UNSPEC_SHA256H UNSPEC_SHA256H2])
|
|
|
1550
|
|
131
|
1551 (define_int_iterator CRYPTO_SHA512 [UNSPEC_SHA512H UNSPEC_SHA512H2])
|
|
|
1552
|
|
|
1553 (define_int_iterator CRYPTO_SM3TT [UNSPEC_SM3TT1A UNSPEC_SM3TT1B
|
|
|
1554 UNSPEC_SM3TT2A UNSPEC_SM3TT2B])
|
|
|
1555
|
|
|
1556 (define_int_iterator CRYPTO_SM3PART [UNSPEC_SM3PARTW1 UNSPEC_SM3PARTW2])
|
|
|
1557
|
|
|
1558 ;; Iterators for fp16 operations
|
|
|
1559
|
|
|
1560 (define_int_iterator VFMLA16_LOW [UNSPEC_FMLAL UNSPEC_FMLSL])
|
|
|
1561
|
|
|
1562 (define_int_iterator VFMLA16_HIGH [UNSPEC_FMLAL2 UNSPEC_FMLSL2])
|
|
|
1563
|
|
|
1564 (define_int_iterator UNPACK [UNSPEC_UNPACKSHI UNSPEC_UNPACKUHI
|
|
|
1565 UNSPEC_UNPACKSLO UNSPEC_UNPACKULO])
|
|
|
1566
|
|
|
1567 (define_int_iterator UNPACK_UNSIGNED [UNSPEC_UNPACKULO UNSPEC_UNPACKUHI])
|
|
|
1568
|
|
|
1569 (define_int_iterator MUL_HIGHPART [UNSPEC_SMUL_HIGHPART UNSPEC_UMUL_HIGHPART])
|
|
|
1570
|
|
|
1571 (define_int_iterator SVE_COND_FP_BINARY [UNSPEC_COND_ADD UNSPEC_COND_SUB
|
|
|
1572 UNSPEC_COND_MUL UNSPEC_COND_DIV
|
|
|
1573 UNSPEC_COND_MAX UNSPEC_COND_MIN])
|
|
|
1574
|
|
|
1575 (define_int_iterator SVE_COND_FP_TERNARY [UNSPEC_COND_FMLA
|
|
|
1576 UNSPEC_COND_FMLS
|
|
|
1577 UNSPEC_COND_FNMLA
|
|
|
1578 UNSPEC_COND_FNMLS])
|
|
|
1579
|
|
|
1580 (define_int_iterator SVE_COND_FP_CMP [UNSPEC_COND_LT UNSPEC_COND_LE
|
|
|
1581 UNSPEC_COND_EQ UNSPEC_COND_NE
|
|
|
1582 UNSPEC_COND_GE UNSPEC_COND_GT])
|
|
|
1583
|
|
111
|
1584 ;; Iterators for atomic operations.
|
|
|
1585
|
|
|
1586 (define_int_iterator ATOMIC_LDOP
|
|
|
1587 [UNSPECV_ATOMIC_LDOP_OR UNSPECV_ATOMIC_LDOP_BIC
|
|
|
1588 UNSPECV_ATOMIC_LDOP_XOR UNSPECV_ATOMIC_LDOP_PLUS])
|
|
|
1589
|
|
|
1590 (define_int_attr atomic_ldop
|
|
|
1591 [(UNSPECV_ATOMIC_LDOP_OR "set") (UNSPECV_ATOMIC_LDOP_BIC "clr")
|
|
|
1592 (UNSPECV_ATOMIC_LDOP_XOR "eor") (UNSPECV_ATOMIC_LDOP_PLUS "add")])
|
|
|
1593
|
|
|
1594 ;; -------------------------------------------------------------------
|
|
|
1595 ;; Int Iterators Attributes.
|
|
|
1596 ;; -------------------------------------------------------------------
|
|
131
|
1597
|
|
|
1598 ;; The optab associated with an operation. Note that for ANDF, IORF
|
|
|
1599 ;; and XORF, the optab pattern is not actually defined; we just use this
|
|
|
1600 ;; name for consistency with the integer patterns.
|
|
|
1601 (define_int_attr optab [(UNSPEC_ANDF "and")
|
|
|
1602 (UNSPEC_IORF "ior")
|
|
|
1603 (UNSPEC_XORF "xor")
|
|
|
1604 (UNSPEC_ANDV "and")
|
|
|
1605 (UNSPEC_IORV "ior")
|
|
|
1606 (UNSPEC_XORV "xor")
|
|
|
1607 (UNSPEC_COND_ADD "add")
|
|
|
1608 (UNSPEC_COND_SUB "sub")
|
|
|
1609 (UNSPEC_COND_MUL "mul")
|
|
|
1610 (UNSPEC_COND_DIV "div")
|
|
|
1611 (UNSPEC_COND_MAX "smax")
|
|
|
1612 (UNSPEC_COND_MIN "smin")
|
|
|
1613 (UNSPEC_COND_FMLA "fma")
|
|
|
1614 (UNSPEC_COND_FMLS "fnma")
|
|
|
1615 (UNSPEC_COND_FNMLA "fnms")
|
|
|
1616 (UNSPEC_COND_FNMLS "fms")])
|
|
|
1617
|
|
111
|
1618 (define_int_attr maxmin_uns [(UNSPEC_UMAXV "umax")
|
|
|
1619 (UNSPEC_UMINV "umin")
|
|
|
1620 (UNSPEC_SMAXV "smax")
|
|
|
1621 (UNSPEC_SMINV "smin")
|
|
|
1622 (UNSPEC_FMAX "smax_nan")
|
|
|
1623 (UNSPEC_FMAXNMV "smax")
|
|
|
1624 (UNSPEC_FMAXV "smax_nan")
|
|
|
1625 (UNSPEC_FMIN "smin_nan")
|
|
|
1626 (UNSPEC_FMINNMV "smin")
|
|
|
1627 (UNSPEC_FMINV "smin_nan")
|
|
|
1628 (UNSPEC_FMAXNM "fmax")
|
|
|
1629 (UNSPEC_FMINNM "fmin")])
|
|
|
1630
|
|
|
1631 (define_int_attr maxmin_uns_op [(UNSPEC_UMAXV "umax")
|
|
|
1632 (UNSPEC_UMINV "umin")
|
|
|
1633 (UNSPEC_SMAXV "smax")
|
|
|
1634 (UNSPEC_SMINV "smin")
|
|
|
1635 (UNSPEC_FMAX "fmax")
|
|
|
1636 (UNSPEC_FMAXNMV "fmaxnm")
|
|
|
1637 (UNSPEC_FMAXV "fmax")
|
|
|
1638 (UNSPEC_FMIN "fmin")
|
|
|
1639 (UNSPEC_FMINNMV "fminnm")
|
|
|
1640 (UNSPEC_FMINV "fmin")
|
|
|
1641 (UNSPEC_FMAXNM "fmaxnm")
|
|
|
1642 (UNSPEC_FMINNM "fminnm")])
|
|
|
1643
|
|
131
|
1644 (define_int_attr bit_reduc_op [(UNSPEC_ANDV "andv")
|
|
|
1645 (UNSPEC_IORV "orv")
|
|
|
1646 (UNSPEC_XORV "eorv")])
|
|
|
1647
|
|
|
1648 ;; The SVE logical instruction that implements an unspec.
|
|
|
1649 (define_int_attr logicalf_op [(UNSPEC_ANDF "and")
|
|
|
1650 (UNSPEC_IORF "orr")
|
|
|
1651 (UNSPEC_XORF "eor")])
|
|
|
1652
|
|
|
1653 ;; "s" for signed operations and "u" for unsigned ones.
|
|
|
1654 (define_int_attr su [(UNSPEC_UNPACKSHI "s")
|
|
|
1655 (UNSPEC_UNPACKUHI "u")
|
|
|
1656 (UNSPEC_UNPACKSLO "s")
|
|
|
1657 (UNSPEC_UNPACKULO "u")
|
|
|
1658 (UNSPEC_SMUL_HIGHPART "s")
|
|
|
1659 (UNSPEC_UMUL_HIGHPART "u")])
|
|
|
1660
|
|
111
|
1661 (define_int_attr sur [(UNSPEC_SHADD "s") (UNSPEC_UHADD "u")
|
|
|
1662 (UNSPEC_SRHADD "sr") (UNSPEC_URHADD "ur")
|
|
|
1663 (UNSPEC_SHSUB "s") (UNSPEC_UHSUB "u")
|
|
|
1664 (UNSPEC_SRHSUB "sr") (UNSPEC_URHSUB "ur")
|
|
|
1665 (UNSPEC_ADDHN "") (UNSPEC_RADDHN "r")
|
|
131
|
1666 (UNSPEC_SABAL "s") (UNSPEC_UABAL "u")
|
|
|
1667 (UNSPEC_SABDL2 "s") (UNSPEC_UABDL2 "u")
|
|
|
1668 (UNSPEC_SADALP "s") (UNSPEC_UADALP "u")
|
|
111
|
1669 (UNSPEC_SUBHN "") (UNSPEC_RSUBHN "r")
|
|
|
1670 (UNSPEC_ADDHN2 "") (UNSPEC_RADDHN2 "r")
|
|
|
1671 (UNSPEC_SUBHN2 "") (UNSPEC_RSUBHN2 "r")
|
|
|
1672 (UNSPEC_SQXTN "s") (UNSPEC_UQXTN "u")
|
|
|
1673 (UNSPEC_USQADD "us") (UNSPEC_SUQADD "su")
|
|
|
1674 (UNSPEC_SSLI "s") (UNSPEC_USLI "u")
|
|
|
1675 (UNSPEC_SSRI "s") (UNSPEC_USRI "u")
|
|
|
1676 (UNSPEC_USRA "u") (UNSPEC_SSRA "s")
|
|
|
1677 (UNSPEC_URSRA "ur") (UNSPEC_SRSRA "sr")
|
|
|
1678 (UNSPEC_URSHR "ur") (UNSPEC_SRSHR "sr")
|
|
|
1679 (UNSPEC_SQSHLU "s") (UNSPEC_SQSHL "s")
|
|
|
1680 (UNSPEC_UQSHL "u")
|
|
|
1681 (UNSPEC_SQSHRUN "s") (UNSPEC_SQRSHRUN "s")
|
|
|
1682 (UNSPEC_SQSHRN "s") (UNSPEC_UQSHRN "u")
|
|
|
1683 (UNSPEC_SQRSHRN "s") (UNSPEC_UQRSHRN "u")
|
|
|
1684 (UNSPEC_USHL "u") (UNSPEC_SSHL "s")
|
|
|
1685 (UNSPEC_USHLL "u") (UNSPEC_SSHLL "s")
|
|
|
1686 (UNSPEC_URSHL "ur") (UNSPEC_SRSHL "sr")
|
|
|
1687 (UNSPEC_UQRSHL "u") (UNSPEC_SQRSHL "s")
|
|
|
1688 (UNSPEC_SDOT "s") (UNSPEC_UDOT "u")
|
|
|
1689 ])
|
|
|
1690
|
|
|
1691 (define_int_attr r [(UNSPEC_SQDMULH "") (UNSPEC_SQRDMULH "r")
|
|
|
1692 (UNSPEC_SQSHRUN "") (UNSPEC_SQRSHRUN "r")
|
|
|
1693 (UNSPEC_SQSHRN "") (UNSPEC_UQSHRN "")
|
|
|
1694 (UNSPEC_SQRSHRN "r") (UNSPEC_UQRSHRN "r")
|
|
|
1695 (UNSPEC_SQSHL "") (UNSPEC_UQSHL "")
|
|
|
1696 (UNSPEC_SQRSHL "r")(UNSPEC_UQRSHL "r")
|
|
|
1697 ])
|
|
|
1698
|
|
|
1699 (define_int_attr lr [(UNSPEC_SSLI "l") (UNSPEC_USLI "l")
|
|
|
1700 (UNSPEC_SSRI "r") (UNSPEC_USRI "r")])
|
|
|
1701
|
|
|
1702 (define_int_attr u [(UNSPEC_SQSHLU "u") (UNSPEC_SQSHL "") (UNSPEC_UQSHL "")
|
|
|
1703 (UNSPEC_SQSHRUN "u") (UNSPEC_SQRSHRUN "u")
|
|
131
|
1704 (UNSPEC_SQSHRN "") (UNSPEC_UQSHRN "")
|
|
|
1705 (UNSPEC_SQRSHRN "") (UNSPEC_UQRSHRN "")
|
|
|
1706 (UNSPEC_SHADD "") (UNSPEC_UHADD "u")
|
|
|
1707 (UNSPEC_SRHADD "") (UNSPEC_URHADD "u")])
|
|
111
|
1708
|
|
|
1709 (define_int_attr addsub [(UNSPEC_SHADD "add")
|
|
|
1710 (UNSPEC_UHADD "add")
|
|
|
1711 (UNSPEC_SRHADD "add")
|
|
|
1712 (UNSPEC_URHADD "add")
|
|
|
1713 (UNSPEC_SHSUB "sub")
|
|
|
1714 (UNSPEC_UHSUB "sub")
|
|
|
1715 (UNSPEC_SRHSUB "sub")
|
|
|
1716 (UNSPEC_URHSUB "sub")
|
|
|
1717 (UNSPEC_ADDHN "add")
|
|
|
1718 (UNSPEC_SUBHN "sub")
|
|
|
1719 (UNSPEC_RADDHN "add")
|
|
|
1720 (UNSPEC_RSUBHN "sub")
|
|
|
1721 (UNSPEC_ADDHN2 "add")
|
|
|
1722 (UNSPEC_SUBHN2 "sub")
|
|
|
1723 (UNSPEC_RADDHN2 "add")
|
|
|
1724 (UNSPEC_RSUBHN2 "sub")])
|
|
|
1725
|
|
|
1726 (define_int_attr offsetlr [(UNSPEC_SSLI "") (UNSPEC_USLI "")
|
|
|
1727 (UNSPEC_SSRI "offset_")
|
|
|
1728 (UNSPEC_USRI "offset_")])
|
|
|
1729
|
|
|
1730 ;; Standard pattern names for floating-point rounding instructions.
|
|
|
1731 (define_int_attr frint_pattern [(UNSPEC_FRINTZ "btrunc")
|
|
|
1732 (UNSPEC_FRINTP "ceil")
|
|
|
1733 (UNSPEC_FRINTM "floor")
|
|
|
1734 (UNSPEC_FRINTI "nearbyint")
|
|
|
1735 (UNSPEC_FRINTX "rint")
|
|
|
1736 (UNSPEC_FRINTA "round")
|
|
|
1737 (UNSPEC_FRINTN "frintn")])
|
|
|
1738
|
|
|
1739 ;; frint suffix for floating-point rounding instructions.
|
|
|
1740 (define_int_attr frint_suffix [(UNSPEC_FRINTZ "z") (UNSPEC_FRINTP "p")
|
|
|
1741 (UNSPEC_FRINTM "m") (UNSPEC_FRINTI "i")
|
|
|
1742 (UNSPEC_FRINTX "x") (UNSPEC_FRINTA "a")
|
|
|
1743 (UNSPEC_FRINTN "n")])
|
|
|
1744
|
|
|
1745 (define_int_attr fcvt_pattern [(UNSPEC_FRINTZ "btrunc") (UNSPEC_FRINTA "round")
|
|
|
1746 (UNSPEC_FRINTP "ceil") (UNSPEC_FRINTM "floor")
|
|
|
1747 (UNSPEC_FRINTN "frintn")])
|
|
|
1748
|
|
|
1749 (define_int_attr fcvt_fixed_insn [(UNSPEC_SCVTF "scvtf")
|
|
|
1750 (UNSPEC_UCVTF "ucvtf")
|
|
|
1751 (UNSPEC_FCVTZS "fcvtzs")
|
|
|
1752 (UNSPEC_FCVTZU "fcvtzu")])
|
|
|
1753
|
|
|
1754 ;; Pointer authentication mnemonic prefix.
|
|
|
1755 (define_int_attr pauth_mnem_prefix [(UNSPEC_PACISP "paci")
|
|
|
1756 (UNSPEC_AUTISP "auti")
|
|
|
1757 (UNSPEC_PACI1716 "paci")
|
|
|
1758 (UNSPEC_AUTI1716 "auti")])
|
|
|
1759
|
|
|
1760 ;; Pointer authentication HINT number for NOP space instructions using A Key.
|
|
|
1761 (define_int_attr pauth_hint_num_a [(UNSPEC_PACISP "25")
|
|
|
1762 (UNSPEC_AUTISP "29")
|
|
|
1763 (UNSPEC_PACI1716 "8")
|
|
|
1764 (UNSPEC_AUTI1716 "12")])
|
|
|
1765
|
|
|
1766 (define_int_attr perm_insn [(UNSPEC_ZIP1 "zip") (UNSPEC_ZIP2 "zip")
|
|
|
1767 (UNSPEC_TRN1 "trn") (UNSPEC_TRN2 "trn")
|
|
|
1768 (UNSPEC_UZP1 "uzp") (UNSPEC_UZP2 "uzp")])
|
|
|
1769
|
|
|
1770 ; op code for REV instructions (size within which elements are reversed).
|
|
|
1771 (define_int_attr rev_op [(UNSPEC_REV64 "64") (UNSPEC_REV32 "32")
|
|
|
1772 (UNSPEC_REV16 "16")])
|
|
|
1773
|
|
|
1774 (define_int_attr perm_hilo [(UNSPEC_ZIP1 "1") (UNSPEC_ZIP2 "2")
|
|
|
1775 (UNSPEC_TRN1 "1") (UNSPEC_TRN2 "2")
|
|
131
|
1776 (UNSPEC_UZP1 "1") (UNSPEC_UZP2 "2")
|
|
|
1777 (UNSPEC_UNPACKSHI "hi") (UNSPEC_UNPACKUHI "hi")
|
|
|
1778 (UNSPEC_UNPACKSLO "lo") (UNSPEC_UNPACKULO "lo")])
|
|
111
|
1779
|
|
131
|
1780 ;; Return true if the associated optab refers to the high-numbered lanes,
|
|
|
1781 ;; false if it refers to the low-numbered lanes. The convention is for
|
|
|
1782 ;; "hi" to refer to the low-numbered lanes (the first ones in memory)
|
|
|
1783 ;; for big-endian.
|
|
|
1784 (define_int_attr hi_lanes_optab [(UNSPEC_UNPACKSHI "!BYTES_BIG_ENDIAN")
|
|
|
1785 (UNSPEC_UNPACKUHI "!BYTES_BIG_ENDIAN")
|
|
|
1786 (UNSPEC_UNPACKSLO "BYTES_BIG_ENDIAN")
|
|
|
1787 (UNSPEC_UNPACKULO "BYTES_BIG_ENDIAN")])
|
|
111
|
1788
|
|
|
1789 (define_int_attr crc_variant [(UNSPEC_CRC32B "crc32b") (UNSPEC_CRC32H "crc32h")
|
|
|
1790 (UNSPEC_CRC32W "crc32w") (UNSPEC_CRC32X "crc32x")
|
|
|
1791 (UNSPEC_CRC32CB "crc32cb") (UNSPEC_CRC32CH "crc32ch")
|
|
|
1792 (UNSPEC_CRC32CW "crc32cw") (UNSPEC_CRC32CX "crc32cx")])
|
|
|
1793
|
|
|
1794 (define_int_attr crc_mode [(UNSPEC_CRC32B "QI") (UNSPEC_CRC32H "HI")
|
|
|
1795 (UNSPEC_CRC32W "SI") (UNSPEC_CRC32X "DI")
|
|
|
1796 (UNSPEC_CRC32CB "QI") (UNSPEC_CRC32CH "HI")
|
|
|
1797 (UNSPEC_CRC32CW "SI") (UNSPEC_CRC32CX "DI")])
|
|
|
1798
|
|
|
1799 (define_int_attr aes_op [(UNSPEC_AESE "e") (UNSPEC_AESD "d")])
|
|
|
1800 (define_int_attr aesmc_op [(UNSPEC_AESMC "mc") (UNSPEC_AESIMC "imc")])
|
|
|
1801
|
|
|
1802 (define_int_attr sha1_op [(UNSPEC_SHA1C "c") (UNSPEC_SHA1P "p")
|
|
|
1803 (UNSPEC_SHA1M "m")])
|
|
|
1804
|
|
|
1805 (define_int_attr sha256_op [(UNSPEC_SHA256H "") (UNSPEC_SHA256H2 "2")])
|
|
|
1806
|
|
|
1807 (define_int_attr rdma_as [(UNSPEC_SQRDMLAH "a") (UNSPEC_SQRDMLSH "s")])
|
|
131
|
1808
|
|
|
1809 (define_int_attr sha512_op [(UNSPEC_SHA512H "") (UNSPEC_SHA512H2 "2")])
|
|
|
1810
|
|
|
1811 (define_int_attr sm3tt_op [(UNSPEC_SM3TT1A "1a") (UNSPEC_SM3TT1B "1b")
|
|
|
1812 (UNSPEC_SM3TT2A "2a") (UNSPEC_SM3TT2B "2b")])
|
|
|
1813
|
|
|
1814 (define_int_attr sm3part_op [(UNSPEC_SM3PARTW1 "1") (UNSPEC_SM3PARTW2 "2")])
|
|
|
1815
|
|
|
1816 (define_int_attr f16mac1 [(UNSPEC_FMLAL "a") (UNSPEC_FMLSL "s")
|
|
|
1817 (UNSPEC_FMLAL2 "a") (UNSPEC_FMLSL2 "s")])
|
|
|
1818
|
|
|
1819 ;; The condition associated with an UNSPEC_COND_<xx>.
|
|
|
1820 (define_int_attr cmp_op [(UNSPEC_COND_LT "lt")
|
|
|
1821 (UNSPEC_COND_LE "le")
|
|
|
1822 (UNSPEC_COND_EQ "eq")
|
|
|
1823 (UNSPEC_COND_NE "ne")
|
|
|
1824 (UNSPEC_COND_GE "ge")
|
|
|
1825 (UNSPEC_COND_GT "gt")])
|
|
|
1826
|
|
|
1827 (define_int_attr sve_fp_op [(UNSPEC_COND_ADD "fadd")
|
|
|
1828 (UNSPEC_COND_SUB "fsub")
|
|
|
1829 (UNSPEC_COND_MUL "fmul")
|
|
|
1830 (UNSPEC_COND_DIV "fdiv")
|
|
|
1831 (UNSPEC_COND_MAX "fmaxnm")
|
|
|
1832 (UNSPEC_COND_MIN "fminnm")])
|
|
|
1833
|
|
|
1834 (define_int_attr sve_fp_op_rev [(UNSPEC_COND_ADD "fadd")
|
|
|
1835 (UNSPEC_COND_SUB "fsubr")
|
|
|
1836 (UNSPEC_COND_MUL "fmul")
|
|
|
1837 (UNSPEC_COND_DIV "fdivr")
|
|
|
1838 (UNSPEC_COND_MAX "fmaxnm")
|
|
|
1839 (UNSPEC_COND_MIN "fminnm")])
|
|
|
1840
|
|
|
1841 (define_int_attr sve_fmla_op [(UNSPEC_COND_FMLA "fmla")
|
|
|
1842 (UNSPEC_COND_FMLS "fmls")
|
|
|
1843 (UNSPEC_COND_FNMLA "fnmla")
|
|
|
1844 (UNSPEC_COND_FNMLS "fnmls")])
|
|
|
1845
|
|
|
1846 (define_int_attr sve_fmad_op [(UNSPEC_COND_FMLA "fmad")
|
|
|
1847 (UNSPEC_COND_FMLS "fmsb")
|
|
|
1848 (UNSPEC_COND_FNMLA "fnmad")
|
|
|
1849 (UNSPEC_COND_FNMLS "fnmsb")])
|
|
|
1850
|
|
|
1851 (define_int_attr commutative [(UNSPEC_COND_ADD "true")
|
|
|
1852 (UNSPEC_COND_SUB "false")
|
|
|
1853 (UNSPEC_COND_MUL "true")
|
|
|
1854 (UNSPEC_COND_DIV "false")
|
|
|
1855 (UNSPEC_COND_MIN "true")
|
|
|
1856 (UNSPEC_COND_MAX "true")])
|
