Mercurial > hg > CbC > CbC_gcc

comparison gcc/config/arc/arc.md @ 131:84e7813d76e9

Find changesets by keywords (author, files, the commit message), revision number or hash, or revset expression.
gcc-8.2
author mir3636
date Thu, 25 Oct 2018 07:37:49 +0900
parents 04ced10e8804
children 1830386684a0
comparison
equal deleted inserted replaced
111:04ced10e8804 131:84e7813d76e9
1 ;; Machine description of the Synopsys DesignWare ARC cpu for GNU C compiler 1 ;; Machine description of the Synopsys DesignWare ARC cpu for GNU C compiler
2 ;; Copyright (C) 1994-2017 Free Software Foundation, Inc. 2 ;; Copyright (C) 1994-2018 Free Software Foundation, Inc.
3 3
4 ;; Sources derived from work done by Sankhya Technologies (www.sankhya.com) on 4 ;; Sources derived from work done by Sankhya Technologies (www.sankhya.com) on
5 ;; behalf of Synopsys Inc. 5 ;; behalf of Synopsys Inc.
6 6
7 ;; Position Independent Code support added,Code cleaned up, 7 ;; Position Independent Code support added,Code cleaned up,
80 ;; Include DFA scheduluers 80 ;; Include DFA scheduluers
81 (include ("arc600.md")) 81 (include ("arc600.md"))
82 (include ("arc700.md")) 82 (include ("arc700.md"))
83 (include ("arcEM.md")) 83 (include ("arcEM.md"))
84 (include ("arcHS.md")) 84 (include ("arcHS.md"))
85 (include ("arcHS4x.md"))
85 86
86 ;; Predicates 87 ;; Predicates
87 88
88 (include ("predicates.md")) 89 (include ("predicates.md"))
89 (include ("constraints.md")) 90 (include ("constraints.md"))
134 UNSPEC_ARC_VMAC2H 135 UNSPEC_ARC_VMAC2H
135 UNSPEC_ARC_VMAC2HU 136 UNSPEC_ARC_VMAC2HU
136 UNSPEC_ARC_VMPY2H 137 UNSPEC_ARC_VMPY2H
137 UNSPEC_ARC_VMPY2HU 138 UNSPEC_ARC_VMPY2HU
138 UNSPEC_ARC_STKTIE 139 UNSPEC_ARC_STKTIE
139 ]) 140
140
141 (define_c_enum "vunspec" [
142 VUNSPEC_ARC_RTIE 141 VUNSPEC_ARC_RTIE
143 VUNSPEC_ARC_SYNC 142 VUNSPEC_ARC_SYNC
144 VUNSPEC_ARC_BRK 143 VUNSPEC_ARC_BRK
145 VUNSPEC_ARC_FLAG 144 VUNSPEC_ARC_FLAG
146 VUNSPEC_ARC_SLEEP 145 VUNSPEC_ARC_SLEEP
161 VUNSPEC_ARC_LR_HIGH 160 VUNSPEC_ARC_LR_HIGH
162 VUNSPEC_ARC_EX 161 VUNSPEC_ARC_EX
163 VUNSPEC_ARC_CAS 162 VUNSPEC_ARC_CAS
164 VUNSPEC_ARC_SC 163 VUNSPEC_ARC_SC
165 VUNSPEC_ARC_LL 164 VUNSPEC_ARC_LL
165 VUNSPEC_ARC_BLOCKAGE
166 ]) 166 ])
167 167
168 (define_constants 168 (define_constants
169 [(R0_REG 0) 169 [(R0_REG 0)
170 (R1_REG 1) 170 (R1_REG 1)
204 simd_vmove_with_acc, simd_varith_1cycle, simd_varith_2cycle, 204 simd_vmove_with_acc, simd_varith_1cycle, simd_varith_2cycle,
205 simd_varith_with_acc, simd_vlogic, simd_vlogic_with_acc, 205 simd_varith_with_acc, simd_vlogic, simd_vlogic_with_acc,
206 simd_vcompare, simd_vpermute, simd_vpack, simd_vpack_with_acc, 206 simd_vcompare, simd_vpermute, simd_vpack, simd_vpack_with_acc,
207 simd_valign, simd_valign_with_acc, simd_vcontrol, 207 simd_valign, simd_valign_with_acc, simd_vcontrol,
208 simd_vspecial_3cycle, simd_vspecial_4cycle, simd_dma, mul16_em, div_rem, 208 simd_vspecial_3cycle, simd_vspecial_4cycle, simd_dma, mul16_em, div_rem,
209 fpu, block" 209 fpu, fpu_fuse, fpu_sdiv, fpu_ddiv, fpu_cvt, block"
210 (cond [(eq_attr "is_sfunc" "yes") 210 (cond [(eq_attr "is_sfunc" "yes")
211 (cond [(match_test "!TARGET_LONG_CALLS_SET && (!TARGET_MEDIUM_CALLS || GET_CODE (PATTERN (insn)) != COND_EXEC)") (const_string "call") 211 (cond [(match_test "!TARGET_LONG_CALLS_SET && (!TARGET_MEDIUM_CALLS || GET_CODE (PATTERN (insn)) != COND_EXEC)") (const_string "call")
212 (match_test "flag_pic") (const_string "sfunc")] 212 (match_test "flag_pic") (const_string "sfunc")]
213 (const_string "call_no_delay_slot"))] 213 (const_string "call_no_delay_slot"))]
214 (const_string "binary"))) 214 (const_string "binary")))
384 ;; Length (in # of bytes, long immediate constants counted too). 384 ;; Length (in # of bytes, long immediate constants counted too).
385 ;; ??? There's a nasty interaction between the conditional execution fsm 385 ;; ??? There's a nasty interaction between the conditional execution fsm
386 ;; and insn lengths: insns with shimm values cannot be conditionally executed. 386 ;; and insn lengths: insns with shimm values cannot be conditionally executed.
387 (define_attr "length" "" 387 (define_attr "length" ""
388 (cond 388 (cond
389 [(eq_attr "iscompact" "true,maybe") 389 [(eq_attr "iscompact" "true")
390 (const_int 2)
391
392 (eq_attr "iscompact" "maybe")
390 (cond 393 (cond
391 [(eq_attr "type" "sfunc") 394 [(eq_attr "type" "sfunc")
392 (cond [(match_test "GET_CODE (PATTERN (insn)) == COND_EXEC") 395 (cond [(match_test "GET_CODE (PATTERN (insn)) == COND_EXEC")
393 (const_int 12)] 396 (const_int 12)]
394 (const_int 10)) 397 (const_int 10))
395 (match_test "GET_CODE (PATTERN (insn)) == COND_EXEC") (const_int 4)] 398 (match_test "GET_CODE (PATTERN (insn)) == COND_EXEC") (const_int 4)
399 (match_test "find_reg_note (insn, REG_SAVE_NOTE, GEN_INT (1))")
400 (const_int 4)]
396 (const_int 2)) 401 (const_int 2))
397 402
398 (eq_attr "iscompact" "true_limm") 403 (eq_attr "iscompact" "true_limm")
399 (const_int 6) 404 (const_int 6)
400 405
469 (gt (symbol_ref "arc_hazard (prev_active_insn (insn), 474 (gt (symbol_ref "arc_hazard (prev_active_insn (insn),
470 next_active_insn (insn))") 475 next_active_insn (insn))")
471 (symbol_ref "(arc_hazard (prev_active_insn (insn), insn) 476 (symbol_ref "(arc_hazard (prev_active_insn (insn), insn)
472 + arc_hazard (insn, next_active_insn (insn)))")) 477 + arc_hazard (insn, next_active_insn (insn)))"))
473 (const_string "false") 478 (const_string "false")
479 (match_test "find_reg_note (insn, REG_SAVE_NOTE, GEN_INT (2))")
480 (const_string "false")
474 (eq_attr "iscompact" "maybe") (const_string "true") 481 (eq_attr "iscompact" "maybe") (const_string "true")
475 ] 482 ]
476 483
477 (if_then_else (eq_attr "length" "2,4") 484 (if_then_else (eq_attr "length" "2,4")
478 (const_string "true") 485 (const_string "true")
495 502
496 ;; Instructions that we can put into a delay slot and conditionalize. 503 ;; Instructions that we can put into a delay slot and conditionalize.
497 (define_attr "cond_delay_insn" "no,yes" 504 (define_attr "cond_delay_insn" "no,yes"
498 (cond [(eq_attr "cond" "!canuse") (const_string "no") 505 (cond [(eq_attr "cond" "!canuse") (const_string "no")
499 (eq_attr "type" "call,branch,uncond_branch,jump,brcc") 506 (eq_attr "type" "call,branch,uncond_branch,jump,brcc")
507 (const_string "no")
508 (match_test "find_reg_note (insn, REG_SAVE_NOTE, GEN_INT (2))")
500 (const_string "no") 509 (const_string "no")
501 (eq_attr "length" "2,4") (const_string "yes")] 510 (eq_attr "length" "2,4") (const_string "yes")]
502 (const_string "no"))) 511 (const_string "no")))
503 512
504 (define_attr "in_ret_delay_slot" "no,yes" 513 (define_attr "in_ret_delay_slot" "no,yes"
589 ;; - either canuse_limm is not eligible for delay slots, and has no 598 ;; - either canuse_limm is not eligible for delay slots, and has no
590 ;; delay slots, or arc_reorg has to treat them as nocond, or it has to 599 ;; delay slots, or arc_reorg has to treat them as nocond, or it has to
591 ;; somehow modify them to become inelegible for delay slots if a decision 600 ;; somehow modify them to become inelegible for delay slots if a decision
592 ;; is made that makes conditional execution required. 601 ;; is made that makes conditional execution required.
593 602
594 (define_attr "tune" "none,arc600,arc700_4_2_std,arc700_4_2_xmac" 603 (define_attr "tune" "none,arc600,arc700_4_2_std,arc700_4_2_xmac, core_3, \
604 archs4x, archs4xd, archs4xd_slow"
595 (const 605 (const
596 (cond [(symbol_ref "arc_tune == TUNE_ARC600") 606 (cond [(symbol_ref "arc_tune == TUNE_ARC600")
597 (const_string "arc600") 607 (const_string "arc600")
598 (symbol_ref "arc_tune == TUNE_ARC700_4_2_STD") 608 (symbol_ref "arc_tune == TUNE_ARC700_4_2_STD")
599 (const_string "arc700_4_2_std") 609 (const_string "arc700_4_2_std")
600 (symbol_ref "arc_tune == TUNE_ARC700_4_2_XMAC") 610 (symbol_ref "arc_tune == TUNE_ARC700_4_2_XMAC")
601 (const_string "arc700_4_2_xmac")] 611 (const_string "arc700_4_2_xmac")
612 (symbol_ref "arc_tune == ARC_TUNE_CORE_3")
613 (const_string "core_3")
614 (symbol_ref "arc_tune == TUNE_ARCHS4X")
615 (const_string "archs4x")
616 (ior (symbol_ref "arc_tune == TUNE_ARCHS4XD")
617 (symbol_ref "arc_tune == TUNE_ARCHS4XD_SLOW"))
618 (const_string "archs4xd")]
602 (const_string "none")))) 619 (const_string "none"))))
603 620
604 (define_attr "tune_arc700" "false,true" 621 (define_attr "tune_arc700" "false,true"
605 (if_then_else (eq_attr "tune" "arc700_4_2_std, arc700_4_2_xmac") 622 (if_then_else (eq_attr "tune" "arc700_4_2_std, arc700_4_2_xmac")
606 (const_string "true") 623 (const_string "true")
607 (const_string "false"))) 624 (const_string "false")))
625
626 (define_attr "tune_dspmpy" "none, slow, fast"
627 (const
628 (cond [(ior (symbol_ref "arc_tune == TUNE_ARCHS4X")
629 (symbol_ref "arc_tune == TUNE_ARCHS4XD"))
630 (const_string "fast")
631 (symbol_ref "arc_tune == TUNE_ARCHS4XD_SLOW")
632 (const_string "slow")]
633 (const_string "none"))))
608 634
609 ;; Move instructions. 635 ;; Move instructions.
610 (define_expand "movqi" 636 (define_expand "movqi"
611 [(set (match_operand:QI 0 "move_dest_operand" "") 637 [(set (match_operand:QI 0 "move_dest_operand" "")
612 (match_operand:QI 1 "general_operand" ""))] 638 (match_operand:QI 1 "general_operand" ""))]
635 mov%? %0,%1%& 661 mov%? %0,%1%&
636 mov%? %0,%1 662 mov%? %0,%1
637 mov%? %0,%1 663 mov%? %0,%1
638 mov%? %0,%1 664 mov%? %0,%1
639 mov%? %0,%1 665 mov%? %0,%1
640 mov%? %0,%S1 666 mov%? %0,%1
641 ldb%? %0,%1%& 667 ldb%? %0,%1%&
642 stb%? %1,%0%& 668 stb%? %1,%0%&
643 ldb%? %0,%1%& 669 ldb%? %0,%1%&
644 xldb%U1 %0,%1 670 xldb%U1 %0,%1
645 ldb%U1%V1 %0,%1 671 ldb%U1%V1 %0,%1
676 mov%? %0,%1%& 702 mov%? %0,%1%&
677 mov%? %0,%1%& 703 mov%? %0,%1%&
678 mov%? %0,%1 704 mov%? %0,%1
679 mov%? %0,%1 705 mov%? %0,%1
680 mov%? %0,%1 706 mov%? %0,%1
681 mov%? %0,%S1%& 707 mov%? %0,%1%&
682 mov%? %0,%S1 708 mov%? %0,%1
683 mov%? %0,%S1 709 mov%? %0,%1
684 ld%_%? %0,%1%& 710 ld%_%? %0,%1%&
685 st%_%? %1,%0%& 711 st%_%? %1,%0%&
686 xld%_%U1 %0,%1 712 xld%_%U1 %0,%1
687 ld%_%U1%V1 %0,%1 713 ld%_%U1%V1 %0,%1
688 xst%_%U0 %1,%0 714 xst%_%U0 %1,%0
689 st%_%U0%V0 %1,%0 715 st%_%U0%V0 %1,%0
690 st%_%U0%V0 %1,%0 716 st%_%U0%V0 %1,%0
691 st%_%U0%V0 %S1,%0 717 st%_%U0%V0 %1,%0
692 st%_%U0%V0 %S1,%0" 718 st%_%U0%V0 %1,%0"
693 [(set_attr "type" "move,move,move,move,move,move,move,move,move,move,move,load,store,load,load,store,store,store,store,store") 719 [(set_attr "type" "move,move,move,move,move,move,move,move,move,move,move,load,store,load,load,store,store,store,store,store")
694 (set_attr "iscompact" "maybe,maybe,maybe,true,true,false,false,false,maybe_limm,maybe_limm,false,true,true,false,false,false,false,false,false,false") 720 (set_attr "iscompact" "maybe,maybe,maybe,true,true,false,false,false,maybe_limm,maybe_limm,false,true,true,false,false,false,false,false,false,false")
695 (set_attr "predicable" "yes,no,yes,no,no,yes,no,yes,yes,yes,yes,no,no,no,no,no,no,no,no,no") 721 (set_attr "predicable" "yes,no,yes,no,no,yes,no,yes,yes,yes,yes,no,no,no,no,no,no,no,no,no")
696 (set_attr "cpu_facility" "av1,av1,av1,av2,av2,*,*,*,*,*,*,*,*,*,*,*,*,*,av2,*")]) 722 (set_attr "cpu_facility" "av1,av1,av1,av2,av2,*,*,*,*,*,*,*,*,*,*,*,*,*,av2,*")])
697 723
718 || register_operand (operands[1], SImode) 744 || register_operand (operands[1], SImode)
719 || (CONSTANT_P (operands[1]) 745 || (CONSTANT_P (operands[1])
720 /* Don't use a LIMM that we could load with a single insn - we loose 746 /* Don't use a LIMM that we could load with a single insn - we loose
721 delay-slot filling opportunities. */ 747 delay-slot filling opportunities. */
722 && !satisfies_constraint_I (operands[1]) 748 && !satisfies_constraint_I (operands[1])
723 && satisfies_constraint_Usc (operands[0]))" 749 && satisfies_constraint_Usc (operands[0]))
750 || (satisfies_constraint_Cm3 (operands[1])
751 && memory_operand (operands[0], SImode))"
724 "@ 752 "@
725 mov%? %0,%1%& ;0 753 mov%? %0,%1%& ;0
726 mov%? %0,%1%& ;1 754 mov%? %0,%1%& ;1
727 mov%? %0,%1%& ;2 755 mov%? %0,%1%& ;2
728 mov%? %0,%1%& ;3 756 mov%? %0,%1%& ;3
732 ror %0,((%1*2+1) & 0x3f) ;7 760 ror %0,((%1*2+1) & 0x3f) ;7
733 movl.cl %0,%1 ;8 761 movl.cl %0,%1 ;8
734 movh.cl %0,%L1>>16 ;9 762 movh.cl %0,%L1>>16 ;9
735 * return INTVAL (operands[1]) & 0xffffff ? \"movbi.cl %0,%1 >> %p1,%p1,8;10\" : \"movbi.cl %0,%L1 >> 24,24,8;10\"; 763 * return INTVAL (operands[1]) & 0xffffff ? \"movbi.cl %0,%1 >> %p1,%p1,8;10\" : \"movbi.cl %0,%L1 >> 24,24,8;10\";
736 mov%? %0,%1 ;11 764 mov%? %0,%1 ;11
737 add %0,%S1 ;12 765 add %0,%1 ;12
738 add %0,pcl,%1@pcl ;13 766 add %0,pcl,%1@pcl ;13
739 mov%? %0,%1 ;14 767 mov%? %0,%j1 ;14
740 mov%? %0,%1 ;15 768 mov%? %0,%j1 ;15
741 mov%? %0,%1 ;16 769 mov%? %0,%j1 ;16
742 ld%?%U1 %0,%1 ;17 770 ld%? %0,%1 ;17
743 st%? %1,%0%& ;18 771 st%? %1,%0%& ;18
744 * return arc_short_long (insn, \"push%? %1%&\", \"st%U0 %1,%0%&\"); 772 * return arc_short_long (insn, \"push%? %1%&\", \"st%U0 %1,%0%&\");
745 * return arc_short_long (insn, \"pop%? %0%&\", \"ld%U1 %0,%1%&\"); 773 * return arc_short_long (insn, \"pop%? %0%&\", \"ld%U1 %0,%1%&\");
746 ld%? %0,%1%& ;21 774 ld%? %0,%1%& ;21
747 xld%U1 %0,%1 ;22 775 xld%U1 %0,%1 ;22
786 UNSPEC_ARC_DIRECT))] 814 UNSPEC_ARC_DIRECT))]
787 "" 815 ""
788 "st%U0 %1,%0\;st%U0.di %1,%0" 816 "st%U0 %1,%0\;st%U0.di %1,%0"
789 [(set_attr "type" "store")]) 817 [(set_attr "type" "store")])
790 818
819 ;; Combiner patterns for compare with zero
820 (define_mode_iterator SQH [QI HI])
821 (define_mode_attr SQH_postfix [(QI "b") (HI "%_")])
822
823 (define_code_iterator SEZ [sign_extend zero_extend])
824 (define_code_attr SEZ_prefix [(sign_extend "sex") (zero_extend "ext")])
825
826 (define_insn "*<SEZ_prefix>xt<SQH_postfix>_cmp0_noout"
827 [(set (match_operand 0 "cc_set_register" "")
828 (compare:CC_ZN (SEZ:SI (match_operand:SQH 1 "register_operand" "r"))
829 (const_int 0)))]
830 ""
831 "<SEZ_prefix><SQH_postfix>.f\\t0,%1"
832 [(set_attr "type" "compare")
833 (set_attr "cond" "set_zn")])
834
835 (define_insn "*<SEZ_prefix>xt<SQH_postfix>_cmp0"
836 [(set (match_operand 0 "cc_set_register" "")
837 (compare:CC_ZN (SEZ:SI (match_operand:SQH 1 "register_operand" "r"))
838 (const_int 0)))
839 (set (match_operand:SI 2 "register_operand" "=r")
840 (SEZ:SI (match_dup 1)))]
841 ""
842 "<SEZ_prefix><SQH_postfix>.f\\t%2,%1"
843 [(set_attr "type" "compare")
844 (set_attr "cond" "set_zn")])
845
846 (define_insn "*xbfu_cmp0_noout"
847 [(set (match_operand 0 "cc_set_register" "")
848 (compare:CC_Z
849 (zero_extract:SI
850 (match_operand:SI 1 "register_operand" " r,r")
851 (match_operand:SI 2 "const_int_operand" "C3p,n")
852 (match_operand:SI 3 "const_int_operand" " n,n"))
853 (const_int 0)))]
854 "TARGET_HS && TARGET_BARREL_SHIFTER"
855 {
856 int assemble_op2 = (((INTVAL (operands[2]) - 1) & 0x1f) << 5) | (INTVAL (operands[3]) & 0x1f);
857 operands[2] = GEN_INT (assemble_op2);
858 return "xbfu%?.f\\t0,%1,%2";
859 }
860 [(set_attr "type" "shift")
861 (set_attr "iscompact" "false")
862 (set_attr "length" "4,8")
863 (set_attr "predicable" "no")
864 (set_attr "cond" "set_zn")])
865
866 (define_insn "*xbfu_cmp0"
867 [(set (match_operand 4 "cc_set_register" "")
868 (compare:CC_Z
869 (zero_extract:SI
870 (match_operand:SI 1 "register_operand" "0 ,r,0")
871 (match_operand:SI 2 "const_int_operand" "C3p,n,n")
872 (match_operand:SI 3 "const_int_operand" "n ,n,n"))
873 (const_int 0)))
874 (set (match_operand:SI 0 "register_operand" "=r,r,r")
875 (zero_extract:SI (match_dup 1) (match_dup 2) (match_dup 3)))]
876 "TARGET_HS && TARGET_BARREL_SHIFTER"
877 {
878 int assemble_op2 = (((INTVAL (operands[2]) - 1) & 0x1f) << 5) | (INTVAL (operands[3]) & 0x1f);
879 operands[2] = GEN_INT (assemble_op2);
880 return "xbfu%?.f\\t%0,%1,%2";
881 }
882 [(set_attr "type" "shift")
883 (set_attr "iscompact" "false")
884 (set_attr "length" "4,8,8")
885 (set_attr "predicable" "yes,no,yes")
886 (set_attr "cond" "set_zn")])
887
888 ; splitting to 'tst' allows short insns and combination into brcc.
791 (define_insn_and_split "*movsi_set_cc_insn" 889 (define_insn_and_split "*movsi_set_cc_insn"
792 [(set (match_operand:CC_ZN 2 "cc_set_register" "") 890 [(set (match_operand 2 "cc_set_register" "")
793 (match_operator:CC_ZN 3 "zn_compare_operator" 891 (match_operator 3 "zn_compare_operator"
794 [(match_operand:SI 1 "nonmemory_operand" "cI,cL,Cal") (const_int 0)])) 892 [(match_operand:SI 1 "nonmemory_operand" "rL,rI,Cal")
795 (set (match_operand:SI 0 "register_operand" "=w,w,w") 893 (const_int 0)]))
894 (set (match_operand:SI 0 "register_operand" "=r,r,r")
796 (match_dup 1))] 895 (match_dup 1))]
797 "" 896 ""
798 "mov%?.f %0,%S1" 897 "mov%?.f\\t%0,%1"
799 ; splitting to 'tst' allows short insns and combination into brcc.
800 "reload_completed && operands_match_p (operands[0], operands[1])" 898 "reload_completed && operands_match_p (operands[0], operands[1])"
801 [(set (match_dup 2) (match_dup 3))] 899 [(set (match_dup 2) (match_dup 3))]
802 "" 900 ""
803 [(set_attr "type" "compare") 901 [(set_attr "type" "compare")
804 (set_attr "predicable" "no,yes,yes") 902 (set_attr "predicable" "yes,no,yes")
805 (set_attr "cond" "set_zn") 903 (set_attr "cond" "set_zn")
806 (set_attr "length" "4,4,8")]) 904 (set_attr "length" "4,4,8")])
807 905
808 (define_insn "unary_comparison" 906 (define_insn "unary_comparison"
809 [(set (match_operand:CC_ZN 0 "cc_set_register" "") 907 [(set (match_operand:CC_ZN 0 "cc_set_register" "")
882 default: 980 default:
883 gcc_unreachable (); 981 gcc_unreachable ();
884 } 982 }
885 " 983 "
886 [(set_attr "iscompact" "maybe,maybe,false,false,false,false,false,false") 984 [(set_attr "iscompact" "maybe,maybe,false,false,false,false,false,false")
887 (set_attr "type" "compare,compare,compare,compare,compare,compare,shift,compare") 985 (set_attr "type" "compare,compare,compare,compare,compare,compare,binary,compare")
888 (set_attr "length" "*,*,4,4,4,4,4,8") 986 (set_attr "length" "*,*,4,4,4,4,4,8")
889 (set_attr "predicable" "no,yes,no,yes,no,no,no,yes") 987 (set_attr "predicable" "no,yes,no,yes,no,no,no,yes")
890 (set_attr "cond" "set_zn")]) 988 (set_attr "cond" "set_zn")])
891 989
892 ; ??? Sometimes, if an AND with a constant can be expressed as a zero_extract, 990 ; ??? Sometimes, if an AND with a constant can be expressed as a zero_extract,
949 [(set_attr "iscompact" "maybe,false,false,false,false") 1047 [(set_attr "iscompact" "maybe,false,false,false,false")
950 (set_attr "type" "compare,compare,compare,shift,compare") 1048 (set_attr "type" "compare,compare,compare,shift,compare")
951 (set_attr "cond" "set_zn") 1049 (set_attr "cond" "set_zn")
952 (set_attr "length" "*,4,4,4,8")]) 1050 (set_attr "length" "*,4,4,4,8")])
953 1051
954 (define_insn "*commutative_binary_comparison" 1052 ;; The next two patterns are for plos, ior, xor, and, and mult.
955 [(set (match_operand:CC_ZN 0 "cc_set_register" "") 1053 (define_insn "*commutative_binary_cmp0_noout"
956 (match_operator:CC_ZN 5 "zn_compare_operator" 1054 [(set (match_operand 0 "cc_set_register" "")
957 [(match_operator:SI 4 "commutative_operator" 1055 (match_operator 4 "zn_compare_operator"
958 [(match_operand:SI 1 "register_operand" "%c,c") 1056 [(match_operator:SI 3 "commutative_operator"
959 (match_operand:SI 2 "nonmemory_operand" "cL,Cal")]) 1057 [(match_operand:SI 1 "register_operand" "%r,r")
960 (const_int 0)])) 1058 (match_operand:SI 2 "nonmemory_operand" "rL,Cal")])
961 (clobber (match_scratch:SI 3 "=X,X"))] 1059 (const_int 0)]))]
962 "" 1060 ""
963 "%O4.f 0,%1,%2" 1061 "%O3.f\\t0,%1,%2"
964 [(set_attr "type" "compare") 1062 [(set_attr "type" "compare")
965 (set_attr "cond" "set_zn") 1063 (set_attr "cond" "set_zn")
966 (set_attr "length" "4,8")]) 1064 (set_attr "length" "4,8")])
1065
1066 (define_insn "*commutative_binary_cmp0"
1067 [(set (match_operand 3 "cc_set_register" "")
1068 (match_operator 5 "zn_compare_operator"
1069 [(match_operator:SI 4 "commutative_operator"
1070 [(match_operand:SI 1 "register_operand" "%0, 0,r,r")
1071 (match_operand:SI 2 "nonmemory_operand" "rL,rI,r,Cal")])
1072 (const_int 0)]))
1073 (set (match_operand:SI 0 "register_operand" "=r,r,r,r")
1074 (match_dup 4))]
1075 ""
1076 "%O4.f\\t%0,%1,%2"
1077 [(set_attr "type" "compare")
1078 (set_attr "cond" "set_zn")
1079 (set_attr "predicable" "yes,yes,no,no")
1080 (set_attr "length" "4,4,4,8")])
967 1081
968 ; for flag setting 'add' instructions like if (a+b) { ...} 1082 ; for flag setting 'add' instructions like if (a+b) { ...}
969 ; the combiner needs this pattern 1083 ; the combiner needs this pattern
970 (define_insn "*addsi_compare" 1084 (define_insn "*addsi_compare"
971 [(set (reg:CC_ZN CC_REG) 1085 [(set (reg:CC_ZN CC_REG)
1035 "%O4.f %0,%1,%2 ; mult commutative" 1149 "%O4.f %0,%1,%2 ; mult commutative"
1036 [(set_attr "type" "compare,compare,compare") 1150 [(set_attr "type" "compare,compare,compare")
1037 (set_attr "cond" "set_zn,set_zn,set_zn") 1151 (set_attr "cond" "set_zn,set_zn,set_zn")
1038 (set_attr "length" "4,4,8")]) 1152 (set_attr "length" "4,4,8")])
1039 1153
1040 ; this pattern is needed by combiner for cases like if (c=a<<b) { ... } 1154 (define_insn "*noncommutative_binary_cmp0"
1041 (define_insn "*noncommutative_binary_comparison_result_used" 1155 [(set (match_operand 3 "cc_set_register" "")
1042 [(set (match_operand 3 "cc_register" "")
1043 (match_operator 5 "zn_compare_operator" 1156 (match_operator 5 "zn_compare_operator"
1044 [(match_operator:SI 4 "noncommutative_operator" 1157 [(match_operator:SI 4 "noncommutative_operator"
1045 [(match_operand:SI 1 "register_operand" "c,0,c") 1158 [(match_operand:SI 1 "register_operand" "0,r,0, 0,r")
1046 (match_operand:SI 2 "nonmemory_operand" "cL,I,?Cal")]) 1159 (match_operand:SI 2 "nonmemory_operand" "rL,r,I,Cal,Cal")])
1047 (const_int 0)])) 1160 (const_int 0)]))
1048 (set (match_operand:SI 0 "register_operand" "=w,w,w") 1161 (set (match_operand:SI 0 "register_operand" "=r,r,r,r,r")
1049 (match_dup 4 ))] 1162 (match_dup 4))]
1050 "TARGET_BARREL_SHIFTER || GET_CODE (operands[4]) == MINUS" 1163 ""
1051 "%O4.f %0,%1,%2" 1164 "%O4%?.f\\t%0,%1,%2"
1052 [(set_attr "type" "compare,compare,compare") 1165 [(set_attr "type" "compare")
1053 (set_attr "cond" "set_zn,set_zn,set_zn") 1166 (set_attr "cond" "set_zn")
1054 (set_attr "length" "4,4,8")]) 1167 (set_attr "predicable" "yes,no,no,yes,no")
1055 1168 (set_attr "length" "4,4,4,8,8")])
1056 (define_insn "*noncommutative_binary_comparison" 1169
1057 [(set (match_operand:CC_ZN 0 "cc_set_register" "") 1170 (define_insn "*noncommutative_binary_cmp0_noout"
1058 (match_operator:CC_ZN 5 "zn_compare_operator" 1171 [(set (match_operand 0 "cc_set_register" "")
1172 (match_operator 3 "zn_compare_operator"
1059 [(match_operator:SI 4 "noncommutative_operator" 1173 [(match_operator:SI 4 "noncommutative_operator"
1060 [(match_operand:SI 1 "register_operand" "c,c") 1174 [(match_operand:SI 1 "register_operand" "r,r")
1061 (match_operand:SI 2 "nonmemory_operand" "cL,Cal")]) 1175 (match_operand:SI 2 "nonmemory_operand" "rL,Cal")])
1176 (const_int 0)]))]
1177 ""
1178 "%O4.f\\t0,%1,%2"
1179 [(set_attr "type" "compare")
1180 (set_attr "cond" "set_zn")
1181 (set_attr "length" "4,8")])
1182
1183 ;;rsub variants
1184 (define_insn "*rsub_cmp0"
1185 [(set (match_operand 4 "cc_set_register" "")
1186 (match_operator 3 "zn_compare_operator"
1187 [(minus:SI
1188 (match_operand:SI 1 "nonmemory_operand" "rL,Cal")
1189 (match_operand:SI 2 "register_operand" "r,r"))
1062 (const_int 0)])) 1190 (const_int 0)]))
1063 (clobber (match_scratch:SI 3 "=X,X"))] 1191 (set (match_operand:SI 0 "register_operand" "=r,r")
1064 "TARGET_BARREL_SHIFTER || GET_CODE (operands[4]) == MINUS" 1192 (minus:SI (match_dup 1) (match_dup 2)))]
1065 "%O4.f 0,%1,%2" 1193 ""
1194 "rsub.f\\t%0,%2,%1"
1195 [(set_attr "type" "compare")
1196 (set_attr "cond" "set_zn")
1197 (set_attr "length" "4,8")])
1198
1199 (define_insn "*rsub_cmp0_noout"
1200 [(set (match_operand 0 "cc_set_register" "")
1201 (match_operator 3 "zn_compare_operator"
1202 [(minus:SI
1203 (match_operand:SI 1 "nonmemory_operand" "rL,Cal")
1204 (match_operand:SI 2 "register_operand" "r,r"))
1205 (const_int 0)]))]
1206 ""
1207 "rsub.f\\t0,%2,%1"
1066 [(set_attr "type" "compare") 1208 [(set_attr "type" "compare")
1067 (set_attr "cond" "set_zn") 1209 (set_attr "cond" "set_zn")
1068 (set_attr "length" "4,8")]) 1210 (set_attr "length" "4,8")])
1069 1211
1070 (define_expand "bic_f_zn" 1212 (define_expand "bic_f_zn"
1101 if (prepare_move_operands (operands, DImode)) 1243 if (prepare_move_operands (operands, DImode))
1102 DONE; 1244 DONE;
1103 ") 1245 ")
1104 1246
1105 (define_insn_and_split "*movdi_insn" 1247 (define_insn_and_split "*movdi_insn"
1106 [(set (match_operand:DI 0 "move_dest_operand" "=w, w,r,m") 1248 [(set (match_operand:DI 0 "move_dest_operand" "=w, w,r, m")
1107 (match_operand:DI 1 "move_double_src_operand" "c,Hi,m,c"))] 1249 (match_operand:DI 1 "move_double_src_operand" "c,Hi,m,cCm3"))]
1108 "register_operand (operands[0], DImode) 1250 "register_operand (operands[0], DImode)
1109 || register_operand (operands[1], DImode)" 1251 || register_operand (operands[1], DImode)
1252 || (satisfies_constraint_Cm3 (operands[1])
1253 && memory_operand (operands[0], DImode))"
1110 "* 1254 "*
1111 { 1255 {
1112 switch (which_alternative) 1256 switch (which_alternative)
1113 { 1257 {
1114 default: 1258 default:
1115 return \"#\"; 1259 return \"#\";
1116 1260
1117 case 2: 1261 case 2:
1118 if (TARGET_LL64 1262 if (TARGET_LL64
1119 && ((even_register_operand (operands[0], DImode) 1263 && memory_operand (operands[1], DImode)
1120 && memory_operand (operands[1], DImode)) 1264 && even_register_operand (operands[0], DImode))
1121 || (memory_operand (operands[0], DImode)
1122 && even_register_operand (operands[1], DImode))))
1123 return \"ldd%U1%V1 %0,%1%&\"; 1265 return \"ldd%U1%V1 %0,%1%&\";
1124 return \"#\"; 1266 return \"#\";
1125 1267
1126 case 3: 1268 case 3:
1127 if (TARGET_LL64 1269 if (TARGET_LL64
1128 && ((even_register_operand (operands[0], DImode) 1270 && memory_operand (operands[0], DImode)
1129 && memory_operand (operands[1], DImode)) 1271 && (even_register_operand (operands[1], DImode)
1130 || (memory_operand (operands[0], DImode) 1272 || satisfies_constraint_Cm3 (operands[1])))
1131 && even_register_operand (operands[1], DImode))))
1132 return \"std%U0%V0 %1,%0\"; 1273 return \"std%U0%V0 %1,%0\";
1133 return \"#\"; 1274 return \"#\";
1134 } 1275 }
1135 }" 1276 }"
1136 "reload_completed" 1277 "reload_completed"
1151 (match_operand:SF 1 "general_operand" ""))] 1292 (match_operand:SF 1 "general_operand" ""))]
1152 "" 1293 ""
1153 "if (prepare_move_operands (operands, SFmode)) DONE;") 1294 "if (prepare_move_operands (operands, SFmode)) DONE;")
1154 1295
1155 (define_insn "*movsf_insn" 1296 (define_insn "*movsf_insn"
1156 [(set (match_operand:SF 0 "move_dest_operand" "=h,w,w,r,m") 1297 [(set (match_operand:SF 0 "move_dest_operand" "=h,h, r,r, q,S,Usc,r,m")
1157 (match_operand:SF 1 "move_src_operand" "hCm1,c,E,m,c"))] 1298 (match_operand:SF 1 "move_src_operand" "hCfZ,E,rCfZ,E,Uts,q, E,m,r"))]
1158 "register_operand (operands[0], SFmode) 1299 "register_operand (operands[0], SFmode)
1159 || register_operand (operands[1], SFmode)" 1300 || register_operand (operands[1], SFmode)"
1160 "@ 1301 "@
1161 mov%? %0,%1 1302 mov%?\\t%0,%1
1162 mov%? %0,%1 1303 mov%?\\t%0,%1 ; %A1
1163 mov%? %0,%1 ; %A1 1304 mov%?\\t%0,%1
1164 ld%U1%V1 %0,%1 1305 mov%?\\t%0,%1 ; %A1
1165 st%U0%V0 %1,%0" 1306 ld%?%U1\\t%0,%1
1166 [(set_attr "type" "move,move,move,load,store") 1307 st%?\\t%1,%0
1167 (set_attr "predicable" "no,yes,yes,no,no") 1308 st%U0%V0\\t%1,%0
1168 (set_attr "iscompact" "true,false,false,false,false")]) 1309 ld%U1%V1\\t%0,%1
1310 st%U0%V0\\t%1,%0"
1311 [(set_attr "type" "move,move,move,move,load,store,store,load,store")
1312 (set_attr "predicable" "no,no,yes,yes,no,no,no,no,no")
1313 (set_attr "length" "*,*,4,*,*,*,*,*,*")
1314 (set_attr "iscompact" "true,true_limm,false,false,true,true,false,false,false")])
1169 1315
1170 (define_expand "movdf" 1316 (define_expand "movdf"
1171 [(set (match_operand:DF 0 "move_dest_operand" "") 1317 [(set (match_operand:DF 0 "move_dest_operand" "")
1172 (match_operand:DF 1 "general_operand" ""))] 1318 (match_operand:DF 1 "general_operand" ""))]
1173 "" 1319 ""
1281 [(plus:SI (match_operand:SI 1 "register_operand" "0,0") 1427 [(plus:SI (match_operand:SI 1 "register_operand" "0,0")
1282 (match_operand:SI 2 "nonmemory_operand" "rCm2,Cal"))])) 1428 (match_operand:SI 2 "nonmemory_operand" "rCm2,Cal"))]))
1283 (set (match_operand:SI 0 "dest_reg_operand" "=r,r") 1429 (set (match_operand:SI 0 "dest_reg_operand" "=r,r")
1284 (plus:SI (match_dup 1) (match_dup 2)))] 1430 (plus:SI (match_dup 1) (match_dup 2)))]
1285 "" 1431 ""
1286 "ldb.a%V4 %3,[%0,%S2]" 1432 "ldb.a%V4 %3,[%0,%2]"
1287 [(set_attr "type" "load,load") 1433 [(set_attr "type" "load,load")
1288 (set_attr "length" "4,8")]) 1434 (set_attr "length" "4,8")])
1289 1435
1290 (define_insn "*load_zeroextendqisi_update" 1436 (define_insn "*load_zeroextendqisi_update"
1291 [(set (match_operand:SI 3 "dest_reg_operand" "=r,r") 1437 [(set (match_operand:SI 3 "dest_reg_operand" "=r,r")
1293 [(plus:SI (match_operand:SI 1 "register_operand" "0,0") 1439 [(plus:SI (match_operand:SI 1 "register_operand" "0,0")
1294 (match_operand:SI 2 "nonmemory_operand" "rCm2,Cal"))]))) 1440 (match_operand:SI 2 "nonmemory_operand" "rCm2,Cal"))])))
1295 (set (match_operand:SI 0 "dest_reg_operand" "=r,r") 1441 (set (match_operand:SI 0 "dest_reg_operand" "=r,r")
1296 (plus:SI (match_dup 1) (match_dup 2)))] 1442 (plus:SI (match_dup 1) (match_dup 2)))]
1297 "" 1443 ""
1298 "ldb.a%V4 %3,[%0,%S2]" 1444 "ldb.a%V4 %3,[%0,%2]"
1299 [(set_attr "type" "load,load") 1445 [(set_attr "type" "load,load")
1300 (set_attr "length" "4,8")]) 1446 (set_attr "length" "4,8")])
1301 1447
1302 (define_insn "*load_signextendqisi_update" 1448 (define_insn "*load_signextendqisi_update"
1303 [(set (match_operand:SI 3 "dest_reg_operand" "=r,r") 1449 [(set (match_operand:SI 3 "dest_reg_operand" "=r,r")
1305 [(plus:SI (match_operand:SI 1 "register_operand" "0,0") 1451 [(plus:SI (match_operand:SI 1 "register_operand" "0,0")
1306 (match_operand:SI 2 "nonmemory_operand" "rCm2,Cal"))]))) 1452 (match_operand:SI 2 "nonmemory_operand" "rCm2,Cal"))])))
1307 (set (match_operand:SI 0 "dest_reg_operand" "=r,r") 1453 (set (match_operand:SI 0 "dest_reg_operand" "=r,r")
1308 (plus:SI (match_dup 1) (match_dup 2)))] 1454 (plus:SI (match_dup 1) (match_dup 2)))]
1309 "" 1455 ""
1310 "ldb.x.a%V4 %3,[%0,%S2]" 1456 "ldb.x.a%V4 %3,[%0,%2]"
1311 [(set_attr "type" "load,load") 1457 [(set_attr "type" "load,load")
1312 (set_attr "length" "4,8")]) 1458 (set_attr "length" "4,8")])
1313 1459
1314 (define_insn "*storeqi_update" 1460 (define_insn "*storeqi_update"
1315 [(set (match_operator:QI 4 "any_mem_operand" 1461 [(set (match_operator:QI 4 "any_mem_operand"
1331 [(plus:SI (match_operand:SI 1 "register_operand" "0,0") 1477 [(plus:SI (match_operand:SI 1 "register_operand" "0,0")
1332 (match_operand:SI 2 "nonmemory_operand" "rCm2,Cal"))])) 1478 (match_operand:SI 2 "nonmemory_operand" "rCm2,Cal"))]))
1333 (set (match_operand:SI 0 "dest_reg_operand" "=w,w") 1479 (set (match_operand:SI 0 "dest_reg_operand" "=w,w")
1334 (plus:SI (match_dup 1) (match_dup 2)))] 1480 (plus:SI (match_dup 1) (match_dup 2)))]
1335 "" 1481 ""
1336 "ld%_.a%V4 %3,[%0,%S2]" 1482 "ld%_.a%V4 %3,[%0,%2]"
1337 [(set_attr "type" "load,load") 1483 [(set_attr "type" "load,load")
1338 (set_attr "length" "4,8")]) 1484 (set_attr "length" "4,8")])
1339 1485
1340 (define_insn "*load_zeroextendhisi_update" 1486 (define_insn "*load_zeroextendhisi_update"
1341 [(set (match_operand:SI 3 "dest_reg_operand" "=r,r") 1487 [(set (match_operand:SI 3 "dest_reg_operand" "=r,r")
1343 [(plus:SI (match_operand:SI 1 "register_operand" "0,0") 1489 [(plus:SI (match_operand:SI 1 "register_operand" "0,0")
1344 (match_operand:SI 2 "nonmemory_operand" "rCm2,Cal"))]))) 1490 (match_operand:SI 2 "nonmemory_operand" "rCm2,Cal"))])))
1345 (set (match_operand:SI 0 "dest_reg_operand" "=r,r") 1491 (set (match_operand:SI 0 "dest_reg_operand" "=r,r")
1346 (plus:SI (match_dup 1) (match_dup 2)))] 1492 (plus:SI (match_dup 1) (match_dup 2)))]
1347 "" 1493 ""
1348 "ld%_.a%V4 %3,[%0,%S2]" 1494 "ld%_.a%V4 %3,[%0,%2]"
1349 [(set_attr "type" "load,load") 1495 [(set_attr "type" "load,load")
1350 (set_attr "length" "4,8")]) 1496 (set_attr "length" "4,8")])
1351 1497
1352 ;; Note: no 16-bit variant for this instruction 1498 ;; Note: no 16-bit variant for this instruction
1353 (define_insn "*load_signextendhisi_update" 1499 (define_insn "*load_signextendhisi_update"
1356 [(plus:SI (match_operand:SI 1 "register_operand" "0,0") 1502 [(plus:SI (match_operand:SI 1 "register_operand" "0,0")
1357 (match_operand:SI 2 "nonmemory_operand" "rCm2,Cal"))]))) 1503 (match_operand:SI 2 "nonmemory_operand" "rCm2,Cal"))])))
1358 (set (match_operand:SI 0 "dest_reg_operand" "=w,w") 1504 (set (match_operand:SI 0 "dest_reg_operand" "=w,w")
1359 (plus:SI (match_dup 1) (match_dup 2)))] 1505 (plus:SI (match_dup 1) (match_dup 2)))]
1360 "" 1506 ""
1361 "ld%_.x.a%V4 %3,[%0,%S2]" 1507 "ld%_.x.a%V4 %3,[%0,%2]"
1362 [(set_attr "type" "load,load") 1508 [(set_attr "type" "load,load")
1363 (set_attr "length" "4,8")]) 1509 (set_attr "length" "4,8")])
1364 1510
1365 (define_insn "*storehi_update" 1511 (define_insn "*storehi_update"
1366 [(set (match_operator:HI 4 "any_mem_operand" 1512 [(set (match_operator:HI 4 "any_mem_operand"
1381 [(plus:SI (match_operand:SI 1 "register_operand" "0,0") 1527 [(plus:SI (match_operand:SI 1 "register_operand" "0,0")
1382 (match_operand:SI 2 "nonmemory_operand" "rCm2,Cal"))])) 1528 (match_operand:SI 2 "nonmemory_operand" "rCm2,Cal"))]))
1383 (set (match_operand:SI 0 "dest_reg_operand" "=w,w") 1529 (set (match_operand:SI 0 "dest_reg_operand" "=w,w")
1384 (plus:SI (match_dup 1) (match_dup 2)))] 1530 (plus:SI (match_dup 1) (match_dup 2)))]
1385 "" 1531 ""
1386 "ld.a%V4 %3,[%0,%S2]" 1532 "ld.a%V4 %3,[%0,%2]"
1387 [(set_attr "type" "load,load") 1533 [(set_attr "type" "load,load")
1388 (set_attr "length" "4,8")]) 1534 (set_attr "length" "4,8")])
1389 1535
1390 (define_insn "*storesi_update" 1536 (define_insn "*storesi_update"
1391 [(set (match_operator:SI 4 "any_mem_operand" 1537 [(set (match_operator:SI 4 "any_mem_operand"
1405 [(plus:SI (match_operand:SI 1 "register_operand" "0,0") 1551 [(plus:SI (match_operand:SI 1 "register_operand" "0,0")
1406 (match_operand:SI 2 "nonmemory_operand" "rCm2,Cal"))])) 1552 (match_operand:SI 2 "nonmemory_operand" "rCm2,Cal"))]))
1407 (set (match_operand:SI 0 "dest_reg_operand" "=w,w") 1553 (set (match_operand:SI 0 "dest_reg_operand" "=w,w")
1408 (plus:SI (match_dup 1) (match_dup 2)))] 1554 (plus:SI (match_dup 1) (match_dup 2)))]
1409 "" 1555 ""
1410 "ld.a%V4 %3,[%0,%S2]" 1556 "ld.a%V4 %3,[%0,%2]"
1411 [(set_attr "type" "load,load") 1557 [(set_attr "type" "load,load")
1412 (set_attr "length" "4,8")]) 1558 (set_attr "length" "4,8")])
1413 1559
1414 (define_insn "*storesf_update" 1560 (define_insn "*storesf_update"
1415 [(set (match_operator:SF 4 "any_mem_operand" 1561 [(set (match_operator:SF 4 "any_mem_operand"
1473 /* ??? might be good for speed on ARC600 too, *if* properly scheduled. */ 1619 /* ??? might be good for speed on ARC600 too, *if* properly scheduled. */
1474 if ((optimize_size && (!TARGET_ARC600_FAMILY)) 1620 if ((optimize_size && (!TARGET_ARC600_FAMILY))
1475 && rtx_equal_p (operands[1], constm1_rtx) 1621 && rtx_equal_p (operands[1], constm1_rtx)
1476 && GET_CODE (operands[3]) == LTU) 1622 && GET_CODE (operands[3]) == LTU)
1477 return "sbc.cs %0,%0,%0"; 1623 return "sbc.cs %0,%0,%0";
1478 return "mov.%d3 %0,%S1"; 1624 return "mov.%d3 %0,%1";
1479 } 1625 }
1480 [(set_attr "type" "cmove,cmove") 1626 [(set_attr "type" "cmove,cmove")
1481 (set_attr "length" "4,8")]) 1627 (set_attr "length" "4,8")])
1482 1628
1483 ;; When there's a mask of a single bit, and then a compare to 0 or 1, 1629 ;; When there's a mask of a single bit, and then a compare to 0 or 1,
1634 1780
1635 (define_expand "zero_extendqihi2" 1781 (define_expand "zero_extendqihi2"
1636 [(set (match_operand:HI 0 "dest_reg_operand" "") 1782 [(set (match_operand:HI 0 "dest_reg_operand" "")
1637 (zero_extend:HI (match_operand:QI 1 "nonvol_nonimm_operand" "")))] 1783 (zero_extend:HI (match_operand:QI 1 "nonvol_nonimm_operand" "")))]
1638 "" 1784 ""
1639 "if (prepare_extend_operands (operands, ZERO_EXTEND, HImode)) DONE;" 1785 ""
1640 ) 1786 )
1641 1787
1642 (define_insn "*zero_extendqisi2_ac" 1788 (define_insn "*zero_extendqisi2_ac"
1643 [(set (match_operand:SI 0 "dest_reg_operand" "=Rcq,Rcq#q,Rcw,w,qRcq,!*x,r,r") 1789 [(set (match_operand:SI 0 "dest_reg_operand" "=Rcq,Rcq#q,Rcw,w,qRcq,!*x,r,r")
1644 (zero_extend:SI (match_operand:QI 1 "nonvol_nonimm_operand" "0,Rcq#q,0,c,T,Usd,Ucm,m")))] 1790 (zero_extend:SI (match_operand:QI 1 "nonvol_nonimm_operand" "0,Rcq#q,0,c,T,Usd,Ucm,m")))]
1658 1804
1659 (define_expand "zero_extendqisi2" 1805 (define_expand "zero_extendqisi2"
1660 [(set (match_operand:SI 0 "dest_reg_operand" "") 1806 [(set (match_operand:SI 0 "dest_reg_operand" "")
1661 (zero_extend:SI (match_operand:QI 1 "nonvol_nonimm_operand" "")))] 1807 (zero_extend:SI (match_operand:QI 1 "nonvol_nonimm_operand" "")))]
1662 "" 1808 ""
1663 "if (prepare_extend_operands (operands, ZERO_EXTEND, SImode)) DONE;" 1809 ""
1664 ) 1810 )
1665 1811
1666 (define_insn "*zero_extendhisi2_i" 1812 (define_insn "*zero_extendhisi2_i"
1667 [(set (match_operand:SI 0 "dest_reg_operand" "=Rcq,q,Rcw,w,!x,Rcqq,r,r") 1813 [(set (match_operand:SI 0 "dest_reg_operand" "=Rcq,q,Rcw,w,!x,Rcqq,r,r")
1668 (zero_extend:SI (match_operand:HI 1 "nonvol_nonimm_operand" "0,q,0,c,Usd,T,Ucm,m")))] 1814 (zero_extend:SI (match_operand:HI 1 "nonvol_nonimm_operand" "0,q,0,c,Usd,T,Ucm,m")))]
1683 1829
1684 (define_expand "zero_extendhisi2" 1830 (define_expand "zero_extendhisi2"
1685 [(set (match_operand:SI 0 "dest_reg_operand" "") 1831 [(set (match_operand:SI 0 "dest_reg_operand" "")
1686 (zero_extend:SI (match_operand:HI 1 "nonvol_nonimm_operand" "")))] 1832 (zero_extend:SI (match_operand:HI 1 "nonvol_nonimm_operand" "")))]
1687 "" 1833 ""
1688 "if (prepare_extend_operands (operands, ZERO_EXTEND, SImode)) DONE;" 1834 ""
1689 ) 1835 )
1690 1836
1691 ;; Sign extension instructions. 1837 ;; Sign extension instructions.
1692 1838
1693 (define_insn "*extendqihi2_i" 1839 (define_insn "*extendqihi2_i"
1706 1852
1707 (define_expand "extendqihi2" 1853 (define_expand "extendqihi2"
1708 [(set (match_operand:HI 0 "dest_reg_operand" "") 1854 [(set (match_operand:HI 0 "dest_reg_operand" "")
1709 (sign_extend:HI (match_operand:QI 1 "nonvol_nonimm_operand" "")))] 1855 (sign_extend:HI (match_operand:QI 1 "nonvol_nonimm_operand" "")))]
1710 "" 1856 ""
1711 "if (prepare_extend_operands (operands, SIGN_EXTEND, HImode)) DONE;" 1857 ""
1712 ) 1858 )
1713 1859
1714 (define_insn "*extendqisi2_ac" 1860 (define_insn "*extendqisi2_ac"
1715 [(set (match_operand:SI 0 "dest_reg_operand" "=Rcqq,w,r,r") 1861 [(set (match_operand:SI 0 "dest_reg_operand" "=Rcqq,w,r,r")
1716 (sign_extend:SI (match_operand:QI 1 "nonvol_nonimm_operand" "Rcqq,c,Uex,m")))] 1862 (sign_extend:SI (match_operand:QI 1 "nonvol_nonimm_operand" "Rcqq,c,Uex,m")))]
1726 1872
1727 (define_expand "extendqisi2" 1873 (define_expand "extendqisi2"
1728 [(set (match_operand:SI 0 "dest_reg_operand" "") 1874 [(set (match_operand:SI 0 "dest_reg_operand" "")
1729 (sign_extend:SI (match_operand:QI 1 "nonvol_nonimm_operand" "")))] 1875 (sign_extend:SI (match_operand:QI 1 "nonvol_nonimm_operand" "")))]
1730 "" 1876 ""
1731 "if (prepare_extend_operands (operands, SIGN_EXTEND, SImode)) DONE;" 1877 ""
1732 ) 1878 )
1733 1879
1734 (define_insn "*extendhisi2_i" 1880 (define_insn "*extendhisi2_i"
1735 [(set (match_operand:SI 0 "dest_reg_operand" "=Rcqq,w,Rcqq,r,r") 1881 [(set (match_operand:SI 0 "dest_reg_operand" "=Rcqq,w,Rcqq,r,r")
1736 (sign_extend:SI (match_operand:HI 1 "nonvol_nonimm_operand" "Rcqq,c,Ucd,Uex,m")))] 1882 (sign_extend:SI (match_operand:HI 1 "nonvol_nonimm_operand" "Rcqq,c,Ucd,Uex,m")))]
1747 1893
1748 (define_expand "extendhisi2" 1894 (define_expand "extendhisi2"
1749 [(set (match_operand:SI 0 "dest_reg_operand" "") 1895 [(set (match_operand:SI 0 "dest_reg_operand" "")
1750 (sign_extend:SI (match_operand:HI 1 "nonvol_nonimm_operand" "")))] 1896 (sign_extend:SI (match_operand:HI 1 "nonvol_nonimm_operand" "")))]
1751 "" 1897 ""
1752 "if (prepare_extend_operands (operands, SIGN_EXTEND, SImode)) DONE;" 1898 ""
1753 ) 1899 )
1754 1900
1755 ;; Unary arithmetic insns 1901 ;; Unary arithmetic insns
1756 1902
1757 ;; We allow constant operands to enable late constant propagation, but it is 1903 ;; We allow constant operands to enable late constant propagation, but it is
2640 "" 2786 ""
2641 "if (flag_pic && arc_raw_symbolic_reference_mentioned_p (operands[2], false)) 2787 "if (flag_pic && arc_raw_symbolic_reference_mentioned_p (operands[2], false))
2642 { 2788 {
2643 operands[2]=force_reg(SImode, operands[2]); 2789 operands[2]=force_reg(SImode, operands[2]);
2644 } 2790 }
2645 else if (!TARGET_NO_SDATA_SET && small_data_pattern (operands[2], Pmode))
2646 {
2647 operands[2] = force_reg (SImode, arc_rewrite_small_data (operands[2]));
2648 }
2649
2650 ") 2791 ")
2651 2792
2652 (define_expand "adddi3" 2793 (define_expand "adddi3"
2653 [(parallel [(set (match_operand:DI 0 "dest_reg_operand" "") 2794 [(parallel [(set (match_operand:DI 0 "dest_reg_operand" "")
2654 (plus:DI (match_operand:DI 1 "register_operand" "") 2795 (plus:DI (match_operand:DI 1 "register_operand" "")
2848 operands[1] = force_reg (SImode, operands[1]); 2989 operands[1] = force_reg (SImode, operands[1]);
2849 c = 2; 2990 c = 2;
2850 } 2991 }
2851 if (flag_pic && arc_raw_symbolic_reference_mentioned_p (operands[c], false)) 2992 if (flag_pic && arc_raw_symbolic_reference_mentioned_p (operands[c], false))
2852 operands[c] = force_reg (SImode, operands[c]); 2993 operands[c] = force_reg (SImode, operands[c]);
2853 else if (!TARGET_NO_SDATA_SET && small_data_pattern (operands[c], Pmode))
2854 operands[c] = force_reg (SImode, arc_rewrite_small_data (operands[c]));
2855 }") 2994 }")
2856 2995
2857 ; the casesi expander might generate a sub of zero, so we have to recognize it. 2996 ; the casesi expander might generate a sub of zero, so we have to recognize it.
2858 ; combine should make such an insn go away. 2997 ; combine should make such an insn go away.
2859 (define_insn_and_split "subsi3_insn" 2998 (define_insn_and_split "subsi3_insn"
3032 [(set (reg:CC CC_REG) (compare:CC (match_dup 1) (match_dup 2))) 3171 [(set (reg:CC CC_REG) (compare:CC (match_dup 1) (match_dup 2)))
3033 (set (match_dup 0) (minus:SI (match_dup 1) (match_dup 2)))]) 3172 (set (match_dup 0) (minus:SI (match_dup 1) (match_dup 2)))])
3034 (set (match_dup 3) (match_dup 4))]) 3173 (set (match_dup 3) (match_dup 4))])
3035 3174
3036 (define_insn "*add_n" 3175 (define_insn "*add_n"
3037 [(set (match_operand:SI 0 "dest_reg_operand" "=Rcqq,Rcw,W,W,w,w") 3176 [(set (match_operand:SI 0 "dest_reg_operand" "=q,r,r")
3038 (plus:SI (ashift:SI (match_operand:SI 1 "register_operand" "Rcqq,c,c,c,c,c") 3177 (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "q,r,r")
3039 (match_operand:SI 2 "_1_2_3_operand" "")) 3178 (match_operand:SI 2 "_2_4_8_operand" ""))
3040 (match_operand:SI 3 "nonmemory_operand" "0,0,c,?Cal,?c,??Cal")))] 3179 (match_operand:SI 3 "nonmemory_operand" "0,r,Csz")))]
3041 "" 3180 ""
3042 "add%c2%? %0,%3,%1%&" 3181 "add%z2%?\\t%0,%3,%1%&"
3043 [(set_attr "type" "shift") 3182 [(set_attr "type" "shift")
3044 (set_attr "length" "*,4,4,8,4,8") 3183 (set_attr "length" "*,4,8")
3045 (set_attr "predicable" "yes,yes,no,no,no,no") 3184 (set_attr "predicable" "yes,no,no")
3046 (set_attr "cond" "canuse,canuse,nocond,nocond,nocond,nocond") 3185 (set_attr "cond" "canuse,nocond,nocond")
3047 (set_attr "iscompact" "maybe,false,false,false,false,false")]) 3186 (set_attr "iscompact" "maybe,false,false")])
3048
3049 (define_insn "*add_n"
3050 [(set (match_operand:SI 0 "dest_reg_operand" "=Rcqq,Rcw,W,W,w,w")
3051 (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "Rcqq,c,c,c,c,c")
3052 (match_operand:SI 2 "_2_4_8_operand" ""))
3053 (match_operand:SI 3 "nonmemory_operand" "0,0,c,?Cal,?c,??Cal")))]
3054 ""
3055 "add%z2%? %0,%3,%1%&"
3056 [(set_attr "type" "shift")
3057 (set_attr "length" "*,4,4,8,4,8")
3058 (set_attr "predicable" "yes,yes,no,no,no,no")
3059 (set_attr "cond" "canuse,canuse,nocond,nocond,nocond,nocond")
3060 (set_attr "iscompact" "maybe,false,false,false,false,false")])
3061 3187
3062 ;; N.B. sub[123] has the operands of the MINUS in the opposite order from 3188 ;; N.B. sub[123] has the operands of the MINUS in the opposite order from
3063 ;; what synth_mult likes. 3189 ;; what synth_mult likes.
3064 (define_insn "*sub_n" 3190 (define_insn "*sub_n"
3065 [(set (match_operand:SI 0 "dest_reg_operand" "=Rcw,w,w") 3191 [(set (match_operand:SI 0 "dest_reg_operand" "=Rcw,w,w")
3138 (match_operand:SI 2 "nonmemory_operand" "cL,cL,c"))) ) ] 3264 (match_operand:SI 2 "nonmemory_operand" "cL,cL,c"))) ) ]
3139 "" 3265 ""
3140 "@ 3266 "@
3141 bset%? %0,%1,%2 ;;peep2, constr 1 3267 bset%? %0,%1,%2 ;;peep2, constr 1
3142 bset %0,%1,%2 ;;peep2, constr 2 3268 bset %0,%1,%2 ;;peep2, constr 2
3143 bset %0,%S1,%2 ;;peep2, constr 3" 3269 bset %0,%1,%2 ;;peep2, constr 3"
3144 [(set_attr "length" "4,4,8") 3270 [(set_attr "length" "4,4,8")
3145 (set_attr "predicable" "yes,no,no") 3271 (set_attr "predicable" "yes,no,no")
3146 (set_attr "cond" "canuse,nocond,nocond")] 3272 (set_attr "cond" "canuse,nocond,nocond")]
3147 ) 3273 )
3148 3274
3154 (match_operand:SI 2 "nonmemory_operand" "cL,cL,c"))) ) ] 3280 (match_operand:SI 2 "nonmemory_operand" "cL,cL,c"))) ) ]
3155 "" 3281 ""
3156 "@ 3282 "@
3157 bxor%? %0,%1,%2 3283 bxor%? %0,%1,%2
3158 bxor %0,%1,%2 3284 bxor %0,%1,%2
3159 bxor %0,%S1,%2" 3285 bxor %0,%1,%2"
3160 [(set_attr "length" "4,4,8") 3286 [(set_attr "length" "4,4,8")
3161 (set_attr "predicable" "yes,no,no") 3287 (set_attr "predicable" "yes,no,no")
3162 (set_attr "cond" "canuse,nocond,nocond")] 3288 (set_attr "cond" "canuse,nocond,nocond")]
3163 ) 3289 )
3164 3290
3170 (match_operand:SI 1 "nonmemory_operand" "0,c,Cal")))] 3296 (match_operand:SI 1 "nonmemory_operand" "0,c,Cal")))]
3171 "" 3297 ""
3172 "@ 3298 "@
3173 bclr%? %0,%1,%2 3299 bclr%? %0,%1,%2
3174 bclr %0,%1,%2 3300 bclr %0,%1,%2
3175 bclr %0,%S1,%2" 3301 bclr %0,%1,%2"
3176 [(set_attr "length" "4,4,8") 3302 [(set_attr "length" "4,4,8")
3177 (set_attr "predicable" "yes,no,no") 3303 (set_attr "predicable" "yes,no,no")
3178 (set_attr "cond" "canuse,nocond,nocond")] 3304 (set_attr "cond" "canuse,nocond,nocond")]
3179 ) 3305 )
3180 3306
3186 (plus:SI (match_operand:SI 2 "nonmemory_operand" "rL,rL,r") 3312 (plus:SI (match_operand:SI 2 "nonmemory_operand" "rL,rL,r")
3187 (const_int 1))) 3313 (const_int 1)))
3188 (const_int -1))))] 3314 (const_int -1))))]
3189 "" 3315 ""
3190 "@ 3316 "@
3191 bmsk%? %0,%S1,%2 3317 bmsk%? %0,%1,%2
3192 bmsk %0,%1,%2 3318 bmsk %0,%1,%2
3193 bmsk %0,%S1,%2" 3319 bmsk %0,%1,%2"
3194 [(set_attr "length" "4,4,8") 3320 [(set_attr "length" "4,4,8")
3195 (set_attr "predicable" "yes,no,no") 3321 (set_attr "predicable" "yes,no,no")
3196 (set_attr "cond" "canuse,nocond,nocond")] 3322 (set_attr "cond" "canuse,nocond,nocond")]
3197 ) 3323 )
3198 3324
3205 (and:SI (match_operand:SI 1 "nonimmediate_operand" "") 3331 (and:SI (match_operand:SI 1 "nonimmediate_operand" "")
3206 (match_operand:SI 2 "nonmemory_operand" "")))] 3332 (match_operand:SI 2 "nonmemory_operand" "")))]
3207 "" 3333 ""
3208 "if (!satisfies_constraint_Cux (operands[2])) 3334 "if (!satisfies_constraint_Cux (operands[2]))
3209 operands[1] = force_reg (SImode, operands[1]); 3335 operands[1] = force_reg (SImode, operands[1]);
3210 else if (!TARGET_NO_SDATA_SET && small_data_pattern (operands[1], Pmode)) 3336 ")
3211 operands[1] = arc_rewrite_small_data (operands[1]);")
3212 3337
3213 (define_insn "andsi3_i" 3338 (define_insn "andsi3_i"
3214 [(set (match_operand:SI 0 "dest_reg_operand" "=Rcqq,Rcq,Rcqq,Rcqq,Rcqq,Rcw,Rcw, Rcw,Rcw,Rcw,Rcw, w, w, w, w,Rrq,w,Rcw, w,W") 3339 [(set (match_operand:SI 0 "dest_reg_operand" "=Rcqq,Rcq,Rcqq,Rcqq,Rcqq,Rcw,Rcw, Rcw,Rcw,Rcw,Rcw, w, w, w, w,Rrq,w,Rcw, w,W")
3215 (and:SI (match_operand:SI 1 "nonimmediate_operand" "%0,Rcq, 0, 0,Rcqq, 0, c, 0, 0, 0, 0, c, c, c, c,Rrq,0, 0, c,o") 3340 (and:SI (match_operand:SI 1 "nonimmediate_operand" "%0,Rcq, 0, 0,Rcqq, 0, c, 0, 0, 0, 0, c, c, c, c,Rrq,0, 0, c,o")
3216 (match_operand:SI 2 "nonmemory_operand" "Rcqq, 0, C1p, Ccp, Cux, cL, 0,C2pC1p,Ccp,CnL, I,Lc,C2pC1p,Ccp,CnL,Cbf,I,Cal,Cal,Cux")))] 3341 (match_operand:SI 2 "nonmemory_operand" "Rcqq, 0, C1p, Ccp, Cux, cL, 0,C2pC1p,Ccp,CnL, I,Lc,C2pC1p,Ccp,CnL,Cbf,I,Cal,Cal,Cux")))]
3300 "" 3425 ""
3301 "@ 3426 "@
3302 bic%? %0, %2, %1%& ;;constraint 0 3427 bic%? %0, %2, %1%& ;;constraint 0
3303 bic%? %0,%2,%1 ;;constraint 1 3428 bic%? %0,%2,%1 ;;constraint 1
3304 bic %0,%2,%1 ;;constraint 2, FIXME: will it ever get generated ??? 3429 bic %0,%2,%1 ;;constraint 2, FIXME: will it ever get generated ???
3305 bic%? %0,%2,%S1 ;;constraint 3, FIXME: will it ever get generated ??? 3430 bic%? %0,%2,%1 ;;constraint 3, FIXME: will it ever get generated ???
3306 bic %0,%2,%1 ;;constraint 4 3431 bic %0,%2,%1 ;;constraint 4
3307 bic %0,%2,%S1 ;;constraint 5, FIXME: will it ever get generated ??? 3432 bic %0,%2,%1 ;;constraint 5, FIXME: will it ever get generated ???
3308 bic %0,%S2,%1 ;;constraint 6" 3433 bic %0,%2,%1 ;;constraint 6"
3309 [(set_attr "length" "*,4,4,8,4,8,8") 3434 [(set_attr "length" "*,4,4,8,4,8,8")
3310 (set_attr "iscompact" "maybe, false, false, false, false, false, false") 3435 (set_attr "iscompact" "maybe, false, false, false, false, false, false")
3311 (set_attr "predicable" "no,yes,no,yes,no,no,no") 3436 (set_attr "predicable" "no,yes,no,yes,no,no,no")
3312 (set_attr "cond" "canuse,canuse,canuse_limm,canuse,nocond,nocond,nocond")]) 3437 (set_attr "cond" "canuse,canuse,canuse_limm,canuse,nocond,nocond,nocond")])
3313 3438
3473 ; is defined in an external symbol, as we don't have special relocations 3598 ; is defined in an external symbol, as we don't have special relocations
3474 ; to truncate a symbol in a u6 immediate; but that's rather exotic, so only 3599 ; to truncate a symbol in a u6 immediate; but that's rather exotic, so only
3475 ; provide one alternatice for this, without condexec support. 3600 ; provide one alternatice for this, without condexec support.
3476 (define_insn "*ashlsi3_insn" 3601 (define_insn "*ashlsi3_insn"
3477 [(set (match_operand:SI 0 "dest_reg_operand" "=Rcq,Rcqq,Rcqq,Rcw, w, w") 3602 [(set (match_operand:SI 0 "dest_reg_operand" "=Rcq,Rcqq,Rcqq,Rcw, w, w")
3478 (ashift:SI (match_operand:SI 1 "nonmemory_operand" "!0,Rcqq, 0, 0, c,cCal") 3603 (ashift:SI (match_operand:SI 1 "nonmemory_operand" "!0,Rcqq, 0, 0, c,cCsz")
3479 (match_operand:SI 2 "nonmemory_operand" "K, K,RcqqM, cL,cL,cCal")))] 3604 (match_operand:SI 2 "nonmemory_operand" "K, K,RcqqM, cL,cL,cCal")))]
3480 "TARGET_BARREL_SHIFTER 3605 "TARGET_BARREL_SHIFTER
3481 && (register_operand (operands[1], SImode) 3606 && (register_operand (operands[1], SImode)
3482 || register_operand (operands[2], SImode))" 3607 || register_operand (operands[2], SImode))"
3483 "asl%? %0,%1,%2%&" 3608 "asl%? %0,%1,%2%&"
3486 (set_attr "predicable" "no,no,no,yes,no,no") 3611 (set_attr "predicable" "no,no,no,yes,no,no")
3487 (set_attr "cond" "canuse,nocond,canuse,canuse,nocond,nocond")]) 3612 (set_attr "cond" "canuse,nocond,canuse,canuse,nocond,nocond")])
3488 3613
3489 (define_insn "*ashrsi3_insn" 3614 (define_insn "*ashrsi3_insn"
3490 [(set (match_operand:SI 0 "dest_reg_operand" "=Rcq,Rcqq,Rcqq,Rcw, w, w") 3615 [(set (match_operand:SI 0 "dest_reg_operand" "=Rcq,Rcqq,Rcqq,Rcw, w, w")
3491 (ashiftrt:SI (match_operand:SI 1 "nonmemory_operand" "!0,Rcqq, 0, 0, c,cCal") 3616 (ashiftrt:SI (match_operand:SI 1 "nonmemory_operand" "!0,Rcqq, 0, 0, c,cCsz")
3492 (match_operand:SI 2 "nonmemory_operand" "K, K,RcqqM, cL,cL,cCal")))] 3617 (match_operand:SI 2 "nonmemory_operand" "K, K,RcqqM, cL,cL,cCal")))]
3493 "TARGET_BARREL_SHIFTER 3618 "TARGET_BARREL_SHIFTER
3494 && (register_operand (operands[1], SImode) 3619 && (register_operand (operands[1], SImode)
3495 || register_operand (operands[2], SImode))" 3620 || register_operand (operands[2], SImode))"
3496 "asr%? %0,%1,%2%&" 3621 "asr%? %0,%1,%2%&"
3513 (set_attr "predicable" "no,no,no,yes,no,no") 3638 (set_attr "predicable" "no,no,no,yes,no,no")
3514 (set_attr "cond" "canuse,nocond,canuse,canuse,nocond,nocond")]) 3639 (set_attr "cond" "canuse,nocond,canuse,canuse,nocond,nocond")])
3515 3640
3516 (define_insn "rotrsi3" 3641 (define_insn "rotrsi3"
3517 [(set (match_operand:SI 0 "dest_reg_operand" "=Rcw, w, w") 3642 [(set (match_operand:SI 0 "dest_reg_operand" "=Rcw, w, w")
3518 (rotatert:SI (match_operand:SI 1 "register_operand" " 0,cL,cCal") 3643 (rotatert:SI (match_operand:SI 1 "register_operand" " 0,cL,cCsz")
3519 (match_operand:SI 2 "nonmemory_operand" "cL,cL,cCal")))] 3644 (match_operand:SI 2 "nonmemory_operand" "cL,cL,cCal")))]
3520 "TARGET_BARREL_SHIFTER" 3645 "TARGET_BARREL_SHIFTER"
3521 "ror%? %0,%1,%2" 3646 "ror%? %0,%1,%2"
3522 [(set_attr "type" "shift,shift,shift") 3647 [(set_attr "type" "shift,shift,shift")
3523 (set_attr "predicable" "yes,no,no") 3648 (set_attr "predicable" "yes,no,no")
3634 (define_insn "*cmpsi_cc_c_insn" 3759 (define_insn "*cmpsi_cc_c_insn"
3635 [(set (reg:CC_C CC_REG) 3760 [(set (reg:CC_C CC_REG)
3636 (compare:CC_C (match_operand:SI 0 "register_operand" "Rcqq,Rcqq, h, c,Rcqq, c") 3761 (compare:CC_C (match_operand:SI 0 "register_operand" "Rcqq,Rcqq, h, c,Rcqq, c")
3637 (match_operand:SI 1 "nonmemory_operand" "cO, hO,Cm1,cI, Cal,Cal")))] 3762 (match_operand:SI 1 "nonmemory_operand" "cO, hO,Cm1,cI, Cal,Cal")))]
3638 "" 3763 ""
3639 "cmp%? %0,%S1%&" 3764 "cmp%? %0,%1%&"
3640 [(set_attr "type" "compare") 3765 [(set_attr "type" "compare")
3641 (set_attr "iscompact" "true,true,true,false,true_limm,false") 3766 (set_attr "iscompact" "true,true,true,false,true_limm,false")
3642 (set_attr "cond" "set") 3767 (set_attr "cond" "set")
3643 (set_attr "length" "*,*,*,4,*,8") 3768 (set_attr "length" "*,*,*,4,*,8")
3644 (set_attr "cpu_facility" "av1,av2,*,*,*,*")]) 3769 (set_attr "cpu_facility" "av1,av2,*,*,*,*")])
3741 "@ 3866 "@
3742 * current_insn_predicate = 0; return \"sub%?.ne %0,%0,%0%&\"; 3867 * current_insn_predicate = 0; return \"sub%?.ne %0,%0,%0%&\";
3743 * current_insn_predicate = 0; return \"mov%?.ne %0,%1\"; 3868 * current_insn_predicate = 0; return \"mov%?.ne %0,%1\";
3744 * current_insn_predicate = 0; return \"mov%?.ne %0,%1\"; 3869 * current_insn_predicate = 0; return \"mov%?.ne %0,%1\";
3745 mov.ne %0,%1 3870 mov.ne %0,%1
3746 mov.ne %0,%S1" 3871 mov.ne %0,%1"
3747 [(set_attr "type" "cmove") 3872 [(set_attr "type" "cmove")
3748 (set_attr "iscompact" "true,true,true_limm,false,false") 3873 (set_attr "iscompact" "true,true,true_limm,false,false")
3749 (set_attr "length" "2,2,6,4,8") 3874 (set_attr "length" "2,2,6,4,8")
3750 (set_attr "cpu_facility" "*,av2,av2,*,*")]) 3875 (set_attr "cpu_facility" "*,av2,av2,*,*")])
3751 3876
3754 (match_operator 3 "proper_comparison_operator" 3879 (match_operator 3 "proper_comparison_operator"
3755 [(match_operand 2 "cc_register" "Rcc,Rcc") (const_int 0)]) 3880 [(match_operand 2 "cc_register" "Rcc,Rcc") (const_int 0)])
3756 (set (match_operand:SI 0 "dest_reg_operand" "=w,w") 3881 (set (match_operand:SI 0 "dest_reg_operand" "=w,w")
3757 (match_operand:SI 1 "nonmemory_operand" "LRac,?Cal")))] 3882 (match_operand:SI 1 "nonmemory_operand" "LRac,?Cal")))]
3758 "" 3883 ""
3759 "mov.%d3 %0,%S1" 3884 "mov.%d3 %0,%1"
3760 [(set_attr "type" "cmove") 3885 [(set_attr "type" "cmove")
3761 (set_attr "length" "4,8")]) 3886 (set_attr "length" "4,8")])
3762 3887
3763 (define_insn "*commutative_cond_exec" 3888 (define_insn "*commutative_cond_exec"
3764 [(cond_exec 3889 [(cond_exec
4222 && (GET_CODE (callee) == PLUS || arc_is_longcall_p (callee))) 4347 && (GET_CODE (callee) == PLUS || arc_is_longcall_p (callee)))
4223 XEXP (operands[0], 0) = force_reg (Pmode, callee); 4348 XEXP (operands[0], 0) = force_reg (Pmode, callee);
4224 } 4349 }
4225 ") 4350 ")
4226 4351
4227
4228 ; Rcq, which is used in alternative 0, checks for conditional execution. 4352 ; Rcq, which is used in alternative 0, checks for conditional execution.
4229 ; At instruction output time, if it doesn't match and we end up with 4353 ; At instruction output time, if it doesn't match and we end up with
4230 ; alternative 1 ("q"), that means that we can't use the short form. 4354 ; alternative 1 ("q"), that means that we can't use the short form.
4231 (define_insn "*call_i" 4355 (define_insn "*call_i"
4232 [(call (mem:SI (match_operand:SI 0 4356 [(call (mem:SI (match_operand:SI 0
4233 "call_address_operand" "Rcq,q,c,Cbp,Cbr,L,I,Cal")) 4357 "call_address_operand" "Rcq,q,c,Cji,Csc,Cbp,Cbr,L,I,Cal"))
4234 (match_operand 1 "" "")) 4358 (match_operand 1 "" ""))
4235 (clobber (reg:SI 31))] 4359 (clobber (reg:SI 31))]
4236 "" 4360 ""
4237 "@ 4361 "@
4238 jl%!%* [%0]%& 4362 jl%!%* [%0]%&
4239 jl%!%* [%0]%& 4363 jl%!%* [%0]%&
4240 jl%!%* [%0] 4364 jl%!%* [%0]
4365 jli_s %S0
4366 sjli %S0
4241 bl%!%* %P0 4367 bl%!%* %P0
4242 bl%!%* %P0 4368 bl%!%* %P0
4243 jl%!%* %S0 4369 jl%!%* %0
4244 jl%* %S0 4370 jl%* %0
4245 jl%! %S0" 4371 jl%! %0"
4246 [(set_attr "type" "call,call,call,call,call,call,call,call_no_delay_slot") 4372 [(set_attr "type" "call,call,call,call_no_delay_slot,call_no_delay_slot,call,call,call,call,call_no_delay_slot")
4247 (set_attr "iscompact" "maybe,false,*,*,*,*,*,*") 4373 (set_attr "iscompact" "maybe,false,*,true,*,*,*,*,*,*")
4248 (set_attr "predicable" "no,no,yes,yes,no,yes,no,yes") 4374 (set_attr "predicable" "no,no,yes,no,no,yes,no,yes,no,yes")
4249 (set_attr "length" "*,*,4,4,4,4,4,8")]) 4375 (set_attr "length" "*,*,4,2,4,4,4,4,4,8")])
4250 4376
4251 (define_expand "call_value" 4377 (define_expand "call_value"
4252 ;; operand 2 is stack_size_rtx 4378 ;; operand 2 is stack_size_rtx
4253 ;; operand 3 is next_arg_register 4379 ;; operand 3 is next_arg_register
4254 [(parallel [(set (match_operand 0 "dest_reg_operand" "=r") 4380 [(parallel [(set (match_operand 0 "dest_reg_operand" "=r")
4266 if (GET_CODE (callee) != REG 4392 if (GET_CODE (callee) != REG
4267 && (GET_CODE (callee) == PLUS || arc_is_longcall_p (callee))) 4393 && (GET_CODE (callee) == PLUS || arc_is_longcall_p (callee)))
4268 XEXP (operands[1], 0) = force_reg (Pmode, callee); 4394 XEXP (operands[1], 0) = force_reg (Pmode, callee);
4269 }") 4395 }")
4270 4396
4271
4272 ; Rcq, which is used in alternative 0, checks for conditional execution. 4397 ; Rcq, which is used in alternative 0, checks for conditional execution.
4273 ; At instruction output time, if it doesn't match and we end up with 4398 ; At instruction output time, if it doesn't match and we end up with
4274 ; alternative 1 ("q"), that means that we can't use the short form. 4399 ; alternative 1 ("q"), that means that we can't use the short form.
4275 (define_insn "*call_value_i" 4400 (define_insn "*call_value_i"
4276 [(set (match_operand 0 "dest_reg_operand" "=Rcq,q,w, w, w,w,w, w") 4401 [(set (match_operand 0 "dest_reg_operand" "=Rcq,q,w, w, w, w, w,w,w, w")
4277 (call (mem:SI (match_operand:SI 1 4402 (call (mem:SI (match_operand:SI 1
4278 "call_address_operand" "Rcq,q,c,Cbp,Cbr,L,I,Cal")) 4403 "call_address_operand" "Rcq,q,c,Cji,Csc,Cbp,Cbr,L,I,Cal"))
4279 (match_operand 2 "" ""))) 4404 (match_operand 2 "" "")))
4280 (clobber (reg:SI 31))] 4405 (clobber (reg:SI 31))]
4281 "" 4406 ""
4282 "@ 4407 "@
4283 jl%!%* [%1]%& 4408 jl%!%* [%1]%&
4284 jl%!%* [%1]%& 4409 jl%!%* [%1]%&
4285 jl%!%* [%1] 4410 jl%!%* [%1]
4411 jli_s %S1
4412 sjli %S1
4286 bl%!%* %P1;1 4413 bl%!%* %P1;1
4287 bl%!%* %P1;1 4414 bl%!%* %P1;1
4288 jl%!%* %S1 4415 jl%!%* %1
4289 jl%* %S1 4416 jl%* %1
4290 jl%! %S1" 4417 jl%! %1"
4291 [(set_attr "type" "call,call,call,call,call,call,call,call_no_delay_slot") 4418 [(set_attr "type" "call,call,call,call_no_delay_slot,call_no_delay_slot,call,call,call,call,call_no_delay_slot")
4292 (set_attr "iscompact" "maybe,false,*,*,*,*,*,*") 4419 (set_attr "iscompact" "maybe,false,*,true,false,*,*,*,*,*")
4293 (set_attr "predicable" "no,no,yes,yes,no,yes,no,yes") 4420 (set_attr "predicable" "no,no,yes,no,no,yes,no,yes,no,yes")
4294 (set_attr "length" "*,*,4,4,4,4,4,8")]) 4421 (set_attr "length" "*,*,4,2,4,4,4,4,4,8")])
4295 4422
4296 ; There is a bl_s instruction (16 bit opcode branch-and-link), but we can't 4423 ; There is a bl_s instruction (16 bit opcode branch-and-link), but we can't
4297 ; use it for lack of inter-procedural branch shortening. 4424 ; use it for lack of inter-procedural branch shortening.
4298 ; Link-time relaxation would help... 4425 ; Link-time relaxation would help...
4426
4427 (define_insn "trap"
4428 [(trap_if (const_int 1) (const_int 0))]
4429 "!TARGET_ARC600_FAMILY"
4430 "trap_s\\t5"
4431 [(set_attr "type" "misc")
4432 (set_attr "length" "2")])
4299 4433
4300 (define_insn "nop" 4434 (define_insn "nop"
4301 [(const_int 0)] 4435 [(const_int 0)]
4302 "" 4436 ""
4303 "nop%?" 4437 "nop%?"
4309 (define_insn "nopv" 4443 (define_insn "nopv"
4310 [(unspec_volatile [(const_int 0)] VUNSPEC_ARC_NOP)] 4444 [(unspec_volatile [(const_int 0)] VUNSPEC_ARC_NOP)]
4311 "" 4445 ""
4312 "nop%?" 4446 "nop%?"
4313 [(set_attr "type" "misc") 4447 [(set_attr "type" "misc")
4314 (set_attr "iscompact" "true") 4448 (set_attr "iscompact" "maybe")
4315 (set_attr "length" "2")]) 4449 (set_attr "length" "*")])
4316 4450
4317 ;; Special pattern to flush the icache. 4451 (define_insn "blockage"
4318 ;; ??? Not sure what to do here. Some ARC's are known to support this. 4452 [(unspec_volatile [(const_int 0)] VUNSPEC_ARC_BLOCKAGE)]
4319 4453 ""
4320 (define_insn "flush_icache" 4454 ""
4321 [(unspec_volatile [(match_operand:SI 0 "memory_operand" "m")] 0)] 4455 [(set_attr "length" "0")
4322 "" 4456 (set_attr "type" "block")]
4323 "* return \"\";" 4457 )
4324 [(set_attr "type" "misc")])
4325 4458
4326 ;; Split up troublesome insns for better scheduling. 4459 ;; Split up troublesome insns for better scheduling.
4327 4460
4328 ;; Peepholes go at the end. 4461 ;; Peepholes go at the end.
4329 ;;asl followed by add can be replaced by an add{1,2,3} 4462 ;;asl followed by add can be replaced by an add{1,2,3}
4346 ;; newlib/libc/time/mktm_r.c . 4479 ;; newlib/libc/time/mktm_r.c .
4347 4480
4348 (define_peephole2 4481 (define_peephole2
4349 [(set (match_operand:SI 0 "dest_reg_operand" "") 4482 [(set (match_operand:SI 0 "dest_reg_operand" "")
4350 (ashift:SI (match_operand:SI 1 "register_operand" "") 4483 (ashift:SI (match_operand:SI 1 "register_operand" "")
4351 (match_operand:SI 2 "const_int_operand" ""))) 4484 (match_operand:SI 2 "_1_2_3_operand" "")))
4352 (set (match_operand:SI 3 "dest_reg_operand" "") 4485 (set (match_operand:SI 3 "dest_reg_operand" "")
4353 (plus:SI (match_operand:SI 4 "nonmemory_operand" "") 4486 (plus:SI (match_operand:SI 4 "nonmemory_operand" "")
4354 (match_operand:SI 5 "nonmemory_operand" "")))] 4487 (match_operand:SI 5 "nonmemory_operand" "")))]
4355 "(INTVAL (operands[2]) == 1 4488 "(true_regnum (operands[4]) == true_regnum (operands[0])
4356 || INTVAL (operands[2]) == 2
4357 || INTVAL (operands[2]) == 3)
4358 && (true_regnum (operands[4]) == true_regnum (operands[0])
4359 || true_regnum (operands[5]) == true_regnum (operands[0])) 4489 || true_regnum (operands[5]) == true_regnum (operands[0]))
4360 && (peep2_reg_dead_p (2, operands[0]) || (true_regnum (operands[3]) == true_regnum (operands[0])))" 4490 && (peep2_reg_dead_p (2, operands[0])
4491 || (true_regnum (operands[3]) == true_regnum (operands[0])))
4492 && !(optimize_size && satisfies_constraint_I (operands[4]))
4493 && !(optimize_size && satisfies_constraint_I (operands[5]))"
4361 ;; the preparation statements take care to put proper operand in operands[4] 4494 ;; the preparation statements take care to put proper operand in operands[4]
4362 ;; operands[4] will always contain the correct operand. This is added to satisfy commutativity 4495 ;; operands[4] will always contain the correct operand. This is added to satisfy commutativity
4363 [(set (match_dup 3) 4496 [(set (match_dup 3)
4364 (plus:SI (mult:SI (match_dup 1) 4497 (plus:SI (mult:SI (match_dup 1)
4365 (match_dup 2)) 4498 (match_dup 2))
4463 [(set (match_operand:SI 0 "dest_reg_operand" "=w,w") 4596 [(set (match_operand:SI 0 "dest_reg_operand" "=w,w")
4464 (clrsb:SI (match_operand:SI 1 "general_operand" "cL,Cal")))] 4597 (clrsb:SI (match_operand:SI 1 "general_operand" "cL,Cal")))]
4465 "TARGET_NORM" 4598 "TARGET_NORM"
4466 "@ 4599 "@
4467 norm \t%0, %1 4600 norm \t%0, %1
4468 norm \t%0, %S1" 4601 norm \t%0, %1"
4469 [(set_attr "length" "4,8") 4602 [(set_attr "length" "4,8")
4470 (set_attr "type" "two_cycle_core,two_cycle_core")]) 4603 (set_attr "type" "two_cycle_core,two_cycle_core")])
4471 4604
4472 (define_insn "norm_f" 4605 (define_insn "norm_f"
4473 [(set (match_operand:SI 0 "dest_reg_operand" "=w,w") 4606 [(set (match_operand:SI 0 "dest_reg_operand" "=w,w")
4475 (set (reg:CC_ZN CC_REG) 4608 (set (reg:CC_ZN CC_REG)
4476 (compare:CC_ZN (match_dup 1) (const_int 0)))] 4609 (compare:CC_ZN (match_dup 1) (const_int 0)))]
4477 "TARGET_NORM" 4610 "TARGET_NORM"
4478 "@ 4611 "@
4479 norm.f\t%0, %1 4612 norm.f\t%0, %1
4480 norm.f\t%0, %S1" 4613 norm.f\t%0, %1"
4481 [(set_attr "length" "4,8") 4614 [(set_attr "length" "4,8")
4482 (set_attr "type" "two_cycle_core,two_cycle_core")]) 4615 (set_attr "type" "two_cycle_core,two_cycle_core")])
4483 4616
4484 (define_insn_and_split "clrsbhi2" 4617 (define_insn_and_split "clrsbhi2"
4485 [(set (match_operand:HI 0 "dest_reg_operand" "=w,w") 4618 [(set (match_operand:HI 0 "dest_reg_operand" "=w,w")
4495 (zero_extend:SI 4628 (zero_extend:SI
4496 (clrsb:HI (match_operand:HI 1 "general_operand" "cL,Cal"))))] 4629 (clrsb:HI (match_operand:HI 1 "general_operand" "cL,Cal"))))]
4497 "TARGET_NORM" 4630 "TARGET_NORM"
4498 "@ 4631 "@
4499 norm%_ \t%0, %1 4632 norm%_ \t%0, %1
4500 norm%_ \t%0, %S1" 4633 norm%_ \t%0, %1"
4501 [(set_attr "length" "4,8") 4634 [(set_attr "length" "4,8")
4502 (set_attr "type" "two_cycle_core,two_cycle_core")]) 4635 (set_attr "type" "two_cycle_core,two_cycle_core")])
4503 4636
4504 (define_expand "clzsi2" 4637 (define_expand "clzsi2"
4505 [(parallel 4638 [(parallel
4584 (unspec:SI [(match_operand:SI 1 "general_operand" "L,Cal,c")] 4717 (unspec:SI [(match_operand:SI 1 "general_operand" "L,Cal,c")]
4585 UNSPEC_ARC_SWAP))] 4718 UNSPEC_ARC_SWAP))]
4586 "TARGET_SWAP" 4719 "TARGET_SWAP"
4587 "@ 4720 "@
4588 swap \t%0, %1 4721 swap \t%0, %1
4589 swap \t%0, %S1 4722 swap \t%0, %1
4590 swap \t%0, %1" 4723 swap \t%0, %1"
4591 [(set_attr "length" "4,8,4") 4724 [(set_attr "length" "4,8,4")
4592 (set_attr "type" "two_cycle_core,two_cycle_core,two_cycle_core")]) 4725 (set_attr "type" "two_cycle_core,two_cycle_core,two_cycle_core")])
4593 4726
4594 (define_insn "divaw" 4727 (define_insn "divaw"
4597 (match_operand:SI 2 "general_operand" "r,r,Cal"))] 4730 (match_operand:SI 2 "general_operand" "r,r,Cal"))]
4598 UNSPEC_ARC_DIVAW))] 4731 UNSPEC_ARC_DIVAW))]
4599 "TARGET_ARC700 || TARGET_EA_SET" 4732 "TARGET_ARC700 || TARGET_EA_SET"
4600 "@ 4733 "@
4601 divaw \t%0, %1, %2 4734 divaw \t%0, %1, %2
4602 divaw \t%0, %S1, %2 4735 divaw \t%0, %1, %2
4603 divaw \t%0, %1, %S2" 4736 divaw \t%0, %1, %2"
4604 [(set_attr "length" "4,8,8") 4737 [(set_attr "length" "4,8,8")
4605 (set_attr "type" "divaw,divaw,divaw")]) 4738 (set_attr "type" "divaw,divaw,divaw")])
4606 4739
4607 (define_insn "flag" 4740 (define_insn "flag"
4608 [(unspec_volatile [(match_operand:SI 0 "nonmemory_operand" "rL,I,Cal")] 4741 [(unspec_volatile [(match_operand:SI 0 "nonmemory_operand" "rL,I,Cal")]
4609 VUNSPEC_ARC_FLAG)] 4742 VUNSPEC_ARC_FLAG)]
4610 "" 4743 ""
4611 "@ 4744 "@
4612 flag%? %0 4745 flag%? %0
4613 flag %0 4746 flag %0
4614 flag%? %S0" 4747 flag%? %0"
4615 [(set_attr "length" "4,4,8") 4748 [(set_attr "length" "4,4,8")
4616 (set_attr "type" "misc,misc,misc") 4749 (set_attr "type" "misc,misc,misc")
4617 (set_attr "predicable" "yes,no,yes") 4750 (set_attr "predicable" "yes,no,yes")
4618 (set_attr "cond" "clob,clob,clob")]) 4751 (set_attr "cond" "clob,clob,clob")])
4619 4752
4656 [(set_attr "length" "4") 4789 [(set_attr "length" "4")
4657 (set_attr "type" "misc")]) 4790 (set_attr "type" "misc")])
4658 4791
4659 4792
4660 (define_insn "sleep" 4793 (define_insn "sleep"
4661 [(unspec_volatile [(match_operand:SI 0 "immediate_operand" "L")] 4794 [(unspec_volatile [(match_operand:SI 0 "nonmemory_operand" "Lr")]
4662 VUNSPEC_ARC_SLEEP)] 4795 VUNSPEC_ARC_SLEEP)]
4663 "check_if_valid_sleep_operand(operands,0)" 4796 ""
4664 "sleep %0" 4797 "sleep %0"
4665 [(set_attr "length" "4") 4798 [(set_attr "length" "4")
4666 (set_attr "type" "misc")]) 4799 (set_attr "type" "misc")])
4667 4800
4668 (define_insn "core_read" 4801 (define_insn "core_read"
4703 (define_insn "sr" 4836 (define_insn "sr"
4704 [(unspec_volatile [(match_operand:SI 0 "general_operand" "Cal,r,r,r") 4837 [(unspec_volatile [(match_operand:SI 0 "general_operand" "Cal,r,r,r")
4705 (match_operand:SI 1 "general_operand" "Ir,I,HCal,r")] 4838 (match_operand:SI 1 "general_operand" "Ir,I,HCal,r")]
4706 VUNSPEC_ARC_SR)] 4839 VUNSPEC_ARC_SR)]
4707 "" 4840 ""
4708 "sr\t%S0, [%1]" 4841 "sr\t%0, [%1]"
4709 [(set_attr "length" "8,4,8,4") 4842 [(set_attr "length" "8,4,8,4")
4710 (set_attr "type" "sr,sr,sr,sr")]) 4843 (set_attr "type" "sr,sr,sr,sr")])
4711 4844
4712 (define_insn "trap_s" 4845 (define_insn "trap_s"
4713 [(unspec_volatile [(match_operand:SI 0 "immediate_operand" "L,Cal")] 4846 [(unspec_volatile [(match_operand:SI 0 "immediate_operand" "L,Cal")]
4864 if (TARGET_V2 4997 if (TARGET_V2
4865 && ARC_INTERRUPT_P (arc_compute_function_type (cfun))) 4998 && ARC_INTERRUPT_P (arc_compute_function_type (cfun)))
4866 { 4999 {
4867 return \"rtie\"; 5000 return \"rtie\";
4868 } 5001 }
4869 if (TARGET_PAD_RETURN)
4870 arc_pad_return ();
4871 output_asm_insn (\"j%!%* [%0]%&\", &reg); 5002 output_asm_insn (\"j%!%* [%0]%&\", &reg);
4872 return \"\"; 5003 return \"\";
4873 } 5004 }
4874 [(set (attr "type") 5005 [(set (attr "type")
4875 (cond [(and (match_test "ARC_INTERRUPT_P (arc_compute_function_type (cfun))") 5006 (cond [(and (match_test "ARC_INTERRUPT_P (arc_compute_function_type (cfun))")
4909 xop[1] 5040 xop[1]
4910 = gen_rtx_REG (Pmode, 5041 = gen_rtx_REG (Pmode,
4911 arc_return_address_register (arc_compute_function_type 5042 arc_return_address_register (arc_compute_function_type
4912 (cfun))); 5043 (cfun)));
4913 5044
4914 if (TARGET_PAD_RETURN)
4915 arc_pad_return ();
4916 output_asm_insn (\"j%d0%!%# [%1]%&\", xop); 5045 output_asm_insn (\"j%d0%!%# [%1]%&\", xop);
4917 /* record the condition in case there is a delay insn. */ 5046 /* record the condition in case there is a delay insn. */
4918 arc_ccfsm_record_condition (xop[0], false, insn, 0); 5047 arc_ccfsm_record_condition (xop[0], false, insn, 0);
4919 return \"\"; 5048 return \"\";
4920 } 5049 }
4932 (not (match_operand 0 "equality_comparison_operator" "")) 5061 (not (match_operand 0 "equality_comparison_operator" ""))
4933 (const_int 4) 5062 (const_int 4)
4934 (eq_attr "delay_slot_filled" "yes") 5063 (eq_attr "delay_slot_filled" "yes")
4935 (const_int 4)] 5064 (const_int 4)]
4936 (const_int 2)))]) 5065 (const_int 2)))])
4937
4938 (define_insn_and_split "eh_return"
4939 [(eh_return)
4940 (use (match_operand:SI 0 "move_src_operand" "rC32,mCalCpc"))
4941 (clobber (match_scratch:SI 1 "=X,r"))
4942 (clobber (match_scratch:SI 2 "=&r,r"))]
4943 ""
4944 "#"
4945 "reload_completed"
4946 [(set (match_dup 2) (match_dup 0))]
4947 {
4948 int offs = arc_return_slot_offset ();
4949
4950 if (offs < 0)
4951 operands[2] = gen_rtx_REG (Pmode, RETURN_ADDR_REGNUM);
4952 else
4953 {
4954 if (!register_operand (operands[0], Pmode)
4955 && !satisfies_constraint_C32 (operands[0]))
4956 {
4957 emit_move_insn (operands[1], operands[0]);
4958 operands[0] = operands[1];
4959 }
4960 rtx addr = plus_constant (Pmode, stack_pointer_rtx, offs);
4961 if (!strict_memory_address_p (Pmode, addr))
4962 {
4963 emit_move_insn (operands[2], addr);
4964 addr = operands[2];
4965 }
4966 operands[2] = gen_frame_mem (Pmode, addr);
4967 }
4968 }
4969 [(set_attr "length" "12")])
4970 5066
4971 ;; ??? #ifdefs in function.c require the presence of this pattern, with a 5067 ;; ??? #ifdefs in function.c require the presence of this pattern, with a
4972 ;; non-constant predicate. 5068 ;; non-constant predicate.
4973 (define_expand "return" 5069 (define_expand "return"
4974 [(return)] 5070 [(return)]
5209 (pc))) 5305 (pc)))
5210 (set (match_dup 0) 5306 (set (match_dup 0)
5211 (plus:SI (match_dup 0) 5307 (plus:SI (match_dup 0)
5212 (const_int -1))) 5308 (const_int -1)))
5213 (clobber (match_scratch:SI 2 "=X,r"))] 5309 (clobber (match_scratch:SI 2 "=X,r"))]
5214 "TARGET_V2" 5310 "TARGET_DBNZ"
5215 "@ 5311 "@
5216 dbnz%#\\t%0,%l1 5312 dbnz%#\\t%0,%l1
5217 #" 5313 #"
5218 "TARGET_V2 && reload_completed && memory_operand (operands[0], SImode)" 5314 "TARGET_DBNZ && reload_completed && memory_operand (operands[0], SImode)"
5219 [(set (match_dup 2) (match_dup 0)) 5315 [(set (match_dup 2) (match_dup 0))
5220 (set (match_dup 2) (plus:SI (match_dup 2) (const_int -1))) 5316 (set (match_dup 2) (plus:SI (match_dup 2) (const_int -1)))
5221 (set (reg:CC CC_REG) (compare:CC (match_dup 2) (const_int 0))) 5317 (set (reg:CC CC_REG) (compare:CC (match_dup 2) (const_int 0)))
5222 (set (match_dup 0) (match_dup 2)) 5318 (set (match_dup 0) (match_dup 2))
5223 (set (pc) (if_then_else (ge (reg:CC CC_REG) 5319 (set (pc) (if_then_else (ge (reg:CC CC_REG)
5312 (set_attr "predicable" "yes,no")]) 5408 (set_attr "predicable" "yes,no")])
5313 5409
5314 ;; ??? Should this use arc_output_libcall and set is_sfunc? 5410 ;; ??? Should this use arc_output_libcall and set is_sfunc?
5315 (define_insn "*millicode_thunk_st" 5411 (define_insn "*millicode_thunk_st"
5316 [(match_parallel 0 "millicode_store_operation" 5412 [(match_parallel 0 "millicode_store_operation"
5317 [(set (mem:SI (reg:SI SP_REG)) (reg:SI 13))])] 5413 [(set (mem:SI (reg:SI SP_REG)) (reg:SI 13))])]
5318 "" 5414 ""
5319 { 5415 {
5320 output_asm_insn ("bl%* __st_r13_to_%0", 5416 output_asm_insn ("bl%* __st_r13_to_%0",
5321 &SET_SRC (XVECEXP (operands[0], 0, 5417 &SET_SRC (XVECEXP (operands[0], 0,
5322 XVECLEN (operands[0], 0) - 2))); 5418 XVECLEN (operands[0], 0) - 2)));
5324 } 5420 }
5325 [(set_attr "type" "call")]) 5421 [(set_attr "type" "call")])
5326 5422
5327 (define_insn "*millicode_thunk_ld" 5423 (define_insn "*millicode_thunk_ld"
5328 [(match_parallel 0 "millicode_load_clob_operation" 5424 [(match_parallel 0 "millicode_load_clob_operation"
5329 [(set (reg:SI 13) (mem:SI (reg:SI SP_REG)))])] 5425 [(set (reg:SI 13) (mem:SI (reg:SI SP_REG)))])]
5330 "" 5426 ""
5331 { 5427 {
5332 output_asm_insn ("bl%* __ld_r13_to_%0", 5428 output_asm_insn ("bl%* __ld_r13_to_%0",
5333 &SET_DEST (XVECEXP (operands[0], 0, 5429 &SET_DEST (XVECEXP (operands[0], 0,
5334 XVECLEN (operands[0], 0) - 2))); 5430 XVECLEN (operands[0], 0) - 2)));
5337 [(set_attr "type" "call")]) 5433 [(set_attr "type" "call")])
5338 5434
5339 ; the sibthunk restores blink, so we use the return rtx. 5435 ; the sibthunk restores blink, so we use the return rtx.
5340 (define_insn "*millicode_sibthunk_ld" 5436 (define_insn "*millicode_sibthunk_ld"
5341 [(match_parallel 0 "millicode_load_operation" 5437 [(match_parallel 0 "millicode_load_operation"
5342 [(return) 5438 [(return)
5343 (set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG) (reg:SI 12))) 5439 (set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG) (reg:SI 12)))
5344 (set (reg:SI 13) (mem:SI (reg:SI SP_REG)))])] 5440 (set (reg:SI 13) (mem:SI (reg:SI SP_REG)))])]
5345 "" 5441 ""
5346 { 5442 {
5347 output_asm_insn ("b%* __ld_r13_to_%0_ret", 5443 output_asm_insn ("b%* __ld_r13_to_%0_ret",
5348 &SET_DEST (XVECEXP (operands[0], 0, 5444 &SET_DEST (XVECEXP (operands[0], 0,
5349 XVECLEN (operands[0], 0) - 1))); 5445 XVECLEN (operands[0], 0) - 1)));
5633 { 5729 {
5634 arc_secondary_reload_conv (operands[1], operands[0], operands[2], true); 5730 arc_secondary_reload_conv (operands[1], operands[0], operands[2], true);
5635 DONE; 5731 DONE;
5636 }) 5732 })
5637 5733
5638
5639 (define_insn "extzvsi" 5734 (define_insn "extzvsi"
5640 [(set (match_operand:SI 0 "register_operand" "=r , r , r, r, r") 5735 [(set (match_operand:SI 0 "register_operand" "=r , r,r,r")
5641 (zero_extract:SI (match_operand:SI 1 "register_operand" "0 , r , 0, 0, r") 5736 (zero_extract:SI (match_operand:SI 1 "register_operand" "0 , r,r,0")
5642 (match_operand:SI 2 "const_int_operand" "C3p, C3p, i, i, i") 5737 (match_operand:SI 2 "const_int_operand" "C3p,C3p,n,n")
5643 (match_operand:SI 3 "const_int_operand" "i , i , i, i, i")))] 5738 (match_operand:SI 3 "const_int_operand" "n , n,n,n")))]
5644 "TARGET_HS && TARGET_BARREL_SHIFTER" 5739 "TARGET_HS && TARGET_BARREL_SHIFTER"
5645 { 5740 {
5646 int assemble_op2 = (((INTVAL (operands[2]) - 1) & 0x1f) << 5) | (INTVAL (operands[3]) & 0x1f); 5741 int assemble_op2 = (((INTVAL (operands[2]) - 1) & 0x1f) << 5) | (INTVAL (operands[3]) & 0x1f);
5647 operands[2] = GEN_INT (assemble_op2); 5742 operands[2] = GEN_INT (assemble_op2);
5648 return "xbfu%? %0,%1,%2"; 5743 return "xbfu%?\\t%0,%1,%2";
5649 } 5744 }
5650 [(set_attr "type" "shift") 5745 [(set_attr "type" "shift")
5651 (set_attr "iscompact" "false") 5746 (set_attr "iscompact" "false")
5652 (set_attr "length" "4,4,4,8,8") 5747 (set_attr "length" "4,4,8,8")
5653 (set_attr "predicable" "yes,no,no,yes,no") 5748 (set_attr "predicable" "yes,no,no,yes")
5654 (set_attr "cond" "canuse,nocond,nocond,canuse,nocond")]) 5749 (set_attr "cond" "canuse,nocond,nocond,canuse_limm")])
5655 5750
5656 (define_insn "kflag" 5751 (define_insn "kflag"
5657 [(unspec_volatile [(match_operand:SI 0 "nonmemory_operand" "rL,I,Cal")] 5752 [(unspec_volatile [(match_operand:SI 0 "nonmemory_operand" "rL,I,Cal")]
5658 VUNSPEC_ARC_KFLAG)] 5753 VUNSPEC_ARC_KFLAG)]
5659 "TARGET_V2" 5754 "TARGET_V2"
5660 "@ 5755 "@
5661 kflag%? %0 5756 kflag%? %0
5662 kflag %0 5757 kflag %0
5663 kflag%? %S0" 5758 kflag%? %0"
5664 [(set_attr "length" "4,4,8") 5759 [(set_attr "length" "4,4,8")
5665 (set_attr "type" "misc,misc,misc") 5760 (set_attr "type" "misc,misc,misc")
5666 (set_attr "predicable" "yes,no,yes") 5761 (set_attr "predicable" "yes,no,yes")
5667 (set_attr "cond" "clob,clob,clob")]) 5762 (set_attr "cond" "clob,clob,clob")])
5668 5763
5680 (unspec:SI [(match_operand:SI 1 "general_operand" "cL,Cal")] 5775 (unspec:SI [(match_operand:SI 1 "general_operand" "cL,Cal")]
5681 UNSPEC_ARC_FFS))] 5776 UNSPEC_ARC_FFS))]
5682 "TARGET_NORM && TARGET_V2" 5777 "TARGET_NORM && TARGET_V2"
5683 "@ 5778 "@
5684 ffs \t%0, %1 5779 ffs \t%0, %1
5685 ffs \t%0, %S1" 5780 ffs \t%0, %1"
5686 [(set_attr "length" "4,8") 5781 [(set_attr "length" "4,8")
5687 (set_attr "type" "two_cycle_core,two_cycle_core")]) 5782 (set_attr "type" "two_cycle_core,two_cycle_core")])
5688 5783
5689 (define_insn "ffs_f" 5784 (define_insn "ffs_f"
5690 [(set (match_operand:SI 0 "dest_reg_operand" "=w,w") 5785 [(set (match_operand:SI 0 "dest_reg_operand" "=w,w")
5693 (set (reg:CC_ZN CC_REG) 5788 (set (reg:CC_ZN CC_REG)
5694 (compare:CC_ZN (match_dup 1) (const_int 0)))] 5789 (compare:CC_ZN (match_dup 1) (const_int 0)))]
5695 "TARGET_NORM && TARGET_V2" 5790 "TARGET_NORM && TARGET_V2"
5696 "@ 5791 "@
5697 ffs.f\t%0, %1 5792 ffs.f\t%0, %1
5698 ffs.f\t%0, %S1" 5793 ffs.f\t%0, %1"
5699 [(set_attr "length" "4,8") 5794 [(set_attr "length" "4,8")
5700 (set_attr "type" "two_cycle_core,two_cycle_core")]) 5795 (set_attr "type" "two_cycle_core,two_cycle_core")])
5701 5796
5702 (define_expand "ffssi2" 5797 (define_expand "ffssi2"
5703 [(parallel [(set (match_dup 2) 5798 [(parallel [(set (match_dup 2)
5714 { 5809 {
5715 operands[2] = gen_reg_rtx (SImode); 5810 operands[2] = gen_reg_rtx (SImode);
5716 }) 5811 })
5717 5812
5718 (define_insn "fls" 5813 (define_insn "fls"
5719 [(set (match_operand:SI 0 "dest_reg_operand" "=w,w") 5814 [(set (match_operand:SI 0 "register_operand" "=r,r")
5720 (unspec:SI [(match_operand:SI 1 "general_operand" "cL,Cal")] 5815 (unspec:SI [(match_operand:SI 1 "nonmemory_operand" "rL,Cal")]
5721 UNSPEC_ARC_FLS))] 5816 UNSPEC_ARC_FLS))]
5722 "TARGET_NORM && TARGET_V2" 5817 "TARGET_NORM && TARGET_V2"
5723 "@ 5818 "fls\\t%0,%1"
5724 fls \t%0, %1
5725 fls \t%0, %S1"
5726 [(set_attr "length" "4,8") 5819 [(set_attr "length" "4,8")
5727 (set_attr "type" "two_cycle_core,two_cycle_core")]) 5820 (set_attr "type" "two_cycle_core,two_cycle_core")])
5728 5821
5729 (define_insn "seti" 5822 (define_insn "seti"
5730 [(unspec_volatile:SI [(match_operand:SI 0 "general_operand" "rL")] 5823 [(unspec_volatile:SI [(match_operand:SI 0 "nonmemory_operand" "rL")]
5731 VUNSPEC_ARC_SETI)] 5824 VUNSPEC_ARC_SETI)]
5732 "TARGET_V2" 5825 "TARGET_V2"
5733 "seti %0" 5826 "seti\\t%0"
5734 [(set_attr "length" "4") 5827 [(set_attr "length" "4")
5735 (set_attr "type" "misc")]) 5828 (set_attr "type" "misc")])
5736 5829
5737 ;; FPU/FPX expands 5830 ;; FPU/FPX expands
5738 5831
6175 "" 6268 ""
6176 "" 6269 ""
6177 [(set_attr "length" "0")]) 6270 [(set_attr "length" "0")])
6178 6271
6179 ;; MAC and DMPY instructions 6272 ;; MAC and DMPY instructions
6180 (define_insn_and_split "maddsidi4" 6273 (define_expand "maddsidi4"
6274 [(match_operand:DI 0 "register_operand" "")
6275 (match_operand:SI 1 "register_operand" "")
6276 (match_operand:SI 2 "extend_operand" "")
6277 (match_operand:DI 3 "register_operand" "")]
6278 "TARGET_PLUS_DMPY"
6279 "{
6280 emit_insn (gen_maddsidi4_split (operands[0], operands[1], operands[2], operands[3]));
6281 DONE;
6282 }")
6283
6284 (define_insn_and_split "maddsidi4_split"
6181 [(set (match_operand:DI 0 "register_operand" "=r") 6285 [(set (match_operand:DI 0 "register_operand" "=r")
6182 (plus:DI 6286 (plus:DI
6183 (mult:DI 6287 (mult:DI
6184 (sign_extend:DI (match_operand:SI 1 "register_operand" "%r")) 6288 (sign_extend:DI (match_operand:SI 1 "register_operand" "%r"))
6185 (sign_extend:DI (match_operand:SI 2 "extend_operand" "ri"))) 6289 (sign_extend:DI (match_operand:SI 2 "extend_operand" "ri")))
6186 (match_operand:DI 3 "register_operand" "r")))] 6290 (match_operand:DI 3 "register_operand" "r")))
6291 (clobber (reg:DI ARCV2_ACC))]
6187 "TARGET_PLUS_DMPY" 6292 "TARGET_PLUS_DMPY"
6188 "#" 6293 "#"
6189 "TARGET_PLUS_DMPY && reload_completed" 6294 "TARGET_PLUS_DMPY && reload_completed"
6190 [(const_int 0)] 6295 [(const_int 0)]
6191 "{ 6296 "{
6192 rtx acc_reg = gen_rtx_REG (DImode, ACC_REG_FIRST); 6297 rtx acc_reg = gen_rtx_REG (DImode, ACC_REG_FIRST);
6193 emit_move_insn (acc_reg, operands[3]); 6298 emit_move_insn (acc_reg, operands[3]);
6194 if (TARGET_PLUS_MACD) 6299 if (TARGET_PLUS_MACD && even_register_operand (operands[0], DImode))
6195 emit_insn (gen_macd (operands[0], operands[1], operands[2])); 6300 emit_insn (gen_macd (operands[0], operands[1], operands[2]));
6196 else 6301 else
6197 { 6302 {
6198 emit_insn (gen_mac (operands[1], operands[2])); 6303 emit_insn (gen_mac (operands[1], operands[2]));
6199 emit_move_insn (operands[0], acc_reg); 6304 emit_move_insn (operands[0], acc_reg);
6263 [(set_attr "length" "4,8") 6368 [(set_attr "length" "4,8")
6264 (set_attr "type" "multi") 6369 (set_attr "type" "multi")
6265 (set_attr "predicable" "no") 6370 (set_attr "predicable" "no")
6266 (set_attr "cond" "nocond")]) 6371 (set_attr "cond" "nocond")])
6267 6372
6268 (define_insn_and_split "umaddsidi4" 6373 (define_expand "umaddsidi4"
6374 [(match_operand:DI 0 "register_operand" "")
6375 (match_operand:SI 1 "register_operand" "")
6376 (match_operand:SI 2 "extend_operand" "")
6377 (match_operand:DI 3 "register_operand" "")]
6378 "TARGET_PLUS_DMPY"
6379 "{
6380 emit_insn (gen_umaddsidi4_split (operands[0], operands[1], operands[2], operands[3]));
6381 DONE;
6382 }")
6383
6384 (define_insn_and_split "umaddsidi4_split"
6269 [(set (match_operand:DI 0 "register_operand" "=r") 6385 [(set (match_operand:DI 0 "register_operand" "=r")
6270 (plus:DI 6386 (plus:DI
6271 (mult:DI 6387 (mult:DI
6272 (zero_extend:DI (match_operand:SI 1 "register_operand" "%r")) 6388 (zero_extend:DI (match_operand:SI 1 "register_operand" "%r"))
6273 (zero_extend:DI (match_operand:SI 2 "extend_operand" "ri"))) 6389 (zero_extend:DI (match_operand:SI 2 "extend_operand" "ri")))
6274 (match_operand:DI 3 "register_operand" "r")))] 6390 (match_operand:DI 3 "register_operand" "r")))
6391 (clobber (reg:DI ARCV2_ACC))]
6275 "TARGET_PLUS_DMPY" 6392 "TARGET_PLUS_DMPY"
6276 "#" 6393 "#"
6277 "TARGET_PLUS_DMPY && reload_completed" 6394 "TARGET_PLUS_DMPY && reload_completed"
6278 [(const_int 0)] 6395 [(const_int 0)]
6279 "{ 6396 "{
6280 rtx acc_reg = gen_rtx_REG (DImode, ACC_REG_FIRST); 6397 rtx acc_reg = gen_rtx_REG (DImode, ACC_REG_FIRST);
6281 emit_move_insn (acc_reg, operands[3]); 6398 emit_move_insn (acc_reg, operands[3]);
6282 if (TARGET_PLUS_MACD) 6399 if (TARGET_PLUS_MACD && even_register_operand (operands[0], DImode))
6283 emit_insn (gen_macdu (operands[0], operands[1], operands[2])); 6400 emit_insn (gen_macdu (operands[0], operands[1], operands[2]));
6284 else 6401 else
6285 { 6402 {
6286 emit_insn (gen_macu (operands[1], operands[2])); 6403 emit_insn (gen_macu (operands[1], operands[2]));
6287 emit_move_insn (operands[0], acc_reg); 6404 emit_move_insn (operands[0], acc_reg);
6424 [(set_attr "length" "0") 6541 [(set_attr "length" "0")
6425 (set_attr "iscompact" "false") 6542 (set_attr "iscompact" "false")
6426 (set_attr "type" "block")] 6543 (set_attr "type" "block")]
6427 ) 6544 )
6428 6545
6546 (define_insn "*add_shift"
6547 [(set (match_operand:SI 0 "register_operand" "=q,r,r")
6548 (plus:SI (ashift:SI (match_operand:SI 1 "register_operand" "q,r,r")
6549 (match_operand:SI 2 "_1_2_3_operand" ""))
6550 (match_operand:SI 3 "nonmemory_operand" "0,r,Csz")))]
6551 ""
6552 "add%2%?\\t%0,%3,%1"
6553 [(set_attr "length" "*,4,8")
6554 (set_attr "predicable" "yes,no,no")
6555 (set_attr "iscompact" "maybe,false,false")
6556 (set_attr "cond" "canuse,nocond,nocond")])
6557
6558 (define_insn "*add_shift2"
6559 [(set (match_operand:SI 0 "register_operand" "=q,r,r")
6560 (plus:SI (match_operand:SI 1 "nonmemory_operand" "0,r,Cal")
6561 (ashift:SI (match_operand:SI 2 "register_operand" "q,r,r")
6562 (match_operand:SI 3 "_1_2_3_operand" ""))))]
6563 ""
6564 "add%3%?\\t%0,%1,%2"
6565 [(set_attr "length" "*,4,8")
6566 (set_attr "predicable" "yes,no,no")
6567 (set_attr "iscompact" "maybe,false,false")
6568 (set_attr "cond" "canuse,nocond,nocond")])
6569
6570 (define_insn "*sub_shift"
6571 [(set (match_operand:SI 0"register_operand" "=r,r,r")
6572 (minus:SI (match_operand:SI 1 "nonmemory_operand" "0,r,Cal")
6573 (ashift:SI (match_operand:SI 2 "register_operand" "r,r,r")
6574 (match_operand:SI 3 "_1_2_3_operand" ""))))]
6575 ""
6576 "sub%3\\t%0,%1,%2"
6577 [(set_attr "length" "4,4,8")
6578 (set_attr "cond" "canuse,nocond,nocond")
6579 (set_attr "predicable" "yes,no,no")])
6580
6581 (define_insn "*sub_shift_cmp0_noout"
6582 [(set (match_operand 0 "cc_set_register" "")
6583 (compare:CC
6584 (minus:SI (match_operand:SI 1 "register_operand" "r")
6585 (ashift:SI (match_operand:SI 2 "register_operand" "r")
6586 (match_operand:SI 3 "_1_2_3_operand" "")))
6587 (const_int 0)))]
6588 ""
6589 "sub%3.f\\t0,%1,%2"
6590 [(set_attr "length" "4")])
6591
6592 (define_insn "*compare_si_ashiftsi"
6593 [(set (match_operand 0 "cc_set_register" "")
6594 (compare:CC (match_operand:SI 1 "register_operand" "r")
6595 (ashift:SI (match_operand:SI 2 "register_operand" "r")
6596 (match_operand:SI 3 "_1_2_3_operand" ""))))]
6597 ""
6598 "sub%3.f\\t0,%1,%2"
6599 [(set_attr "length" "4")])
6600
6601 ;; Convert the sequence
6602 ;; asl rd,rn,_1_2_3
6603 ;; cmp ra,rd
6604 ;; into
6605 ;; sub{123}.f 0,ra,rn
6606 (define_peephole2
6607 [(set (match_operand:SI 0 "register_operand" "")
6608 (ashift:SI (match_operand:SI 1 "register_operand" "")
6609 (match_operand:SI 2 "_1_2_3_operand" "")))
6610 (set (reg:CC CC_REG)
6611 (compare:CC (match_operand:SI 3 "register_operand" "")
6612 (match_dup 0)))]
6613 "peep2_reg_dead_p (2, operands[0])"
6614 [(set (reg:CC CC_REG) (compare:CC (match_dup 3)
6615 (ashift:SI (match_dup 1) (match_dup 2))))])
6616
6429 ;; include the arc-FPX instructions 6617 ;; include the arc-FPX instructions
6430 (include "fpx.md") 6618 (include "fpx.md")
6431 6619
6432 ;; include the arc-FPU instructions 6620 ;; include the arc-FPU instructions
6433 (include "fpu.md") 6621 (include "fpu.md")