Mercurial > hg > CbC > CbC_gcc
diff gcc/config/arc/arc.md @ 131:84e7813d76e9
gcc-8.2
| author | mir3636 |
|---|---|
| date | Thu, 25 Oct 2018 07:37:49 +0900 |
| parents | 04ced10e8804 |
| children | 1830386684a0 |
line wrap: on
line diff
--- a/gcc/config/arc/arc.md Fri Oct 27 22:46:09 2017 +0900 +++ b/gcc/config/arc/arc.md Thu Oct 25 07:37:49 2018 +0900 @@ -1,5 +1,5 @@ ;; Machine description of the Synopsys DesignWare ARC cpu for GNU C compiler -;; Copyright (C) 1994-2017 Free Software Foundation, Inc. +;; Copyright (C) 1994-2018 Free Software Foundation, Inc. ;; Sources derived from work done by Sankhya Technologies (www.sankhya.com) on ;; behalf of Synopsys Inc. @@ -82,6 +82,7 @@ (include ("arc700.md")) (include ("arcEM.md")) (include ("arcHS.md")) +(include ("arcHS4x.md")) ;; Predicates @@ -136,9 +137,7 @@ UNSPEC_ARC_VMPY2H UNSPEC_ARC_VMPY2HU UNSPEC_ARC_STKTIE - ]) - -(define_c_enum "vunspec" [ + VUNSPEC_ARC_RTIE VUNSPEC_ARC_SYNC VUNSPEC_ARC_BRK @@ -163,6 +162,7 @@ VUNSPEC_ARC_CAS VUNSPEC_ARC_SC VUNSPEC_ARC_LL + VUNSPEC_ARC_BLOCKAGE ]) (define_constants @@ -206,7 +206,7 @@ simd_vcompare, simd_vpermute, simd_vpack, simd_vpack_with_acc, simd_valign, simd_valign_with_acc, simd_vcontrol, simd_vspecial_3cycle, simd_vspecial_4cycle, simd_dma, mul16_em, div_rem, - fpu, block" + fpu, fpu_fuse, fpu_sdiv, fpu_ddiv, fpu_cvt, block" (cond [(eq_attr "is_sfunc" "yes") (cond [(match_test "!TARGET_LONG_CALLS_SET && (!TARGET_MEDIUM_CALLS || GET_CODE (PATTERN (insn)) != COND_EXEC)") (const_string "call") (match_test "flag_pic") (const_string "sfunc")] @@ -386,13 +386,18 @@ ;; and insn lengths: insns with shimm values cannot be conditionally executed. (define_attr "length" "" (cond - [(eq_attr "iscompact" "true,maybe") + [(eq_attr "iscompact" "true") + (const_int 2) + + (eq_attr "iscompact" "maybe") (cond [(eq_attr "type" "sfunc") (cond [(match_test "GET_CODE (PATTERN (insn)) == COND_EXEC") (const_int 12)] (const_int 10)) - (match_test "GET_CODE (PATTERN (insn)) == COND_EXEC") (const_int 4)] + (match_test "GET_CODE (PATTERN (insn)) == COND_EXEC") (const_int 4) + (match_test "find_reg_note (insn, REG_SAVE_NOTE, GEN_INT (1))") + (const_int 4)] (const_int 2)) (eq_attr "iscompact" "true_limm") @@ -471,6 +476,8 @@ (symbol_ref "(arc_hazard (prev_active_insn (insn), insn) + arc_hazard (insn, next_active_insn (insn)))")) (const_string "false") + (match_test "find_reg_note (insn, REG_SAVE_NOTE, GEN_INT (2))") + (const_string "false") (eq_attr "iscompact" "maybe") (const_string "true") ] @@ -498,6 +505,8 @@ (cond [(eq_attr "cond" "!canuse") (const_string "no") (eq_attr "type" "call,branch,uncond_branch,jump,brcc") (const_string "no") + (match_test "find_reg_note (insn, REG_SAVE_NOTE, GEN_INT (2))") + (const_string "no") (eq_attr "length" "2,4") (const_string "yes")] (const_string "no"))) @@ -591,14 +600,22 @@ ;; somehow modify them to become inelegible for delay slots if a decision ;; is made that makes conditional execution required. -(define_attr "tune" "none,arc600,arc700_4_2_std,arc700_4_2_xmac" +(define_attr "tune" "none,arc600,arc700_4_2_std,arc700_4_2_xmac, core_3, \ +archs4x, archs4xd, archs4xd_slow" (const (cond [(symbol_ref "arc_tune == TUNE_ARC600") (const_string "arc600") (symbol_ref "arc_tune == TUNE_ARC700_4_2_STD") (const_string "arc700_4_2_std") (symbol_ref "arc_tune == TUNE_ARC700_4_2_XMAC") - (const_string "arc700_4_2_xmac")] + (const_string "arc700_4_2_xmac") + (symbol_ref "arc_tune == ARC_TUNE_CORE_3") + (const_string "core_3") + (symbol_ref "arc_tune == TUNE_ARCHS4X") + (const_string "archs4x") + (ior (symbol_ref "arc_tune == TUNE_ARCHS4XD") + (symbol_ref "arc_tune == TUNE_ARCHS4XD_SLOW")) + (const_string "archs4xd")] (const_string "none")))) (define_attr "tune_arc700" "false,true" @@ -606,6 +623,15 @@ (const_string "true") (const_string "false"))) +(define_attr "tune_dspmpy" "none, slow, fast" + (const + (cond [(ior (symbol_ref "arc_tune == TUNE_ARCHS4X") + (symbol_ref "arc_tune == TUNE_ARCHS4XD")) + (const_string "fast") + (symbol_ref "arc_tune == TUNE_ARCHS4XD_SLOW") + (const_string "slow")] + (const_string "none")))) + ;; Move instructions. (define_expand "movqi" [(set (match_operand:QI 0 "move_dest_operand" "") @@ -637,7 +663,7 @@ mov%? %0,%1 mov%? %0,%1 mov%? %0,%1 - mov%? %0,%S1 + mov%? %0,%1 ldb%? %0,%1%& stb%? %1,%0%& ldb%? %0,%1%& @@ -678,9 +704,9 @@ mov%? %0,%1 mov%? %0,%1 mov%? %0,%1 - mov%? %0,%S1%& - mov%? %0,%S1 - mov%? %0,%S1 + mov%? %0,%1%& + mov%? %0,%1 + mov%? %0,%1 ld%_%? %0,%1%& st%_%? %1,%0%& xld%_%U1 %0,%1 @@ -688,8 +714,8 @@ xst%_%U0 %1,%0 st%_%U0%V0 %1,%0 st%_%U0%V0 %1,%0 - st%_%U0%V0 %S1,%0 - st%_%U0%V0 %S1,%0" + st%_%U0%V0 %1,%0 + st%_%U0%V0 %1,%0" [(set_attr "type" "move,move,move,move,move,move,move,move,move,move,move,load,store,load,load,store,store,store,store,store") (set_attr "iscompact" "maybe,maybe,maybe,true,true,false,false,false,maybe_limm,maybe_limm,false,true,true,false,false,false,false,false,false,false") (set_attr "predicable" "yes,no,yes,no,no,yes,no,yes,yes,yes,yes,no,no,no,no,no,no,no,no,no") @@ -720,7 +746,9 @@ /* Don't use a LIMM that we could load with a single insn - we loose delay-slot filling opportunities. */ && !satisfies_constraint_I (operands[1]) - && satisfies_constraint_Usc (operands[0]))" + && satisfies_constraint_Usc (operands[0])) + || (satisfies_constraint_Cm3 (operands[1]) + && memory_operand (operands[0], SImode))" "@ mov%? %0,%1%& ;0 mov%? %0,%1%& ;1 @@ -734,12 +762,12 @@ movh.cl %0,%L1>>16 ;9 * return INTVAL (operands[1]) & 0xffffff ? \"movbi.cl %0,%1 >> %p1,%p1,8;10\" : \"movbi.cl %0,%L1 >> 24,24,8;10\"; mov%? %0,%1 ;11 - add %0,%S1 ;12 + add %0,%1 ;12 add %0,pcl,%1@pcl ;13 - mov%? %0,%1 ;14 - mov%? %0,%1 ;15 - mov%? %0,%1 ;16 - ld%?%U1 %0,%1 ;17 + mov%? %0,%j1 ;14 + mov%? %0,%j1 ;15 + mov%? %0,%j1 ;16 + ld%? %0,%1 ;17 st%? %1,%0%& ;18 * return arc_short_long (insn, \"push%? %1%&\", \"st%U0 %1,%0%&\"); * return arc_short_long (insn, \"pop%? %0%&\", \"ld%U1 %0,%1%&\"); @@ -788,20 +816,90 @@ "st%U0 %1,%0\;st%U0.di %1,%0" [(set_attr "type" "store")]) +;; Combiner patterns for compare with zero +(define_mode_iterator SQH [QI HI]) +(define_mode_attr SQH_postfix [(QI "b") (HI "%_")]) + +(define_code_iterator SEZ [sign_extend zero_extend]) +(define_code_attr SEZ_prefix [(sign_extend "sex") (zero_extend "ext")]) + +(define_insn "*<SEZ_prefix>xt<SQH_postfix>_cmp0_noout" + [(set (match_operand 0 "cc_set_register" "") + (compare:CC_ZN (SEZ:SI (match_operand:SQH 1 "register_operand" "r")) + (const_int 0)))] + "" + "<SEZ_prefix><SQH_postfix>.f\\t0,%1" + [(set_attr "type" "compare") + (set_attr "cond" "set_zn")]) + +(define_insn "*<SEZ_prefix>xt<SQH_postfix>_cmp0" + [(set (match_operand 0 "cc_set_register" "") + (compare:CC_ZN (SEZ:SI (match_operand:SQH 1 "register_operand" "r")) + (const_int 0))) + (set (match_operand:SI 2 "register_operand" "=r") + (SEZ:SI (match_dup 1)))] + "" + "<SEZ_prefix><SQH_postfix>.f\\t%2,%1" + [(set_attr "type" "compare") + (set_attr "cond" "set_zn")]) + +(define_insn "*xbfu_cmp0_noout" + [(set (match_operand 0 "cc_set_register" "") + (compare:CC_Z + (zero_extract:SI + (match_operand:SI 1 "register_operand" " r,r") + (match_operand:SI 2 "const_int_operand" "C3p,n") + (match_operand:SI 3 "const_int_operand" " n,n")) + (const_int 0)))] + "TARGET_HS && TARGET_BARREL_SHIFTER" + { + int assemble_op2 = (((INTVAL (operands[2]) - 1) & 0x1f) << 5) | (INTVAL (operands[3]) & 0x1f); + operands[2] = GEN_INT (assemble_op2); + return "xbfu%?.f\\t0,%1,%2"; + } + [(set_attr "type" "shift") + (set_attr "iscompact" "false") + (set_attr "length" "4,8") + (set_attr "predicable" "no") + (set_attr "cond" "set_zn")]) + +(define_insn "*xbfu_cmp0" + [(set (match_operand 4 "cc_set_register" "") + (compare:CC_Z + (zero_extract:SI + (match_operand:SI 1 "register_operand" "0 ,r,0") + (match_operand:SI 2 "const_int_operand" "C3p,n,n") + (match_operand:SI 3 "const_int_operand" "n ,n,n")) + (const_int 0))) + (set (match_operand:SI 0 "register_operand" "=r,r,r") + (zero_extract:SI (match_dup 1) (match_dup 2) (match_dup 3)))] + "TARGET_HS && TARGET_BARREL_SHIFTER" + { + int assemble_op2 = (((INTVAL (operands[2]) - 1) & 0x1f) << 5) | (INTVAL (operands[3]) & 0x1f); + operands[2] = GEN_INT (assemble_op2); + return "xbfu%?.f\\t%0,%1,%2"; + } + [(set_attr "type" "shift") + (set_attr "iscompact" "false") + (set_attr "length" "4,8,8") + (set_attr "predicable" "yes,no,yes") + (set_attr "cond" "set_zn")]) + +; splitting to 'tst' allows short insns and combination into brcc. (define_insn_and_split "*movsi_set_cc_insn" - [(set (match_operand:CC_ZN 2 "cc_set_register" "") - (match_operator:CC_ZN 3 "zn_compare_operator" - [(match_operand:SI 1 "nonmemory_operand" "cI,cL,Cal") (const_int 0)])) - (set (match_operand:SI 0 "register_operand" "=w,w,w") + [(set (match_operand 2 "cc_set_register" "") + (match_operator 3 "zn_compare_operator" + [(match_operand:SI 1 "nonmemory_operand" "rL,rI,Cal") + (const_int 0)])) + (set (match_operand:SI 0 "register_operand" "=r,r,r") (match_dup 1))] "" - "mov%?.f %0,%S1" - ; splitting to 'tst' allows short insns and combination into brcc. + "mov%?.f\\t%0,%1" "reload_completed && operands_match_p (operands[0], operands[1])" [(set (match_dup 2) (match_dup 3))] "" [(set_attr "type" "compare") - (set_attr "predicable" "no,yes,yes") + (set_attr "predicable" "yes,no,yes") (set_attr "cond" "set_zn") (set_attr "length" "4,4,8")]) @@ -884,7 +982,7 @@ } " [(set_attr "iscompact" "maybe,maybe,false,false,false,false,false,false") - (set_attr "type" "compare,compare,compare,compare,compare,compare,shift,compare") + (set_attr "type" "compare,compare,compare,compare,compare,compare,binary,compare") (set_attr "length" "*,*,4,4,4,4,4,8") (set_attr "predicable" "no,yes,no,yes,no,no,no,yes") (set_attr "cond" "set_zn")]) @@ -951,20 +1049,36 @@ (set_attr "cond" "set_zn") (set_attr "length" "*,4,4,4,8")]) -(define_insn "*commutative_binary_comparison" - [(set (match_operand:CC_ZN 0 "cc_set_register" "") - (match_operator:CC_ZN 5 "zn_compare_operator" - [(match_operator:SI 4 "commutative_operator" - [(match_operand:SI 1 "register_operand" "%c,c") - (match_operand:SI 2 "nonmemory_operand" "cL,Cal")]) - (const_int 0)])) - (clobber (match_scratch:SI 3 "=X,X"))] - "" - "%O4.f 0,%1,%2" +;; The next two patterns are for plos, ior, xor, and, and mult. +(define_insn "*commutative_binary_cmp0_noout" + [(set (match_operand 0 "cc_set_register" "") + (match_operator 4 "zn_compare_operator" + [(match_operator:SI 3 "commutative_operator" + [(match_operand:SI 1 "register_operand" "%r,r") + (match_operand:SI 2 "nonmemory_operand" "rL,Cal")]) + (const_int 0)]))] + "" + "%O3.f\\t0,%1,%2" [(set_attr "type" "compare") (set_attr "cond" "set_zn") (set_attr "length" "4,8")]) +(define_insn "*commutative_binary_cmp0" + [(set (match_operand 3 "cc_set_register" "") + (match_operator 5 "zn_compare_operator" + [(match_operator:SI 4 "commutative_operator" + [(match_operand:SI 1 "register_operand" "%0, 0,r,r") + (match_operand:SI 2 "nonmemory_operand" "rL,rI,r,Cal")]) + (const_int 0)])) + (set (match_operand:SI 0 "register_operand" "=r,r,r,r") + (match_dup 4))] + "" + "%O4.f\\t%0,%1,%2" + [(set_attr "type" "compare") + (set_attr "cond" "set_zn") + (set_attr "predicable" "yes,yes,no,no") + (set_attr "length" "4,4,4,8")]) + ; for flag setting 'add' instructions like if (a+b) { ...} ; the combiner needs this pattern (define_insn "*addsi_compare" @@ -1037,32 +1151,60 @@ (set_attr "cond" "set_zn,set_zn,set_zn") (set_attr "length" "4,4,8")]) -; this pattern is needed by combiner for cases like if (c=a<<b) { ... } -(define_insn "*noncommutative_binary_comparison_result_used" - [(set (match_operand 3 "cc_register" "") +(define_insn "*noncommutative_binary_cmp0" + [(set (match_operand 3 "cc_set_register" "") (match_operator 5 "zn_compare_operator" [(match_operator:SI 4 "noncommutative_operator" - [(match_operand:SI 1 "register_operand" "c,0,c") - (match_operand:SI 2 "nonmemory_operand" "cL,I,?Cal")]) - (const_int 0)])) - (set (match_operand:SI 0 "register_operand" "=w,w,w") - (match_dup 4 ))] - "TARGET_BARREL_SHIFTER || GET_CODE (operands[4]) == MINUS" - "%O4.f %0,%1,%2" - [(set_attr "type" "compare,compare,compare") - (set_attr "cond" "set_zn,set_zn,set_zn") - (set_attr "length" "4,4,8")]) - -(define_insn "*noncommutative_binary_comparison" - [(set (match_operand:CC_ZN 0 "cc_set_register" "") - (match_operator:CC_ZN 5 "zn_compare_operator" + [(match_operand:SI 1 "register_operand" "0,r,0, 0,r") + (match_operand:SI 2 "nonmemory_operand" "rL,r,I,Cal,Cal")]) + (const_int 0)])) + (set (match_operand:SI 0 "register_operand" "=r,r,r,r,r") + (match_dup 4))] + "" + "%O4%?.f\\t%0,%1,%2" + [(set_attr "type" "compare") + (set_attr "cond" "set_zn") + (set_attr "predicable" "yes,no,no,yes,no") + (set_attr "length" "4,4,4,8,8")]) + +(define_insn "*noncommutative_binary_cmp0_noout" + [(set (match_operand 0 "cc_set_register" "") + (match_operator 3 "zn_compare_operator" [(match_operator:SI 4 "noncommutative_operator" - [(match_operand:SI 1 "register_operand" "c,c") - (match_operand:SI 2 "nonmemory_operand" "cL,Cal")]) + [(match_operand:SI 1 "register_operand" "r,r") + (match_operand:SI 2 "nonmemory_operand" "rL,Cal")]) + (const_int 0)]))] + "" + "%O4.f\\t0,%1,%2" + [(set_attr "type" "compare") + (set_attr "cond" "set_zn") + (set_attr "length" "4,8")]) + +;;rsub variants +(define_insn "*rsub_cmp0" + [(set (match_operand 4 "cc_set_register" "") + (match_operator 3 "zn_compare_operator" + [(minus:SI + (match_operand:SI 1 "nonmemory_operand" "rL,Cal") + (match_operand:SI 2 "register_operand" "r,r")) (const_int 0)])) - (clobber (match_scratch:SI 3 "=X,X"))] - "TARGET_BARREL_SHIFTER || GET_CODE (operands[4]) == MINUS" - "%O4.f 0,%1,%2" + (set (match_operand:SI 0 "register_operand" "=r,r") + (minus:SI (match_dup 1) (match_dup 2)))] + "" + "rsub.f\\t%0,%2,%1" + [(set_attr "type" "compare") + (set_attr "cond" "set_zn") + (set_attr "length" "4,8")]) + +(define_insn "*rsub_cmp0_noout" + [(set (match_operand 0 "cc_set_register" "") + (match_operator 3 "zn_compare_operator" + [(minus:SI + (match_operand:SI 1 "nonmemory_operand" "rL,Cal") + (match_operand:SI 2 "register_operand" "r,r")) + (const_int 0)]))] + "" + "rsub.f\\t0,%2,%1" [(set_attr "type" "compare") (set_attr "cond" "set_zn") (set_attr "length" "4,8")]) @@ -1103,10 +1245,12 @@ ") (define_insn_and_split "*movdi_insn" - [(set (match_operand:DI 0 "move_dest_operand" "=w, w,r,m") - (match_operand:DI 1 "move_double_src_operand" "c,Hi,m,c"))] + [(set (match_operand:DI 0 "move_dest_operand" "=w, w,r, m") + (match_operand:DI 1 "move_double_src_operand" "c,Hi,m,cCm3"))] "register_operand (operands[0], DImode) - || register_operand (operands[1], DImode)" + || register_operand (operands[1], DImode) + || (satisfies_constraint_Cm3 (operands[1]) + && memory_operand (operands[0], DImode))" "* { switch (which_alternative) @@ -1116,19 +1260,16 @@ case 2: if (TARGET_LL64 - && ((even_register_operand (operands[0], DImode) - && memory_operand (operands[1], DImode)) - || (memory_operand (operands[0], DImode) - && even_register_operand (operands[1], DImode)))) + && memory_operand (operands[1], DImode) + && even_register_operand (operands[0], DImode)) return \"ldd%U1%V1 %0,%1%&\"; return \"#\"; case 3: if (TARGET_LL64 - && ((even_register_operand (operands[0], DImode) - && memory_operand (operands[1], DImode)) - || (memory_operand (operands[0], DImode) - && even_register_operand (operands[1], DImode)))) + && memory_operand (operands[0], DImode) + && (even_register_operand (operands[1], DImode) + || satisfies_constraint_Cm3 (operands[1]))) return \"std%U0%V0 %1,%0\"; return \"#\"; } @@ -1153,19 +1294,24 @@ "if (prepare_move_operands (operands, SFmode)) DONE;") (define_insn "*movsf_insn" - [(set (match_operand:SF 0 "move_dest_operand" "=h,w,w,r,m") - (match_operand:SF 1 "move_src_operand" "hCm1,c,E,m,c"))] + [(set (match_operand:SF 0 "move_dest_operand" "=h,h, r,r, q,S,Usc,r,m") + (match_operand:SF 1 "move_src_operand" "hCfZ,E,rCfZ,E,Uts,q, E,m,r"))] "register_operand (operands[0], SFmode) || register_operand (operands[1], SFmode)" "@ - mov%? %0,%1 - mov%? %0,%1 - mov%? %0,%1 ; %A1 - ld%U1%V1 %0,%1 - st%U0%V0 %1,%0" - [(set_attr "type" "move,move,move,load,store") - (set_attr "predicable" "no,yes,yes,no,no") - (set_attr "iscompact" "true,false,false,false,false")]) + mov%?\\t%0,%1 + mov%?\\t%0,%1 ; %A1 + mov%?\\t%0,%1 + mov%?\\t%0,%1 ; %A1 + ld%?%U1\\t%0,%1 + st%?\\t%1,%0 + st%U0%V0\\t%1,%0 + ld%U1%V1\\t%0,%1 + st%U0%V0\\t%1,%0" + [(set_attr "type" "move,move,move,move,load,store,store,load,store") + (set_attr "predicable" "no,no,yes,yes,no,no,no,no,no") + (set_attr "length" "*,*,4,*,*,*,*,*,*") + (set_attr "iscompact" "true,true_limm,false,false,true,true,false,false,false")]) (define_expand "movdf" [(set (match_operand:DF 0 "move_dest_operand" "") @@ -1283,7 +1429,7 @@ (set (match_operand:SI 0 "dest_reg_operand" "=r,r") (plus:SI (match_dup 1) (match_dup 2)))] "" - "ldb.a%V4 %3,[%0,%S2]" + "ldb.a%V4 %3,[%0,%2]" [(set_attr "type" "load,load") (set_attr "length" "4,8")]) @@ -1295,7 +1441,7 @@ (set (match_operand:SI 0 "dest_reg_operand" "=r,r") (plus:SI (match_dup 1) (match_dup 2)))] "" - "ldb.a%V4 %3,[%0,%S2]" + "ldb.a%V4 %3,[%0,%2]" [(set_attr "type" "load,load") (set_attr "length" "4,8")]) @@ -1307,7 +1453,7 @@ (set (match_operand:SI 0 "dest_reg_operand" "=r,r") (plus:SI (match_dup 1) (match_dup 2)))] "" - "ldb.x.a%V4 %3,[%0,%S2]" + "ldb.x.a%V4 %3,[%0,%2]" [(set_attr "type" "load,load") (set_attr "length" "4,8")]) @@ -1333,7 +1479,7 @@ (set (match_operand:SI 0 "dest_reg_operand" "=w,w") (plus:SI (match_dup 1) (match_dup 2)))] "" - "ld%_.a%V4 %3,[%0,%S2]" + "ld%_.a%V4 %3,[%0,%2]" [(set_attr "type" "load,load") (set_attr "length" "4,8")]) @@ -1345,7 +1491,7 @@ (set (match_operand:SI 0 "dest_reg_operand" "=r,r") (plus:SI (match_dup 1) (match_dup 2)))] "" - "ld%_.a%V4 %3,[%0,%S2]" + "ld%_.a%V4 %3,[%0,%2]" [(set_attr "type" "load,load") (set_attr "length" "4,8")]) @@ -1358,7 +1504,7 @@ (set (match_operand:SI 0 "dest_reg_operand" "=w,w") (plus:SI (match_dup 1) (match_dup 2)))] "" - "ld%_.x.a%V4 %3,[%0,%S2]" + "ld%_.x.a%V4 %3,[%0,%2]" [(set_attr "type" "load,load") (set_attr "length" "4,8")]) @@ -1383,7 +1529,7 @@ (set (match_operand:SI 0 "dest_reg_operand" "=w,w") (plus:SI (match_dup 1) (match_dup 2)))] "" - "ld.a%V4 %3,[%0,%S2]" + "ld.a%V4 %3,[%0,%2]" [(set_attr "type" "load,load") (set_attr "length" "4,8")]) @@ -1407,7 +1553,7 @@ (set (match_operand:SI 0 "dest_reg_operand" "=w,w") (plus:SI (match_dup 1) (match_dup 2)))] "" - "ld.a%V4 %3,[%0,%S2]" + "ld.a%V4 %3,[%0,%2]" [(set_attr "type" "load,load") (set_attr "length" "4,8")]) @@ -1475,7 +1621,7 @@ && rtx_equal_p (operands[1], constm1_rtx) && GET_CODE (operands[3]) == LTU) return "sbc.cs %0,%0,%0"; - return "mov.%d3 %0,%S1"; + return "mov.%d3 %0,%1"; } [(set_attr "type" "cmove,cmove") (set_attr "length" "4,8")]) @@ -1636,7 +1782,7 @@ [(set (match_operand:HI 0 "dest_reg_operand" "") (zero_extend:HI (match_operand:QI 1 "nonvol_nonimm_operand" "")))] "" - "if (prepare_extend_operands (operands, ZERO_EXTEND, HImode)) DONE;" + "" ) (define_insn "*zero_extendqisi2_ac" @@ -1660,7 +1806,7 @@ [(set (match_operand:SI 0 "dest_reg_operand" "") (zero_extend:SI (match_operand:QI 1 "nonvol_nonimm_operand" "")))] "" - "if (prepare_extend_operands (operands, ZERO_EXTEND, SImode)) DONE;" + "" ) (define_insn "*zero_extendhisi2_i" @@ -1685,7 +1831,7 @@ [(set (match_operand:SI 0 "dest_reg_operand" "") (zero_extend:SI (match_operand:HI 1 "nonvol_nonimm_operand" "")))] "" - "if (prepare_extend_operands (operands, ZERO_EXTEND, SImode)) DONE;" + "" ) ;; Sign extension instructions. @@ -1708,7 +1854,7 @@ [(set (match_operand:HI 0 "dest_reg_operand" "") (sign_extend:HI (match_operand:QI 1 "nonvol_nonimm_operand" "")))] "" - "if (prepare_extend_operands (operands, SIGN_EXTEND, HImode)) DONE;" + "" ) (define_insn "*extendqisi2_ac" @@ -1728,7 +1874,7 @@ [(set (match_operand:SI 0 "dest_reg_operand" "") (sign_extend:SI (match_operand:QI 1 "nonvol_nonimm_operand" "")))] "" - "if (prepare_extend_operands (operands, SIGN_EXTEND, SImode)) DONE;" + "" ) (define_insn "*extendhisi2_i" @@ -1749,7 +1895,7 @@ [(set (match_operand:SI 0 "dest_reg_operand" "") (sign_extend:SI (match_operand:HI 1 "nonvol_nonimm_operand" "")))] "" - "if (prepare_extend_operands (operands, SIGN_EXTEND, SImode)) DONE;" + "" ) ;; Unary arithmetic insns @@ -2642,11 +2788,6 @@ { operands[2]=force_reg(SImode, operands[2]); } - else if (!TARGET_NO_SDATA_SET && small_data_pattern (operands[2], Pmode)) - { - operands[2] = force_reg (SImode, arc_rewrite_small_data (operands[2])); - } - ") (define_expand "adddi3" @@ -2850,8 +2991,6 @@ } if (flag_pic && arc_raw_symbolic_reference_mentioned_p (operands[c], false)) operands[c] = force_reg (SImode, operands[c]); - else if (!TARGET_NO_SDATA_SET && small_data_pattern (operands[c], Pmode)) - operands[c] = force_reg (SImode, arc_rewrite_small_data (operands[c])); }") ; the casesi expander might generate a sub of zero, so we have to recognize it. @@ -3034,30 +3173,17 @@ (set (match_dup 3) (match_dup 4))]) (define_insn "*add_n" - [(set (match_operand:SI 0 "dest_reg_operand" "=Rcqq,Rcw,W,W,w,w") - (plus:SI (ashift:SI (match_operand:SI 1 "register_operand" "Rcqq,c,c,c,c,c") - (match_operand:SI 2 "_1_2_3_operand" "")) - (match_operand:SI 3 "nonmemory_operand" "0,0,c,?Cal,?c,??Cal")))] - "" - "add%c2%? %0,%3,%1%&" + [(set (match_operand:SI 0 "dest_reg_operand" "=q,r,r") + (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "q,r,r") + (match_operand:SI 2 "_2_4_8_operand" "")) + (match_operand:SI 3 "nonmemory_operand" "0,r,Csz")))] + "" + "add%z2%?\\t%0,%3,%1%&" [(set_attr "type" "shift") - (set_attr "length" "*,4,4,8,4,8") - (set_attr "predicable" "yes,yes,no,no,no,no") - (set_attr "cond" "canuse,canuse,nocond,nocond,nocond,nocond") - (set_attr "iscompact" "maybe,false,false,false,false,false")]) - -(define_insn "*add_n" - [(set (match_operand:SI 0 "dest_reg_operand" "=Rcqq,Rcw,W,W,w,w") - (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "Rcqq,c,c,c,c,c") - (match_operand:SI 2 "_2_4_8_operand" "")) - (match_operand:SI 3 "nonmemory_operand" "0,0,c,?Cal,?c,??Cal")))] - "" - "add%z2%? %0,%3,%1%&" - [(set_attr "type" "shift") - (set_attr "length" "*,4,4,8,4,8") - (set_attr "predicable" "yes,yes,no,no,no,no") - (set_attr "cond" "canuse,canuse,nocond,nocond,nocond,nocond") - (set_attr "iscompact" "maybe,false,false,false,false,false")]) + (set_attr "length" "*,4,8") + (set_attr "predicable" "yes,no,no") + (set_attr "cond" "canuse,nocond,nocond") + (set_attr "iscompact" "maybe,false,false")]) ;; N.B. sub[123] has the operands of the MINUS in the opposite order from ;; what synth_mult likes. @@ -3140,7 +3266,7 @@ "@ bset%? %0,%1,%2 ;;peep2, constr 1 bset %0,%1,%2 ;;peep2, constr 2 - bset %0,%S1,%2 ;;peep2, constr 3" + bset %0,%1,%2 ;;peep2, constr 3" [(set_attr "length" "4,4,8") (set_attr "predicable" "yes,no,no") (set_attr "cond" "canuse,nocond,nocond")] @@ -3156,7 +3282,7 @@ "@ bxor%? %0,%1,%2 bxor %0,%1,%2 - bxor %0,%S1,%2" + bxor %0,%1,%2" [(set_attr "length" "4,4,8") (set_attr "predicable" "yes,no,no") (set_attr "cond" "canuse,nocond,nocond")] @@ -3172,7 +3298,7 @@ "@ bclr%? %0,%1,%2 bclr %0,%1,%2 - bclr %0,%S1,%2" + bclr %0,%1,%2" [(set_attr "length" "4,4,8") (set_attr "predicable" "yes,no,no") (set_attr "cond" "canuse,nocond,nocond")] @@ -3188,9 +3314,9 @@ (const_int -1))))] "" "@ - bmsk%? %0,%S1,%2 + bmsk%? %0,%1,%2 bmsk %0,%1,%2 - bmsk %0,%S1,%2" + bmsk %0,%1,%2" [(set_attr "length" "4,4,8") (set_attr "predicable" "yes,no,no") (set_attr "cond" "canuse,nocond,nocond")] @@ -3207,8 +3333,7 @@ "" "if (!satisfies_constraint_Cux (operands[2])) operands[1] = force_reg (SImode, operands[1]); - else if (!TARGET_NO_SDATA_SET && small_data_pattern (operands[1], Pmode)) - operands[1] = arc_rewrite_small_data (operands[1]);") + ") (define_insn "andsi3_i" [(set (match_operand:SI 0 "dest_reg_operand" "=Rcqq,Rcq,Rcqq,Rcqq,Rcqq,Rcw,Rcw, Rcw,Rcw,Rcw,Rcw, w, w, w, w,Rrq,w,Rcw, w,W") @@ -3302,10 +3427,10 @@ bic%? %0, %2, %1%& ;;constraint 0 bic%? %0,%2,%1 ;;constraint 1 bic %0,%2,%1 ;;constraint 2, FIXME: will it ever get generated ??? - bic%? %0,%2,%S1 ;;constraint 3, FIXME: will it ever get generated ??? + bic%? %0,%2,%1 ;;constraint 3, FIXME: will it ever get generated ??? bic %0,%2,%1 ;;constraint 4 - bic %0,%2,%S1 ;;constraint 5, FIXME: will it ever get generated ??? - bic %0,%S2,%1 ;;constraint 6" + bic %0,%2,%1 ;;constraint 5, FIXME: will it ever get generated ??? + bic %0,%2,%1 ;;constraint 6" [(set_attr "length" "*,4,4,8,4,8,8") (set_attr "iscompact" "maybe, false, false, false, false, false, false") (set_attr "predicable" "no,yes,no,yes,no,no,no") @@ -3475,7 +3600,7 @@ ; provide one alternatice for this, without condexec support. (define_insn "*ashlsi3_insn" [(set (match_operand:SI 0 "dest_reg_operand" "=Rcq,Rcqq,Rcqq,Rcw, w, w") - (ashift:SI (match_operand:SI 1 "nonmemory_operand" "!0,Rcqq, 0, 0, c,cCal") + (ashift:SI (match_operand:SI 1 "nonmemory_operand" "!0,Rcqq, 0, 0, c,cCsz") (match_operand:SI 2 "nonmemory_operand" "K, K,RcqqM, cL,cL,cCal")))] "TARGET_BARREL_SHIFTER && (register_operand (operands[1], SImode) @@ -3488,7 +3613,7 @@ (define_insn "*ashrsi3_insn" [(set (match_operand:SI 0 "dest_reg_operand" "=Rcq,Rcqq,Rcqq,Rcw, w, w") - (ashiftrt:SI (match_operand:SI 1 "nonmemory_operand" "!0,Rcqq, 0, 0, c,cCal") + (ashiftrt:SI (match_operand:SI 1 "nonmemory_operand" "!0,Rcqq, 0, 0, c,cCsz") (match_operand:SI 2 "nonmemory_operand" "K, K,RcqqM, cL,cL,cCal")))] "TARGET_BARREL_SHIFTER && (register_operand (operands[1], SImode) @@ -3515,7 +3640,7 @@ (define_insn "rotrsi3" [(set (match_operand:SI 0 "dest_reg_operand" "=Rcw, w, w") - (rotatert:SI (match_operand:SI 1 "register_operand" " 0,cL,cCal") + (rotatert:SI (match_operand:SI 1 "register_operand" " 0,cL,cCsz") (match_operand:SI 2 "nonmemory_operand" "cL,cL,cCal")))] "TARGET_BARREL_SHIFTER" "ror%? %0,%1,%2" @@ -3636,7 +3761,7 @@ (compare:CC_C (match_operand:SI 0 "register_operand" "Rcqq,Rcqq, h, c,Rcqq, c") (match_operand:SI 1 "nonmemory_operand" "cO, hO,Cm1,cI, Cal,Cal")))] "" - "cmp%? %0,%S1%&" + "cmp%? %0,%1%&" [(set_attr "type" "compare") (set_attr "iscompact" "true,true,true,false,true_limm,false") (set_attr "cond" "set") @@ -3743,7 +3868,7 @@ * current_insn_predicate = 0; return \"mov%?.ne %0,%1\"; * current_insn_predicate = 0; return \"mov%?.ne %0,%1\"; mov.ne %0,%1 - mov.ne %0,%S1" + mov.ne %0,%1" [(set_attr "type" "cmove") (set_attr "iscompact" "true,true,true_limm,false,false") (set_attr "length" "2,2,6,4,8") @@ -3756,7 +3881,7 @@ (set (match_operand:SI 0 "dest_reg_operand" "=w,w") (match_operand:SI 1 "nonmemory_operand" "LRac,?Cal")))] "" - "mov.%d3 %0,%S1" + "mov.%d3 %0,%1" [(set_attr "type" "cmove") (set_attr "length" "4,8")]) @@ -4224,13 +4349,12 @@ } ") - ; Rcq, which is used in alternative 0, checks for conditional execution. ; At instruction output time, if it doesn't match and we end up with ; alternative 1 ("q"), that means that we can't use the short form. (define_insn "*call_i" [(call (mem:SI (match_operand:SI 0 - "call_address_operand" "Rcq,q,c,Cbp,Cbr,L,I,Cal")) + "call_address_operand" "Rcq,q,c,Cji,Csc,Cbp,Cbr,L,I,Cal")) (match_operand 1 "" "")) (clobber (reg:SI 31))] "" @@ -4238,15 +4362,17 @@ jl%!%* [%0]%& jl%!%* [%0]%& jl%!%* [%0] + jli_s %S0 + sjli %S0 bl%!%* %P0 bl%!%* %P0 - jl%!%* %S0 - jl%* %S0 - jl%! %S0" - [(set_attr "type" "call,call,call,call,call,call,call,call_no_delay_slot") - (set_attr "iscompact" "maybe,false,*,*,*,*,*,*") - (set_attr "predicable" "no,no,yes,yes,no,yes,no,yes") - (set_attr "length" "*,*,4,4,4,4,4,8")]) + jl%!%* %0 + jl%* %0 + jl%! %0" + [(set_attr "type" "call,call,call,call_no_delay_slot,call_no_delay_slot,call,call,call,call,call_no_delay_slot") + (set_attr "iscompact" "maybe,false,*,true,*,*,*,*,*,*") + (set_attr "predicable" "no,no,yes,no,no,yes,no,yes,no,yes") + (set_attr "length" "*,*,4,2,4,4,4,4,4,8")]) (define_expand "call_value" ;; operand 2 is stack_size_rtx @@ -4268,14 +4394,13 @@ XEXP (operands[1], 0) = force_reg (Pmode, callee); }") - ; Rcq, which is used in alternative 0, checks for conditional execution. ; At instruction output time, if it doesn't match and we end up with ; alternative 1 ("q"), that means that we can't use the short form. (define_insn "*call_value_i" - [(set (match_operand 0 "dest_reg_operand" "=Rcq,q,w, w, w,w,w, w") + [(set (match_operand 0 "dest_reg_operand" "=Rcq,q,w, w, w, w, w,w,w, w") (call (mem:SI (match_operand:SI 1 - "call_address_operand" "Rcq,q,c,Cbp,Cbr,L,I,Cal")) + "call_address_operand" "Rcq,q,c,Cji,Csc,Cbp,Cbr,L,I,Cal")) (match_operand 2 "" ""))) (clobber (reg:SI 31))] "" @@ -4283,20 +4408,29 @@ jl%!%* [%1]%& jl%!%* [%1]%& jl%!%* [%1] + jli_s %S1 + sjli %S1 bl%!%* %P1;1 bl%!%* %P1;1 - jl%!%* %S1 - jl%* %S1 - jl%! %S1" - [(set_attr "type" "call,call,call,call,call,call,call,call_no_delay_slot") - (set_attr "iscompact" "maybe,false,*,*,*,*,*,*") - (set_attr "predicable" "no,no,yes,yes,no,yes,no,yes") - (set_attr "length" "*,*,4,4,4,4,4,8")]) + jl%!%* %1 + jl%* %1 + jl%! %1" + [(set_attr "type" "call,call,call,call_no_delay_slot,call_no_delay_slot,call,call,call,call,call_no_delay_slot") + (set_attr "iscompact" "maybe,false,*,true,false,*,*,*,*,*") + (set_attr "predicable" "no,no,yes,no,no,yes,no,yes,no,yes") + (set_attr "length" "*,*,4,2,4,4,4,4,4,8")]) ; There is a bl_s instruction (16 bit opcode branch-and-link), but we can't ; use it for lack of inter-procedural branch shortening. ; Link-time relaxation would help... +(define_insn "trap" + [(trap_if (const_int 1) (const_int 0))] + "!TARGET_ARC600_FAMILY" + "trap_s\\t5" + [(set_attr "type" "misc") + (set_attr "length" "2")]) + (define_insn "nop" [(const_int 0)] "" @@ -4311,17 +4445,16 @@ "" "nop%?" [(set_attr "type" "misc") - (set_attr "iscompact" "true") - (set_attr "length" "2")]) - -;; Special pattern to flush the icache. -;; ??? Not sure what to do here. Some ARC's are known to support this. - -(define_insn "flush_icache" - [(unspec_volatile [(match_operand:SI 0 "memory_operand" "m")] 0)] - "" - "* return \"\";" - [(set_attr "type" "misc")]) + (set_attr "iscompact" "maybe") + (set_attr "length" "*")]) + +(define_insn "blockage" + [(unspec_volatile [(const_int 0)] VUNSPEC_ARC_BLOCKAGE)] + "" + "" + [(set_attr "length" "0") + (set_attr "type" "block")] +) ;; Split up troublesome insns for better scheduling. @@ -4348,16 +4481,16 @@ (define_peephole2 [(set (match_operand:SI 0 "dest_reg_operand" "") (ashift:SI (match_operand:SI 1 "register_operand" "") - (match_operand:SI 2 "const_int_operand" ""))) + (match_operand:SI 2 "_1_2_3_operand" ""))) (set (match_operand:SI 3 "dest_reg_operand" "") (plus:SI (match_operand:SI 4 "nonmemory_operand" "") (match_operand:SI 5 "nonmemory_operand" "")))] - "(INTVAL (operands[2]) == 1 - || INTVAL (operands[2]) == 2 - || INTVAL (operands[2]) == 3) - && (true_regnum (operands[4]) == true_regnum (operands[0]) + "(true_regnum (operands[4]) == true_regnum (operands[0]) || true_regnum (operands[5]) == true_regnum (operands[0])) - && (peep2_reg_dead_p (2, operands[0]) || (true_regnum (operands[3]) == true_regnum (operands[0])))" + && (peep2_reg_dead_p (2, operands[0]) + || (true_regnum (operands[3]) == true_regnum (operands[0]))) + && !(optimize_size && satisfies_constraint_I (operands[4])) + && !(optimize_size && satisfies_constraint_I (operands[5]))" ;; the preparation statements take care to put proper operand in operands[4] ;; operands[4] will always contain the correct operand. This is added to satisfy commutativity [(set (match_dup 3) @@ -4465,7 +4598,7 @@ "TARGET_NORM" "@ norm \t%0, %1 - norm \t%0, %S1" + norm \t%0, %1" [(set_attr "length" "4,8") (set_attr "type" "two_cycle_core,two_cycle_core")]) @@ -4477,7 +4610,7 @@ "TARGET_NORM" "@ norm.f\t%0, %1 - norm.f\t%0, %S1" + norm.f\t%0, %1" [(set_attr "length" "4,8") (set_attr "type" "two_cycle_core,two_cycle_core")]) @@ -4497,7 +4630,7 @@ "TARGET_NORM" "@ norm%_ \t%0, %1 - norm%_ \t%0, %S1" + norm%_ \t%0, %1" [(set_attr "length" "4,8") (set_attr "type" "two_cycle_core,two_cycle_core")]) @@ -4586,7 +4719,7 @@ "TARGET_SWAP" "@ swap \t%0, %1 - swap \t%0, %S1 + swap \t%0, %1 swap \t%0, %1" [(set_attr "length" "4,8,4") (set_attr "type" "two_cycle_core,two_cycle_core,two_cycle_core")]) @@ -4599,8 +4732,8 @@ "TARGET_ARC700 || TARGET_EA_SET" "@ divaw \t%0, %1, %2 - divaw \t%0, %S1, %2 - divaw \t%0, %1, %S2" + divaw \t%0, %1, %2 + divaw \t%0, %1, %2" [(set_attr "length" "4,8,8") (set_attr "type" "divaw,divaw,divaw")]) @@ -4611,7 +4744,7 @@ "@ flag%? %0 flag %0 - flag%? %S0" + flag%? %0" [(set_attr "length" "4,4,8") (set_attr "type" "misc,misc,misc") (set_attr "predicable" "yes,no,yes") @@ -4658,9 +4791,9 @@ (define_insn "sleep" - [(unspec_volatile [(match_operand:SI 0 "immediate_operand" "L")] + [(unspec_volatile [(match_operand:SI 0 "nonmemory_operand" "Lr")] VUNSPEC_ARC_SLEEP)] - "check_if_valid_sleep_operand(operands,0)" + "" "sleep %0" [(set_attr "length" "4") (set_attr "type" "misc")]) @@ -4705,7 +4838,7 @@ (match_operand:SI 1 "general_operand" "Ir,I,HCal,r")] VUNSPEC_ARC_SR)] "" - "sr\t%S0, [%1]" + "sr\t%0, [%1]" [(set_attr "length" "8,4,8,4") (set_attr "type" "sr,sr,sr,sr")]) @@ -4866,8 +4999,6 @@ { return \"rtie\"; } - if (TARGET_PAD_RETURN) - arc_pad_return (); output_asm_insn (\"j%!%* [%0]%&\", ®); return \"\"; } @@ -4911,8 +5042,6 @@ arc_return_address_register (arc_compute_function_type (cfun))); - if (TARGET_PAD_RETURN) - arc_pad_return (); output_asm_insn (\"j%d0%!%# [%1]%&\", xop); /* record the condition in case there is a delay insn. */ arc_ccfsm_record_condition (xop[0], false, insn, 0); @@ -4935,39 +5064,6 @@ (const_int 4)] (const_int 2)))]) -(define_insn_and_split "eh_return" - [(eh_return) - (use (match_operand:SI 0 "move_src_operand" "rC32,mCalCpc")) - (clobber (match_scratch:SI 1 "=X,r")) - (clobber (match_scratch:SI 2 "=&r,r"))] - "" - "#" - "reload_completed" - [(set (match_dup 2) (match_dup 0))] -{ - int offs = arc_return_slot_offset (); - - if (offs < 0) - operands[2] = gen_rtx_REG (Pmode, RETURN_ADDR_REGNUM); - else - { - if (!register_operand (operands[0], Pmode) - && !satisfies_constraint_C32 (operands[0])) - { - emit_move_insn (operands[1], operands[0]); - operands[0] = operands[1]; - } - rtx addr = plus_constant (Pmode, stack_pointer_rtx, offs); - if (!strict_memory_address_p (Pmode, addr)) - { - emit_move_insn (operands[2], addr); - addr = operands[2]; - } - operands[2] = gen_frame_mem (Pmode, addr); - } -} - [(set_attr "length" "12")]) - ;; ??? #ifdefs in function.c require the presence of this pattern, with a ;; non-constant predicate. (define_expand "return" @@ -5211,11 +5307,11 @@ (plus:SI (match_dup 0) (const_int -1))) (clobber (match_scratch:SI 2 "=X,r"))] - "TARGET_V2" + "TARGET_DBNZ" "@ dbnz%#\\t%0,%l1 #" - "TARGET_V2 && reload_completed && memory_operand (operands[0], SImode)" + "TARGET_DBNZ && reload_completed && memory_operand (operands[0], SImode)" [(set (match_dup 2) (match_dup 0)) (set (match_dup 2) (plus:SI (match_dup 2) (const_int -1))) (set (reg:CC CC_REG) (compare:CC (match_dup 2) (const_int 0))) @@ -5314,7 +5410,7 @@ ;; ??? Should this use arc_output_libcall and set is_sfunc? (define_insn "*millicode_thunk_st" [(match_parallel 0 "millicode_store_operation" - [(set (mem:SI (reg:SI SP_REG)) (reg:SI 13))])] + [(set (mem:SI (reg:SI SP_REG)) (reg:SI 13))])] "" { output_asm_insn ("bl%* __st_r13_to_%0", @@ -5326,7 +5422,7 @@ (define_insn "*millicode_thunk_ld" [(match_parallel 0 "millicode_load_clob_operation" - [(set (reg:SI 13) (mem:SI (reg:SI SP_REG)))])] + [(set (reg:SI 13) (mem:SI (reg:SI SP_REG)))])] "" { output_asm_insn ("bl%* __ld_r13_to_%0", @@ -5339,9 +5435,9 @@ ; the sibthunk restores blink, so we use the return rtx. (define_insn "*millicode_sibthunk_ld" [(match_parallel 0 "millicode_load_operation" - [(return) - (set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG) (reg:SI 12))) - (set (reg:SI 13) (mem:SI (reg:SI SP_REG)))])] + [(return) + (set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG) (reg:SI 12))) + (set (reg:SI 13) (mem:SI (reg:SI SP_REG)))])] "" { output_asm_insn ("b%* __ld_r13_to_%0_ret", @@ -5635,23 +5731,22 @@ DONE; }) - (define_insn "extzvsi" - [(set (match_operand:SI 0 "register_operand" "=r , r , r, r, r") - (zero_extract:SI (match_operand:SI 1 "register_operand" "0 , r , 0, 0, r") - (match_operand:SI 2 "const_int_operand" "C3p, C3p, i, i, i") - (match_operand:SI 3 "const_int_operand" "i , i , i, i, i")))] + [(set (match_operand:SI 0 "register_operand" "=r , r,r,r") + (zero_extract:SI (match_operand:SI 1 "register_operand" "0 , r,r,0") + (match_operand:SI 2 "const_int_operand" "C3p,C3p,n,n") + (match_operand:SI 3 "const_int_operand" "n , n,n,n")))] "TARGET_HS && TARGET_BARREL_SHIFTER" { int assemble_op2 = (((INTVAL (operands[2]) - 1) & 0x1f) << 5) | (INTVAL (operands[3]) & 0x1f); operands[2] = GEN_INT (assemble_op2); - return "xbfu%? %0,%1,%2"; + return "xbfu%?\\t%0,%1,%2"; } [(set_attr "type" "shift") (set_attr "iscompact" "false") - (set_attr "length" "4,4,4,8,8") - (set_attr "predicable" "yes,no,no,yes,no") - (set_attr "cond" "canuse,nocond,nocond,canuse,nocond")]) + (set_attr "length" "4,4,8,8") + (set_attr "predicable" "yes,no,no,yes") + (set_attr "cond" "canuse,nocond,nocond,canuse_limm")]) (define_insn "kflag" [(unspec_volatile [(match_operand:SI 0 "nonmemory_operand" "rL,I,Cal")] @@ -5660,7 +5755,7 @@ "@ kflag%? %0 kflag %0 - kflag%? %S0" + kflag%? %0" [(set_attr "length" "4,4,8") (set_attr "type" "misc,misc,misc") (set_attr "predicable" "yes,no,yes") @@ -5682,7 +5777,7 @@ "TARGET_NORM && TARGET_V2" "@ ffs \t%0, %1 - ffs \t%0, %S1" + ffs \t%0, %1" [(set_attr "length" "4,8") (set_attr "type" "two_cycle_core,two_cycle_core")]) @@ -5695,7 +5790,7 @@ "TARGET_NORM && TARGET_V2" "@ ffs.f\t%0, %1 - ffs.f\t%0, %S1" + ffs.f\t%0, %1" [(set_attr "length" "4,8") (set_attr "type" "two_cycle_core,two_cycle_core")]) @@ -5716,21 +5811,19 @@ }) (define_insn "fls" - [(set (match_operand:SI 0 "dest_reg_operand" "=w,w") - (unspec:SI [(match_operand:SI 1 "general_operand" "cL,Cal")] + [(set (match_operand:SI 0 "register_operand" "=r,r") + (unspec:SI [(match_operand:SI 1 "nonmemory_operand" "rL,Cal")] UNSPEC_ARC_FLS))] "TARGET_NORM && TARGET_V2" - "@ - fls \t%0, %1 - fls \t%0, %S1" + "fls\\t%0,%1" [(set_attr "length" "4,8") (set_attr "type" "two_cycle_core,two_cycle_core")]) (define_insn "seti" - [(unspec_volatile:SI [(match_operand:SI 0 "general_operand" "rL")] + [(unspec_volatile:SI [(match_operand:SI 0 "nonmemory_operand" "rL")] VUNSPEC_ARC_SETI)] "TARGET_V2" - "seti %0" + "seti\\t%0" [(set_attr "length" "4") (set_attr "type" "misc")]) @@ -6177,13 +6270,25 @@ [(set_attr "length" "0")]) ;; MAC and DMPY instructions -(define_insn_and_split "maddsidi4" +(define_expand "maddsidi4" + [(match_operand:DI 0 "register_operand" "") + (match_operand:SI 1 "register_operand" "") + (match_operand:SI 2 "extend_operand" "") + (match_operand:DI 3 "register_operand" "")] + "TARGET_PLUS_DMPY" + "{ + emit_insn (gen_maddsidi4_split (operands[0], operands[1], operands[2], operands[3])); + DONE; + }") + +(define_insn_and_split "maddsidi4_split" [(set (match_operand:DI 0 "register_operand" "=r") (plus:DI (mult:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "%r")) (sign_extend:DI (match_operand:SI 2 "extend_operand" "ri"))) - (match_operand:DI 3 "register_operand" "r")))] + (match_operand:DI 3 "register_operand" "r"))) + (clobber (reg:DI ARCV2_ACC))] "TARGET_PLUS_DMPY" "#" "TARGET_PLUS_DMPY && reload_completed" @@ -6191,7 +6296,7 @@ "{ rtx acc_reg = gen_rtx_REG (DImode, ACC_REG_FIRST); emit_move_insn (acc_reg, operands[3]); - if (TARGET_PLUS_MACD) + if (TARGET_PLUS_MACD && even_register_operand (operands[0], DImode)) emit_insn (gen_macd (operands[0], operands[1], operands[2])); else { @@ -6265,13 +6370,25 @@ (set_attr "predicable" "no") (set_attr "cond" "nocond")]) -(define_insn_and_split "umaddsidi4" +(define_expand "umaddsidi4" + [(match_operand:DI 0 "register_operand" "") + (match_operand:SI 1 "register_operand" "") + (match_operand:SI 2 "extend_operand" "") + (match_operand:DI 3 "register_operand" "")] + "TARGET_PLUS_DMPY" + "{ + emit_insn (gen_umaddsidi4_split (operands[0], operands[1], operands[2], operands[3])); + DONE; + }") + +(define_insn_and_split "umaddsidi4_split" [(set (match_operand:DI 0 "register_operand" "=r") (plus:DI (mult:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "%r")) (zero_extend:DI (match_operand:SI 2 "extend_operand" "ri"))) - (match_operand:DI 3 "register_operand" "r")))] + (match_operand:DI 3 "register_operand" "r"))) + (clobber (reg:DI ARCV2_ACC))] "TARGET_PLUS_DMPY" "#" "TARGET_PLUS_DMPY && reload_completed" @@ -6279,7 +6396,7 @@ "{ rtx acc_reg = gen_rtx_REG (DImode, ACC_REG_FIRST); emit_move_insn (acc_reg, operands[3]); - if (TARGET_PLUS_MACD) + if (TARGET_PLUS_MACD && even_register_operand (operands[0], DImode)) emit_insn (gen_macdu (operands[0], operands[1], operands[2])); else { @@ -6426,6 +6543,77 @@ (set_attr "type" "block")] ) +(define_insn "*add_shift" + [(set (match_operand:SI 0 "register_operand" "=q,r,r") + (plus:SI (ashift:SI (match_operand:SI 1 "register_operand" "q,r,r") + (match_operand:SI 2 "_1_2_3_operand" "")) + (match_operand:SI 3 "nonmemory_operand" "0,r,Csz")))] + "" + "add%2%?\\t%0,%3,%1" + [(set_attr "length" "*,4,8") + (set_attr "predicable" "yes,no,no") + (set_attr "iscompact" "maybe,false,false") + (set_attr "cond" "canuse,nocond,nocond")]) + +(define_insn "*add_shift2" + [(set (match_operand:SI 0 "register_operand" "=q,r,r") + (plus:SI (match_operand:SI 1 "nonmemory_operand" "0,r,Cal") + (ashift:SI (match_operand:SI 2 "register_operand" "q,r,r") + (match_operand:SI 3 "_1_2_3_operand" ""))))] + "" + "add%3%?\\t%0,%1,%2" + [(set_attr "length" "*,4,8") + (set_attr "predicable" "yes,no,no") + (set_attr "iscompact" "maybe,false,false") + (set_attr "cond" "canuse,nocond,nocond")]) + +(define_insn "*sub_shift" + [(set (match_operand:SI 0"register_operand" "=r,r,r") + (minus:SI (match_operand:SI 1 "nonmemory_operand" "0,r,Cal") + (ashift:SI (match_operand:SI 2 "register_operand" "r,r,r") + (match_operand:SI 3 "_1_2_3_operand" ""))))] + "" + "sub%3\\t%0,%1,%2" + [(set_attr "length" "4,4,8") + (set_attr "cond" "canuse,nocond,nocond") + (set_attr "predicable" "yes,no,no")]) + +(define_insn "*sub_shift_cmp0_noout" + [(set (match_operand 0 "cc_set_register" "") + (compare:CC + (minus:SI (match_operand:SI 1 "register_operand" "r") + (ashift:SI (match_operand:SI 2 "register_operand" "r") + (match_operand:SI 3 "_1_2_3_operand" ""))) + (const_int 0)))] + "" + "sub%3.f\\t0,%1,%2" + [(set_attr "length" "4")]) + +(define_insn "*compare_si_ashiftsi" + [(set (match_operand 0 "cc_set_register" "") + (compare:CC (match_operand:SI 1 "register_operand" "r") + (ashift:SI (match_operand:SI 2 "register_operand" "r") + (match_operand:SI 3 "_1_2_3_operand" ""))))] + "" + "sub%3.f\\t0,%1,%2" + [(set_attr "length" "4")]) + +;; Convert the sequence +;; asl rd,rn,_1_2_3 +;; cmp ra,rd +;; into +;; sub{123}.f 0,ra,rn +(define_peephole2 + [(set (match_operand:SI 0 "register_operand" "") + (ashift:SI (match_operand:SI 1 "register_operand" "") + (match_operand:SI 2 "_1_2_3_operand" ""))) + (set (reg:CC CC_REG) + (compare:CC (match_operand:SI 3 "register_operand" "") + (match_dup 0)))] + "peep2_reg_dead_p (2, operands[0])" + [(set (reg:CC CC_REG) (compare:CC (match_dup 3) + (ashift:SI (match_dup 1) (match_dup 2))))]) + ;; include the arc-FPX instructions (include "fpx.md")