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comparison gcc/config/arm/arm-fixed.md @ 131:84e7813d76e9

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gcc-8.2
author mir3636
date Thu, 25 Oct 2018 07:37:49 +0900
parents 04ced10e8804
children 1830386684a0
comparison
equal deleted inserted replaced
111:04ced10e8804 131:84e7813d76e9
1 ;; Copyright (C) 2011-2017 Free Software Foundation, Inc. 1 ;; Copyright (C) 2011-2018 Free Software Foundation, Inc.
2 ;; 2 ;;
3 ;; This file is part of GCC. 3 ;; This file is part of GCC.
4 ;; 4 ;;
5 ;; GCC is free software; you can redistribute it and/or modify it 5 ;; GCC is free software; you can redistribute it and/or modify it
6 ;; under the terms of the GNU General Public License as published 6 ;; under the terms of the GNU General Public License as published
33 (plus:ADDSUB (match_operand:ADDSUB 1 "s_register_operand" "r") 33 (plus:ADDSUB (match_operand:ADDSUB 1 "s_register_operand" "r")
34 (match_operand:ADDSUB 2 "s_register_operand" "r")))] 34 (match_operand:ADDSUB 2 "s_register_operand" "r")))]
35 "TARGET_INT_SIMD" 35 "TARGET_INT_SIMD"
36 "sadd<qaddsub_suf>%?\\t%0, %1, %2" 36 "sadd<qaddsub_suf>%?\\t%0, %1, %2"
37 [(set_attr "predicable" "yes") 37 [(set_attr "predicable" "yes")
38 (set_attr "predicable_short_it" "no")
39 (set_attr "type" "alu_dsp_reg")]) 38 (set_attr "type" "alu_dsp_reg")])
40 39
41 (define_insn "usadd<mode>3" 40 (define_insn "usadd<mode>3"
42 [(set (match_operand:UQADDSUB 0 "s_register_operand" "=r") 41 [(set (match_operand:UQADDSUB 0 "s_register_operand" "=r")
43 (us_plus:UQADDSUB (match_operand:UQADDSUB 1 "s_register_operand" "r") 42 (us_plus:UQADDSUB (match_operand:UQADDSUB 1 "s_register_operand" "r")
44 (match_operand:UQADDSUB 2 "s_register_operand" "r")))] 43 (match_operand:UQADDSUB 2 "s_register_operand" "r")))]
45 "TARGET_INT_SIMD" 44 "TARGET_INT_SIMD"
46 "uqadd<qaddsub_suf>%?\\t%0, %1, %2" 45 "uqadd<qaddsub_suf>%?\\t%0, %1, %2"
47 [(set_attr "predicable" "yes") 46 [(set_attr "predicable" "yes")
48 (set_attr "predicable_short_it" "no")
49 (set_attr "type" "alu_dsp_reg")]) 47 (set_attr "type" "alu_dsp_reg")])
50 48
51 (define_insn "ssadd<mode>3" 49 (define_insn "ssadd<mode>3"
52 [(set (match_operand:QADDSUB 0 "s_register_operand" "=r") 50 [(set (match_operand:QADDSUB 0 "s_register_operand" "=r")
53 (ss_plus:QADDSUB (match_operand:QADDSUB 1 "s_register_operand" "r") 51 (ss_plus:QADDSUB (match_operand:QADDSUB 1 "s_register_operand" "r")
54 (match_operand:QADDSUB 2 "s_register_operand" "r")))] 52 (match_operand:QADDSUB 2 "s_register_operand" "r")))]
55 "TARGET_INT_SIMD" 53 "TARGET_INT_SIMD"
56 "qadd<qaddsub_suf>%?\\t%0, %1, %2" 54 "qadd<qaddsub_suf>%?\\t%0, %1, %2"
57 [(set_attr "predicable" "yes") 55 [(set_attr "predicable" "yes")
58 (set_attr "predicable_short_it" "no")
59 (set_attr "type" "alu_dsp_reg")]) 56 (set_attr "type" "alu_dsp_reg")])
60 57
61 (define_insn "sub<mode>3" 58 (define_insn "sub<mode>3"
62 [(set (match_operand:FIXED 0 "s_register_operand" "=l,r") 59 [(set (match_operand:FIXED 0 "s_register_operand" "=l,r")
63 (minus:FIXED (match_operand:FIXED 1 "s_register_operand" "l,r") 60 (minus:FIXED (match_operand:FIXED 1 "s_register_operand" "l,r")
73 (minus:ADDSUB (match_operand:ADDSUB 1 "s_register_operand" "r") 70 (minus:ADDSUB (match_operand:ADDSUB 1 "s_register_operand" "r")
74 (match_operand:ADDSUB 2 "s_register_operand" "r")))] 71 (match_operand:ADDSUB 2 "s_register_operand" "r")))]
75 "TARGET_INT_SIMD" 72 "TARGET_INT_SIMD"
76 "ssub<qaddsub_suf>%?\\t%0, %1, %2" 73 "ssub<qaddsub_suf>%?\\t%0, %1, %2"
77 [(set_attr "predicable" "yes") 74 [(set_attr "predicable" "yes")
78 (set_attr "predicable_short_it" "no")
79 (set_attr "type" "alu_dsp_reg")]) 75 (set_attr "type" "alu_dsp_reg")])
80 76
81 (define_insn "ussub<mode>3" 77 (define_insn "ussub<mode>3"
82 [(set (match_operand:UQADDSUB 0 "s_register_operand" "=r") 78 [(set (match_operand:UQADDSUB 0 "s_register_operand" "=r")
83 (us_minus:UQADDSUB 79 (us_minus:UQADDSUB
84 (match_operand:UQADDSUB 1 "s_register_operand" "r") 80 (match_operand:UQADDSUB 1 "s_register_operand" "r")
85 (match_operand:UQADDSUB 2 "s_register_operand" "r")))] 81 (match_operand:UQADDSUB 2 "s_register_operand" "r")))]
86 "TARGET_INT_SIMD" 82 "TARGET_INT_SIMD"
87 "uqsub<qaddsub_suf>%?\\t%0, %1, %2" 83 "uqsub<qaddsub_suf>%?\\t%0, %1, %2"
88 [(set_attr "predicable" "yes") 84 [(set_attr "predicable" "yes")
89 (set_attr "predicable_short_it" "no")
90 (set_attr "type" "alu_dsp_reg")]) 85 (set_attr "type" "alu_dsp_reg")])
91 86
92 (define_insn "sssub<mode>3" 87 (define_insn "sssub<mode>3"
93 [(set (match_operand:QADDSUB 0 "s_register_operand" "=r") 88 [(set (match_operand:QADDSUB 0 "s_register_operand" "=r")
94 (ss_minus:QADDSUB (match_operand:QADDSUB 1 "s_register_operand" "r") 89 (ss_minus:QADDSUB (match_operand:QADDSUB 1 "s_register_operand" "r")
95 (match_operand:QADDSUB 2 "s_register_operand" "r")))] 90 (match_operand:QADDSUB 2 "s_register_operand" "r")))]
96 "TARGET_INT_SIMD" 91 "TARGET_INT_SIMD"
97 "qsub<qaddsub_suf>%?\\t%0, %1, %2" 92 "qsub<qaddsub_suf>%?\\t%0, %1, %2"
98 [(set_attr "predicable" "yes") 93 [(set_attr "predicable" "yes")
99 (set_attr "predicable_short_it" "no")
100 (set_attr "type" "alu_dsp_reg")]) 94 (set_attr "type" "alu_dsp_reg")])
101 95
102 ;; Fractional multiplies. 96 ;; Fractional multiplies.
103 97
104 ; Note: none of these do any rounding. 98 ; Note: none of these do any rounding.
141 135
142 (define_expand "mulsq3" 136 (define_expand "mulsq3"
143 [(set (match_operand:SQ 0 "s_register_operand" "") 137 [(set (match_operand:SQ 0 "s_register_operand" "")
144 (mult:SQ (match_operand:SQ 1 "s_register_operand" "") 138 (mult:SQ (match_operand:SQ 1 "s_register_operand" "")
145 (match_operand:SQ 2 "s_register_operand" "")))] 139 (match_operand:SQ 2 "s_register_operand" "")))]
146 "TARGET_32BIT && arm_arch3m" 140 "TARGET_32BIT"
147 { 141 {
148 rtx tmp1 = gen_reg_rtx (DImode); 142 rtx tmp1 = gen_reg_rtx (DImode);
149 rtx tmp2 = gen_reg_rtx (SImode); 143 rtx tmp2 = gen_reg_rtx (SImode);
150 rtx tmp3 = gen_reg_rtx (SImode); 144 rtx tmp3 = gen_reg_rtx (SImode);
151 145
163 157
164 (define_expand "mulsa3" 158 (define_expand "mulsa3"
165 [(set (match_operand:SA 0 "s_register_operand" "") 159 [(set (match_operand:SA 0 "s_register_operand" "")
166 (mult:SA (match_operand:SA 1 "s_register_operand" "") 160 (mult:SA (match_operand:SA 1 "s_register_operand" "")
167 (match_operand:SA 2 "s_register_operand" "")))] 161 (match_operand:SA 2 "s_register_operand" "")))]
168 "TARGET_32BIT && arm_arch3m" 162 "TARGET_32BIT"
169 { 163 {
170 rtx tmp1 = gen_reg_rtx (DImode); 164 rtx tmp1 = gen_reg_rtx (DImode);
171 rtx tmp2 = gen_reg_rtx (SImode); 165 rtx tmp2 = gen_reg_rtx (SImode);
172 rtx tmp3 = gen_reg_rtx (SImode); 166 rtx tmp3 = gen_reg_rtx (SImode);
173 167
182 176
183 (define_expand "mulusa3" 177 (define_expand "mulusa3"
184 [(set (match_operand:USA 0 "s_register_operand" "") 178 [(set (match_operand:USA 0 "s_register_operand" "")
185 (mult:USA (match_operand:USA 1 "s_register_operand" "") 179 (mult:USA (match_operand:USA 1 "s_register_operand" "")
186 (match_operand:USA 2 "s_register_operand" "")))] 180 (match_operand:USA 2 "s_register_operand" "")))]
187 "TARGET_32BIT && arm_arch3m" 181 "TARGET_32BIT"
188 { 182 {
189 rtx tmp1 = gen_reg_rtx (DImode); 183 rtx tmp1 = gen_reg_rtx (DImode);
190 rtx tmp2 = gen_reg_rtx (SImode); 184 rtx tmp2 = gen_reg_rtx (SImode);
191 rtx tmp3 = gen_reg_rtx (SImode); 185 rtx tmp3 = gen_reg_rtx (SImode);
192 186
412 [(match_operand:SI 2 "s_register_operand" "r") 406 [(match_operand:SI 2 "s_register_operand" "r")
413 (match_operand:SI 3 "immediate_operand" "I")])))] 407 (match_operand:SI 3 "immediate_operand" "I")])))]
414 "TARGET_32BIT && arm_arch6" 408 "TARGET_32BIT && arm_arch6"
415 "ssat%?\\t%0, #16, %2%S1" 409 "ssat%?\\t%0, #16, %2%S1"
416 [(set_attr "predicable" "yes") 410 [(set_attr "predicable" "yes")
417 (set_attr "predicable_short_it" "no")
418 (set_attr "shift" "1") 411 (set_attr "shift" "1")
419 (set_attr "type" "alu_shift_imm")]) 412 (set_attr "type" "alu_shift_imm")])
420 413
421 (define_insn "arm_usatsihi" 414 (define_insn "arm_usatsihi"
422 [(set (match_operand:HI 0 "s_register_operand" "=r") 415 [(set (match_operand:HI 0 "s_register_operand" "=r")
423 (us_truncate:HI (match_operand:SI 1 "s_register_operand")))] 416 (us_truncate:HI (match_operand:SI 1 "s_register_operand")))]
424 "TARGET_INT_SIMD" 417 "TARGET_INT_SIMD"
425 "usat%?\\t%0, #16, %1" 418 "usat%?\\t%0, #16, %1"
426 [(set_attr "predicable" "yes") 419 [(set_attr "predicable" "yes")
427 (set_attr "predicable_short_it" "no")
428 (set_attr "type" "alu_imm")] 420 (set_attr "type" "alu_imm")]
429 ) 421 )