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comparison gcc/config/m68k/m68k.md @ 131:84e7813d76e9

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gcc-8.2
author mir3636
date Thu, 25 Oct 2018 07:37:49 +0900
parents 04ced10e8804
children 1830386684a0
comparison
equal deleted inserted replaced
111:04ced10e8804 131:84e7813d76e9
1 ;;- Machine description for GNU compiler, Motorola 68000 Version 1 ;;- Machine description for GNU compiler, Motorola 68000 Version
2 ;; Copyright (C) 1987-2017 Free Software Foundation, Inc. 2 ;; Copyright (C) 1987-2018 Free Software Foundation, Inc.
3 3
4 ;; This file is part of GCC. 4 ;; This file is part of GCC.
5 5
6 ;; GCC is free software; you can redistribute it and/or modify 6 ;; GCC is free software; you can redistribute it and/or modify
7 ;; it under the terms of the GNU General Public License as published by 7 ;; it under the terms of the GNU General Public License as published by
3238 (mult:DI (zero_extend:DI (match_operand:SI 2 "register_operand" "%1")) 3238 (mult:DI (zero_extend:DI (match_operand:SI 2 "register_operand" "%1"))
3239 (zero_extend:DI (match_operand:SI 3 "nonimmediate_operand" "dm"))) 3239 (zero_extend:DI (match_operand:SI 3 "nonimmediate_operand" "dm")))
3240 (const_int 32)))) 3240 (const_int 32))))
3241 (clobber (match_operand:SI 1 "register_operand" "=d"))] 3241 (clobber (match_operand:SI 1 "register_operand" "=d"))]
3242 "TARGET_68020 && !TUNE_68060 && !TARGET_COLDFIRE" 3242 "TARGET_68020 && !TUNE_68060 && !TARGET_COLDFIRE"
3243 "mulu%.l %3,%0:%1") 3243 {
3244 CC_STATUS_INIT;
3245 return "mulu%.l %3,%0:%1";
3246 })
3244 3247
3245 (define_insn "const_umulsi3_highpart" 3248 (define_insn "const_umulsi3_highpart"
3246 [(set (match_operand:SI 0 "register_operand" "=d") 3249 [(set (match_operand:SI 0 "register_operand" "=d")
3247 (truncate:SI 3250 (truncate:SI
3248 (lshiftrt:DI 3251 (lshiftrt:DI
3249 (mult:DI (zero_extend:DI (match_operand:SI 2 "register_operand" "1")) 3252 (mult:DI (zero_extend:DI (match_operand:SI 2 "register_operand" "1"))
3250 (match_operand:DI 3 "const_uint32_operand" "n")) 3253 (match_operand:DI 3 "const_uint32_operand" "n"))
3251 (const_int 32)))) 3254 (const_int 32))))
3252 (clobber (match_operand:SI 1 "register_operand" "=d"))] 3255 (clobber (match_operand:SI 1 "register_operand" "=d"))]
3253 "TARGET_68020 && !TUNE_68060 && !TARGET_COLDFIRE" 3256 "TARGET_68020 && !TUNE_68060 && !TARGET_COLDFIRE"
3254 "mulu%.l %3,%0:%1") 3257 {
3258 CC_STATUS_INIT;
3259 return "mulu%.l %3,%0:%1";
3260 })
3255 3261
3256 (define_expand "smulsi3_highpart" 3262 (define_expand "smulsi3_highpart"
3257 [(parallel 3263 [(parallel
3258 [(set (match_operand:SI 0 "register_operand" "") 3264 [(set (match_operand:SI 0 "register_operand" "")
3259 (truncate:SI 3265 (truncate:SI
3281 (mult:DI (sign_extend:DI (match_operand:SI 2 "register_operand" "%1")) 3287 (mult:DI (sign_extend:DI (match_operand:SI 2 "register_operand" "%1"))
3282 (sign_extend:DI (match_operand:SI 3 "nonimmediate_operand" "dm"))) 3288 (sign_extend:DI (match_operand:SI 3 "nonimmediate_operand" "dm")))
3283 (const_int 32)))) 3289 (const_int 32))))
3284 (clobber (match_operand:SI 1 "register_operand" "=d"))] 3290 (clobber (match_operand:SI 1 "register_operand" "=d"))]
3285 "TARGET_68020 && !TUNE_68060 && !TARGET_COLDFIRE" 3291 "TARGET_68020 && !TUNE_68060 && !TARGET_COLDFIRE"
3286 "muls%.l %3,%0:%1") 3292 {
3293 CC_STATUS_INIT;
3294 return "muls%.l %3,%0:%1";
3295 })
3287 3296
3288 (define_insn "const_smulsi3_highpart" 3297 (define_insn "const_smulsi3_highpart"
3289 [(set (match_operand:SI 0 "register_operand" "=d") 3298 [(set (match_operand:SI 0 "register_operand" "=d")
3290 (truncate:SI 3299 (truncate:SI
3291 (lshiftrt:DI 3300 (lshiftrt:DI
3292 (mult:DI (sign_extend:DI (match_operand:SI 2 "register_operand" "1")) 3301 (mult:DI (sign_extend:DI (match_operand:SI 2 "register_operand" "1"))
3293 (match_operand:DI 3 "const_sint32_operand" "n")) 3302 (match_operand:DI 3 "const_sint32_operand" "n"))
3294 (const_int 32)))) 3303 (const_int 32))))
3295 (clobber (match_operand:SI 1 "register_operand" "=d"))] 3304 (clobber (match_operand:SI 1 "register_operand" "=d"))]
3296 "TARGET_68020 && !TUNE_68060 && !TARGET_COLDFIRE" 3305 "TARGET_68020 && !TUNE_68060 && !TARGET_COLDFIRE"
3297 "muls%.l %3,%0:%1") 3306 {
3307 CC_STATUS_INIT;
3308 return "muls%.l %3,%0:%1";
3309 })
3298 3310
3299 (define_expand "mul<mode>3" 3311 (define_expand "mul<mode>3"
3300 [(set (match_operand:FP 0 "nonimmediate_operand" "") 3312 [(set (match_operand:FP 0 "nonimmediate_operand" "")
3301 (mult:FP (match_operand:FP 1 "general_operand" "") 3313 (mult:FP (match_operand:FP 1 "general_operand" "")
3302 (match_operand:FP 2 "general_operand" "")))] 3314 (match_operand:FP 2 "general_operand" "")))]
4681 (ashiftrt:DI (match_operand:DI 1 "register_operand" "0") 4693 (ashiftrt:DI (match_operand:DI 1 "register_operand" "0")
4682 (const_int 1)))] 4694 (const_int 1)))]
4683 "!TARGET_COLDFIRE" 4695 "!TARGET_COLDFIRE"
4684 { 4696 {
4685 operands[1] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1); 4697 operands[1] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
4698 CC_STATUS_INIT;
4686 return "asr%.l #1,%0\;roxr%.l #1,%1"; 4699 return "asr%.l #1,%0\;roxr%.l #1,%1";
4687 }) 4700 })
4688 4701
4689 (define_split 4702 (define_split
4690 [(set (match_operand:DI 0 "register_operand" "") 4703 [(set (match_operand:DI 0 "register_operand" "")
4917 (define_insn "*lshrdi3_const1" 4930 (define_insn "*lshrdi3_const1"
4918 [(set (match_operand:DI 0 "register_operand" "=d") 4931 [(set (match_operand:DI 0 "register_operand" "=d")
4919 (lshiftrt:DI (match_operand:DI 1 "register_operand" "0") 4932 (lshiftrt:DI (match_operand:DI 1 "register_operand" "0")
4920 (const_int 1)))] 4933 (const_int 1)))]
4921 "!TARGET_COLDFIRE" 4934 "!TARGET_COLDFIRE"
4922 "lsr%.l #1,%0\;roxr%.l #1,%R0") 4935 {
4936 CC_STATUS_INIT;
4937 return "lsr%.l #1,%0\;roxr%.l #1,%R0";
4938 })
4923 4939
4924 (define_split 4940 (define_split
4925 [(set (match_operand:DI 0 "register_operand" "") 4941 [(set (match_operand:DI 0 "register_operand" "")
4926 (lshiftrt:DI (match_operand:DI 1 "register_operand" "") 4942 (lshiftrt:DI (match_operand:DI 1 "register_operand" "")
4927 (const_int 2)))] 4943 (const_int 2)))]