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comparison gcc/config/nds32/constraints.md @ 131:84e7813d76e9

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gcc-8.2
author mir3636
date Thu, 25 Oct 2018 07:37:49 +0900
parents 04ced10e8804
children 1830386684a0
comparison
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111:04ced10e8804 131:84e7813d76e9
1 ;; Constraint definitions of Andes NDS32 cpu for GNU compiler 1 ;; Constraint definitions of Andes NDS32 cpu for GNU compiler
2 ;; Copyright (C) 2012-2017 Free Software Foundation, Inc. 2 ;; Copyright (C) 2012-2018 Free Software Foundation, Inc.
3 ;; Contributed by Andes Technology Corporation. 3 ;; Contributed by Andes Technology Corporation.
4 ;; 4 ;;
5 ;; This file is part of GCC. 5 ;; This file is part of GCC.
6 ;; 6 ;;
7 ;; GCC is free software; you can redistribute it and/or modify it 7 ;; GCC is free software; you can redistribute it and/or modify it
39 39
40 40
41 (define_register_constraint "t" "R15_TA_REG" 41 (define_register_constraint "t" "R15_TA_REG"
42 "Temporary Assist register $ta (i.e. $r15)") 42 "Temporary Assist register $ta (i.e. $r15)")
43 43
44 (define_register_constraint "e" "R8_REG"
45 "Function Entry register $r8)")
46
44 (define_register_constraint "k" "STACK_REG" 47 (define_register_constraint "k" "STACK_REG"
45 "Stack register $sp") 48 "Stack register $sp")
46 49
50 (define_register_constraint "v" "R5_REG"
51 "Register $r5")
52
53 (define_register_constraint "x" "FRAME_POINTER_REG"
54 "Frame pointer register $fp")
55
56 (define_register_constraint "f"
57 "(TARGET_FPU_SINGLE || TARGET_FPU_DOUBLE) ? FP_REGS : NO_REGS"
58 "The Floating point registers $fs0 ~ $fs31")
59
60 (define_constraint "Iv00"
61 "Constant value 0"
62 (and (match_code "const_int")
63 (match_test "ival == 0")))
64
65 (define_constraint "Iv01"
66 "Constant value 1"
67 (and (match_code "const_int")
68 (match_test "ival == 1")))
69
70 (define_constraint "Iv02"
71 "Constant value 2"
72 (and (match_code "const_int")
73 (match_test "ival == 2")))
74
75 (define_constraint "Iv04"
76 "Constant value 4"
77 (and (match_code "const_int")
78 (match_test "ival == 4")))
79
80 (define_constraint "Iv08"
81 "Constant value 8"
82 (and (match_code "const_int")
83 (match_test "ival == 8")))
84
85 (define_constraint "Iu01"
86 "Unsigned immediate 1-bit value"
87 (and (match_code "const_int")
88 (match_test "ival == 1 || ival == 0")))
89
90 (define_constraint "Iu02"
91 "Unsigned immediate 2-bit value"
92 (and (match_code "const_int")
93 (match_test "ival < (1 << 2) && ival >= 0")))
47 94
48 (define_constraint "Iu03" 95 (define_constraint "Iu03"
49 "Unsigned immediate 3-bit value" 96 "Unsigned immediate 3-bit value"
50 (and (match_code "const_int") 97 (and (match_code "const_int")
51 (match_test "ival < (1 << 3) && ival >= 0"))) 98 (match_test "ival < (1 << 3) && ival >= 0")))
63 (define_constraint "Is05" 110 (define_constraint "Is05"
64 "Signed immediate 5-bit value" 111 "Signed immediate 5-bit value"
65 (and (match_code "const_int") 112 (and (match_code "const_int")
66 (match_test "ival < (1 << 4) && ival >= -(1 << 4)"))) 113 (match_test "ival < (1 << 4) && ival >= -(1 << 4)")))
67 114
115 (define_constraint "Cs05"
116 "Signed immediate 5-bit value"
117 (and (match_code "const_double")
118 (match_test "nds32_const_double_range_ok_p (op, SFmode, -(1 << 4), (1 << 4))")))
119
68 (define_constraint "Iu05" 120 (define_constraint "Iu05"
69 "Unsigned immediate 5-bit value" 121 "Unsigned immediate 5-bit value"
70 (and (match_code "const_int") 122 (and (match_code "const_int")
71 (match_test "ival < (1 << 5) && ival >= 0"))) 123 (match_test "ival < (1 << 5) && ival >= 0")))
72 124
73 (define_constraint "In05" 125 (define_constraint "In05"
74 "Negative immediate 5-bit value in the range of -31 to 0" 126 "Negative immediate 5-bit value in the range of -31 to 0"
75 (and (match_code "const_int") 127 (and (match_code "const_int")
76 (match_test "IN_RANGE (ival, -31, 0)"))) 128 (match_test "IN_RANGE (ival, -31, 0)")))
129
130 (define_constraint "Iu06"
131 "Unsigned immediate 6-bit value"
132 (and (match_code "const_int")
133 (match_test "ival < (1 << 6) && ival >= 0")))
77 134
78 ;; Ip05 is special and dedicated for v3 movpi45 instruction. 135 ;; Ip05 is special and dedicated for v3 movpi45 instruction.
79 ;; movpi45 has imm5u field but the range is 16 ~ 47. 136 ;; movpi45 has imm5u field but the range is 16 ~ 47.
80 (define_constraint "Ip05" 137 (define_constraint "Ip05"
81 "Unsigned immediate 5-bit value for movpi45 instruction with range 16-47" 138 "Unsigned immediate 5-bit value for movpi45 instruction with range 16-47"
82 (and (match_code "const_int") 139 (and (match_code "const_int")
83 (match_test "ival < ((1 << 5) + 16) 140 (match_test "ival < ((1 << 5) + 16)
84 && ival >= (0 + 16) 141 && ival >= (0 + 16)
85 && (TARGET_ISA_V3 || TARGET_ISA_V3M)"))) 142 && (TARGET_ISA_V3 || TARGET_ISA_V3M)")))
86 143
87 (define_constraint "Iu06" 144 (define_constraint "IU06"
88 "Unsigned immediate 6-bit value constraint for addri36.sp instruction" 145 "Unsigned immediate 6-bit value constraint for addri36.sp instruction"
89 (and (match_code "const_int") 146 (and (match_code "const_int")
90 (match_test "ival < (1 << 6) 147 (match_test "ival < (1 << 8)
91 && ival >= 0 148 && ival >= 0
92 && (ival % 4 == 0) 149 && (ival % 4 == 0)
93 && (TARGET_ISA_V3 || TARGET_ISA_V3M)"))) 150 && (TARGET_ISA_V3 || TARGET_ISA_V3M)")))
94 151
95 (define_constraint "Iu08" 152 (define_constraint "Iu08"
101 "Unsigned immediate 9-bit value" 158 "Unsigned immediate 9-bit value"
102 (and (match_code "const_int") 159 (and (match_code "const_int")
103 (match_test "ival < (1 << 9) && ival >= 0"))) 160 (match_test "ival < (1 << 9) && ival >= 0")))
104 161
105 162
163 (define_constraint "Is08"
164 "Signed immediate 8-bit value"
165 (and (match_code "const_int")
166 (match_test "ival < (1 << 7) && ival >= -(1 << 7)")))
167
106 (define_constraint "Is10" 168 (define_constraint "Is10"
107 "Signed immediate 10-bit value" 169 "Signed immediate 10-bit value"
108 (and (match_code "const_int") 170 (and (match_code "const_int")
109 (match_test "ival < (1 << 9) && ival >= -(1 << 9)"))) 171 (match_test "ival < (1 << 9) && ival >= -(1 << 9)")))
110 172
111 (define_constraint "Is11" 173 (define_constraint "Is11"
112 "Signed immediate 11-bit value" 174 "Signed immediate 11-bit value"
113 (and (match_code "const_int") 175 (and (match_code "const_int")
114 (match_test "ival < (1 << 10) && ival >= -(1 << 10)"))) 176 (match_test "ival < (1 << 10) && ival >= -(1 << 10)")))
115 177
178 (define_constraint "Is14"
179 "Signed immediate 14-bit value"
180 (and (match_code "const_int")
181 (match_test "ival < (1 << 13) && ival >= -(1 << 13)")))
116 182
117 (define_constraint "Is15" 183 (define_constraint "Is15"
118 "Signed immediate 15-bit value" 184 "Signed immediate 15-bit value"
119 (and (match_code "const_int") 185 (and (match_code "const_int")
120 (match_test "ival < (1 << 14) && ival >= -(1 << 14)"))) 186 (match_test "ival < (1 << 14) && ival >= -(1 << 14)")))
192 (define_constraint "Is20" 258 (define_constraint "Is20"
193 "Signed immediate 20-bit value" 259 "Signed immediate 20-bit value"
194 (and (match_code "const_int") 260 (and (match_code "const_int")
195 (match_test "ival < (1 << 19) && ival >= -(1 << 19)"))) 261 (match_test "ival < (1 << 19) && ival >= -(1 << 19)")))
196 262
263 (define_constraint "Cs20"
264 "Signed immediate 20-bit value"
265 (and (match_code "const_double")
266 (match_test "nds32_const_double_range_ok_p (op, SFmode, -(1 << 19), (1 << 19))")))
197 267
198 (define_constraint "Ihig" 268 (define_constraint "Ihig"
199 "The immediate value that can be simply set high 20-bit" 269 "The immediate value that can be simply set high 20-bit"
200 (and (match_code "const_int") 270 (and (match_code "const_int")
201 (match_test "(ival != 0) && ((ival & 0xfff) == 0)"))) 271 (match_test "(ival != 0) && ((ival & 0xfff) == 0)")))
202 272
273 (define_constraint "Chig"
274 "The immediate value that can be simply set high 20-bit"
275 (and (match_code "high")
276 (match_test "GET_CODE (XEXP (op, 0)) == CONST_DOUBLE")))
277
203 (define_constraint "Izeb" 278 (define_constraint "Izeb"
204 "The immediate value 0xff" 279 "The immediate value 0xff"
205 (and (match_code "const_int") 280 (and (match_code "const_int")
206 (match_test "(ival == 0xff)"))) 281 (match_test "(ival == 0xff)")))
207 282
211 (match_test "(ival == 0xffff)"))) 286 (match_test "(ival == 0xffff)")))
212 287
213 (define_constraint "Ixls" 288 (define_constraint "Ixls"
214 "The immediate value 0x01" 289 "The immediate value 0x01"
215 (and (match_code "const_int") 290 (and (match_code "const_int")
216 (match_test "TARGET_PERF_EXT && (ival == 0x1)"))) 291 (match_test "TARGET_EXT_PERF && (ival == 0x1)")))
217 292
218 (define_constraint "Ix11" 293 (define_constraint "Ix11"
219 "The immediate value 0x7ff" 294 "The immediate value 0x7ff"
220 (and (match_code "const_int") 295 (and (match_code "const_int")
221 (match_test "TARGET_PERF_EXT && (ival == 0x7ff)"))) 296 (match_test "TARGET_EXT_PERF && (ival == 0x7ff)")))
222 297
223 (define_constraint "Ibms" 298 (define_constraint "Ibms"
224 "The immediate value with power of 2" 299 "The immediate value with power of 2"
225 (and (match_code "const_int") 300 (and (match_code "const_int")
226 (match_test "(TARGET_ISA_V3 || TARGET_ISA_V3M) 301 (match_test "(TARGET_ISA_V3 || TARGET_ISA_V3M)
230 "The immediate value with power of 2 minus 1" 305 "The immediate value with power of 2 minus 1"
231 (and (match_code "const_int") 306 (and (match_code "const_int")
232 (match_test "(TARGET_ISA_V3 || TARGET_ISA_V3M) 307 (match_test "(TARGET_ISA_V3 || TARGET_ISA_V3M)
233 && (IN_RANGE (exact_log2 (ival + 1), 1, 8))"))) 308 && (IN_RANGE (exact_log2 (ival + 1), 1, 8))")))
234 309
310 (define_constraint "CVp5"
311 "Unsigned immediate 5-bit value for movpi45 instruction with range 16-47"
312 (and (match_code "const_vector")
313 (match_test "nds32_valid_CVp5_p (op)")))
314
315 (define_constraint "CVs5"
316 "Signed immediate 5-bit value"
317 (and (match_code "const_vector")
318 (match_test "nds32_valid_CVs5_p (op)")))
319
320 (define_constraint "CVs2"
321 "Signed immediate 20-bit value"
322 (and (match_code "const_vector")
323 (match_test "nds32_valid_CVs2_p (op)")))
324
325 (define_constraint "CVhi"
326 "The immediate value that can be simply set high 20-bit"
327 (and (match_code "const_vector")
328 (match_test "nds32_valid_CVhi_p (op)")))
235 329
236 (define_memory_constraint "U33" 330 (define_memory_constraint "U33"
237 "Memory constraint for 333 format" 331 "Memory constraint for 333 format"
238 (and (match_code "mem") 332 (and (match_code "mem")
239 (match_test "nds32_mem_format (op) == ADDRESS_LO_REG_IMM3U"))) 333 (match_test "nds32_mem_format (op) == ADDRESS_POST_INC_LO_REG_IMM3U
334 || nds32_mem_format (op) == ADDRESS_POST_MODIFY_LO_REG_IMM3U
335 || nds32_mem_format (op) == ADDRESS_LO_REG_IMM3U")))
240 336
241 (define_memory_constraint "U45" 337 (define_memory_constraint "U45"
242 "Memory constraint for 45 format" 338 "Memory constraint for 45 format"
243 (and (match_code "mem") 339 (and (match_code "mem")
244 (match_test "(nds32_mem_format (op) == ADDRESS_REG) 340 (match_test "(nds32_mem_format (op) == ADDRESS_REG)
245 && (GET_MODE (op) == SImode)"))) 341 && ((GET_MODE (op) == SImode)
342 || (GET_MODE (op) == SFmode))")))
343
344 (define_memory_constraint "Ufe"
345 "Memory constraint for fe format"
346 (and (match_code "mem")
347 (match_test "nds32_mem_format (op) == ADDRESS_R8_IMM7U
348 && (GET_MODE (op) == SImode
349 || GET_MODE (op) == SFmode)")))
246 350
247 (define_memory_constraint "U37" 351 (define_memory_constraint "U37"
248 "Memory constraint for 37 format" 352 "Memory constraint for 37 format"
249 (and (match_code "mem") 353 (and (match_code "mem")
250 (match_test "(nds32_mem_format (op) == ADDRESS_SP_IMM7U 354 (match_test "(nds32_mem_format (op) == ADDRESS_SP_IMM7U
251 || nds32_mem_format (op) == ADDRESS_FP_IMM7U) 355 || nds32_mem_format (op) == ADDRESS_FP_IMM7U)
252 && (GET_MODE (op) == SImode)"))) 356 && (GET_MODE (op) == SImode
357 || GET_MODE (op) == SFmode)")))
358
359 (define_memory_constraint "Umw"
360 "Memory constraint for lwm/smw"
361 (and (match_code "mem")
362 (match_test "nds32_valid_smw_lwm_base_p (op)")))
363
364 (define_memory_constraint "Da"
365 "Memory constraint for non-offset loads/stores"
366 (and (match_code "mem")
367 (match_test "REG_P (XEXP (op, 0))
368 || (GET_CODE (XEXP (op, 0)) == POST_INC)")))
369
370 (define_memory_constraint "Q"
371 "Memory constraint for no symbol_ref and const"
372 (and (match_code "mem")
373 (match_test "(TARGET_FPU_SINGLE || TARGET_FPU_DOUBLE)
374 && nds32_float_mem_operand_p (op)")))
375
376 (define_constraint "S"
377 "@internal
378 A constant call address."
379 (match_operand 0 "nds32_symbolic_operand"))
253 380
254 ;; ------------------------------------------------------------------------ 381 ;; ------------------------------------------------------------------------