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1 ;; Constraint definitions of Andes NDS32 cpu for GNU compiler
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2 ;; Copyright (C) 2012-2018 Free Software Foundation, Inc.
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3 ;; Contributed by Andes Technology Corporation.
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4 ;;
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5 ;; This file is part of GCC.
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6 ;;
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7 ;; GCC is free software; you can redistribute it and/or modify it
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8 ;; under the terms of the GNU General Public License as published
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9 ;; by the Free Software Foundation; either version 3, or (at your
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10 ;; option) any later version.
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11 ;;
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12 ;; GCC is distributed in the hope that it will be useful, but WITHOUT
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13 ;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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14 ;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
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15 ;; License for more details.
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16 ;;
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17 ;; You should have received a copy of the GNU General Public License
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18 ;; along with GCC; see the file COPYING3. If not see
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19 ;; <http://www.gnu.org/licenses/>.
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20
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21 ;; Check 16.8.7 Defining Machine-Specific Constraints for detail.
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22
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23 ;; NO contrains can be prefixed with: E F V X g i m n o p r s
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24 ;; Machine-dependent integer: I J K L M N O P
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25 ;; Machine-dependent floating: G H
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26
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27
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28 (define_register_constraint "w" "(TARGET_ISA_V3 || TARGET_ISA_V3M) ? LOW_REGS : NO_REGS"
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29 "LOW register class $r0 ~ $r7 constraint for V3/V3M ISA")
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30
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31 (define_register_constraint "l" "LOW_REGS"
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32 "LOW register class $r0 ~ $r7")
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33
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34 (define_register_constraint "d" "MIDDLE_REGS"
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35 "MIDDLE register class $r0 ~ $r11, $r16 ~ $r19")
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36
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37 (define_register_constraint "h" "HIGH_REGS"
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38 "HIGH register class $r12 ~ $r14, $r20 ~ $r31")
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39
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40
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41 (define_register_constraint "t" "R15_TA_REG"
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42 "Temporary Assist register $ta (i.e. $r15)")
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43
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44 (define_register_constraint "e" "R8_REG"
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45 "Function Entry register $r8)")
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46
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47 (define_register_constraint "k" "STACK_REG"
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48 "Stack register $sp")
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49
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131
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50 (define_register_constraint "v" "R5_REG"
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51 "Register $r5")
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52
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53 (define_register_constraint "x" "FRAME_POINTER_REG"
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54 "Frame pointer register $fp")
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55
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56 (define_register_constraint "f"
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57 "(TARGET_FPU_SINGLE || TARGET_FPU_DOUBLE) ? FP_REGS : NO_REGS"
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58 "The Floating point registers $fs0 ~ $fs31")
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59
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60 (define_constraint "Iv00"
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61 "Constant value 0"
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62 (and (match_code "const_int")
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63 (match_test "ival == 0")))
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64
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65 (define_constraint "Iv01"
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66 "Constant value 1"
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67 (and (match_code "const_int")
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68 (match_test "ival == 1")))
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69
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70 (define_constraint "Iv02"
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71 "Constant value 2"
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72 (and (match_code "const_int")
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73 (match_test "ival == 2")))
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74
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75 (define_constraint "Iv04"
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76 "Constant value 4"
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77 (and (match_code "const_int")
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78 (match_test "ival == 4")))
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79
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80 (define_constraint "Iv08"
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81 "Constant value 8"
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82 (and (match_code "const_int")
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83 (match_test "ival == 8")))
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84
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85 (define_constraint "Iu01"
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86 "Unsigned immediate 1-bit value"
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87 (and (match_code "const_int")
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88 (match_test "ival == 1 || ival == 0")))
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89
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90 (define_constraint "Iu02"
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91 "Unsigned immediate 2-bit value"
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92 (and (match_code "const_int")
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93 (match_test "ival < (1 << 2) && ival >= 0")))
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94
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95 (define_constraint "Iu03"
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96 "Unsigned immediate 3-bit value"
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97 (and (match_code "const_int")
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98 (match_test "ival < (1 << 3) && ival >= 0")))
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99
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100 (define_constraint "In03"
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101 "Negative immediate 3-bit value in the range of -7 to 0"
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102 (and (match_code "const_int")
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103 (match_test "IN_RANGE (ival, -7, 0)")))
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104
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105 (define_constraint "Iu04"
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106 "Unsigned immediate 4-bit value"
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107 (and (match_code "const_int")
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108 (match_test "ival < (1 << 4) && ival >= 0")))
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109
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110 (define_constraint "Is05"
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111 "Signed immediate 5-bit value"
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112 (and (match_code "const_int")
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113 (match_test "ival < (1 << 4) && ival >= -(1 << 4)")))
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114
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131
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115 (define_constraint "Cs05"
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116 "Signed immediate 5-bit value"
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117 (and (match_code "const_double")
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118 (match_test "nds32_const_double_range_ok_p (op, SFmode, -(1 << 4), (1 << 4))")))
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119
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120 (define_constraint "Iu05"
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121 "Unsigned immediate 5-bit value"
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122 (and (match_code "const_int")
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123 (match_test "ival < (1 << 5) && ival >= 0")))
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124
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125 (define_constraint "In05"
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126 "Negative immediate 5-bit value in the range of -31 to 0"
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127 (and (match_code "const_int")
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128 (match_test "IN_RANGE (ival, -31, 0)")))
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129
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131
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130 (define_constraint "Iu06"
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131 "Unsigned immediate 6-bit value"
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132 (and (match_code "const_int")
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133 (match_test "ival < (1 << 6) && ival >= 0")))
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134
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135 ;; Ip05 is special and dedicated for v3 movpi45 instruction.
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136 ;; movpi45 has imm5u field but the range is 16 ~ 47.
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137 (define_constraint "Ip05"
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138 "Unsigned immediate 5-bit value for movpi45 instruction with range 16-47"
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139 (and (match_code "const_int")
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140 (match_test "ival < ((1 << 5) + 16)
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141 && ival >= (0 + 16)
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142 && (TARGET_ISA_V3 || TARGET_ISA_V3M)")))
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143
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144 (define_constraint "IU06"
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145 "Unsigned immediate 6-bit value constraint for addri36.sp instruction"
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146 (and (match_code "const_int")
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147 (match_test "ival < (1 << 8)
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148 && ival >= 0
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149 && (ival % 4 == 0)
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150 && (TARGET_ISA_V3 || TARGET_ISA_V3M)")))
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151
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152 (define_constraint "Iu08"
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153 "Unsigned immediate 8-bit value"
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154 (and (match_code "const_int")
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155 (match_test "ival < (1 << 8) && ival >= 0")))
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156
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157 (define_constraint "Iu09"
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158 "Unsigned immediate 9-bit value"
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159 (and (match_code "const_int")
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160 (match_test "ival < (1 << 9) && ival >= 0")))
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161
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162
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163 (define_constraint "Is08"
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164 "Signed immediate 8-bit value"
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165 (and (match_code "const_int")
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166 (match_test "ival < (1 << 7) && ival >= -(1 << 7)")))
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167
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168 (define_constraint "Is10"
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169 "Signed immediate 10-bit value"
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170 (and (match_code "const_int")
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171 (match_test "ival < (1 << 9) && ival >= -(1 << 9)")))
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172
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173 (define_constraint "Is11"
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174 "Signed immediate 11-bit value"
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175 (and (match_code "const_int")
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176 (match_test "ival < (1 << 10) && ival >= -(1 << 10)")))
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177
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178 (define_constraint "Is14"
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179 "Signed immediate 14-bit value"
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180 (and (match_code "const_int")
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181 (match_test "ival < (1 << 13) && ival >= -(1 << 13)")))
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111
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182
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183 (define_constraint "Is15"
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184 "Signed immediate 15-bit value"
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185 (and (match_code "const_int")
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186 (match_test "ival < (1 << 14) && ival >= -(1 << 14)")))
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187
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188 (define_constraint "Iu15"
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189 "Unsigned immediate 15-bit value"
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190 (and (match_code "const_int")
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191 (match_test "ival < (1 << 15) && ival >= 0")))
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192
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193
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194 ;; Ic15 is special and dedicated for performance extension
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195 ;; 'bclr' (single-bit-clear) instruction.
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196 ;; It is used in andsi3 pattern and recognized for the immediate
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197 ;; which is NOT in the range of imm15u but OK for 'bclr' instruction.
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198 ;; (If the immediate value IS in the range of imm15u,
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199 ;; we can directly use 'andi' instruction.)
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200 (define_constraint "Ic15"
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201 "A constant which is not in the range of imm15u but ok for bclr instruction"
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202 (and (match_code "const_int")
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203 (match_test "(ival & 0xffff8000) && nds32_can_use_bclr_p (ival)")))
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204
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205 ;; Ie15 is special and dedicated for performance extension
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206 ;; 'bset' (single-bit-set) instruction.
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207 ;; It is used in iorsi3 pattern and recognized for the immediate
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208 ;; which is NOT in the range of imm15u but OK for 'bset' instruction.
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209 ;; (If the immediate value IS in the range of imm15u,
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210 ;; we can directly use 'ori' instruction.)
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211 (define_constraint "Ie15"
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212 "A constant which is not in the range of imm15u but ok for bset instruction"
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213 (and (match_code "const_int")
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214 (match_test "(ival & 0xffff8000) && nds32_can_use_bset_p (ival)")))
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215
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216 ;; It15 is special and dedicated for performance extension
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217 ;; 'btgl' (single-bit-toggle) instruction.
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218 ;; It is used in xorsi3 pattern and recognized for the immediate
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219 ;; which is NOT in the range of imm15u but OK for 'btgl' instruction.
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220 ;; (If the immediate value IS in the range of imm15u,
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221 ;; we can directly use 'xori' instruction.)
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222 (define_constraint "It15"
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223 "A constant which is not in the range of imm15u but ok for btgl instruction"
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224 (and (match_code "const_int")
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225 (match_test "(ival & 0xffff8000) && nds32_can_use_btgl_p (ival)")))
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226
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227
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228 ;; Ii15 is special and dedicated for v3 isa
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229 ;; 'bitci' (bit-clear-immediate) instruction.
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230 ;; It is used in andsi3 pattern and recognized for the immediate whose
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231 ;; (~ival) value is in the range of imm15u and OK for 'bitci' instruction.
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232 ;; For example, 'andi $r0,$r0,0xfffffffc' can be presented
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233 ; with 'bitci $r0,$r0,3'.
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234 (define_constraint "Ii15"
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235 "A constant whose compliment value is in the range of imm15u
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236 and ok for bitci instruction"
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237 (and (match_code "const_int")
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238 (match_test "nds32_can_use_bitci_p (ival)")))
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239
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240
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241 (define_constraint "Is16"
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242 "Signed immediate 16-bit value"
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243 (and (match_code "const_int")
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244 (match_test "ival < (1 << 15) && ival >= -(1 << 15)")))
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245
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246 (define_constraint "Is17"
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247 "Signed immediate 17-bit value"
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248 (and (match_code "const_int")
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249 (match_test "ival < (1 << 16) && ival >= -(1 << 16)")))
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250
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251
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252 (define_constraint "Is19"
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253 "Signed immediate 19-bit value"
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254 (and (match_code "const_int")
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255 (match_test "ival < (1 << 18) && ival >= -(1 << 18)")))
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256
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257
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258 (define_constraint "Is20"
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259 "Signed immediate 20-bit value"
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260 (and (match_code "const_int")
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261 (match_test "ival < (1 << 19) && ival >= -(1 << 19)")))
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262
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131
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263 (define_constraint "Cs20"
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264 "Signed immediate 20-bit value"
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265 (and (match_code "const_double")
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266 (match_test "nds32_const_double_range_ok_p (op, SFmode, -(1 << 19), (1 << 19))")))
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111
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267
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268 (define_constraint "Ihig"
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269 "The immediate value that can be simply set high 20-bit"
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270 (and (match_code "const_int")
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271 (match_test "(ival != 0) && ((ival & 0xfff) == 0)")))
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272
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131
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273 (define_constraint "Chig"
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274 "The immediate value that can be simply set high 20-bit"
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275 (and (match_code "high")
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276 (match_test "GET_CODE (XEXP (op, 0)) == CONST_DOUBLE")))
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277
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111
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278 (define_constraint "Izeb"
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279 "The immediate value 0xff"
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280 (and (match_code "const_int")
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281 (match_test "(ival == 0xff)")))
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282
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283 (define_constraint "Izeh"
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284 "The immediate value 0xffff"
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285 (and (match_code "const_int")
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286 (match_test "(ival == 0xffff)")))
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287
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288 (define_constraint "Ixls"
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289 "The immediate value 0x01"
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290 (and (match_code "const_int")
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131
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291 (match_test "TARGET_EXT_PERF && (ival == 0x1)")))
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111
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292
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293 (define_constraint "Ix11"
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294 "The immediate value 0x7ff"
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295 (and (match_code "const_int")
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131
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296 (match_test "TARGET_EXT_PERF && (ival == 0x7ff)")))
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111
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297
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298 (define_constraint "Ibms"
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299 "The immediate value with power of 2"
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300 (and (match_code "const_int")
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301 (match_test "(TARGET_ISA_V3 || TARGET_ISA_V3M)
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302 && (IN_RANGE (exact_log2 (ival), 0, 7))")))
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303
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304 (define_constraint "Ifex"
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305 "The immediate value with power of 2 minus 1"
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306 (and (match_code "const_int")
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307 (match_test "(TARGET_ISA_V3 || TARGET_ISA_V3M)
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308 && (IN_RANGE (exact_log2 (ival + 1), 1, 8))")))
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309
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131
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310 (define_constraint "CVp5"
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311 "Unsigned immediate 5-bit value for movpi45 instruction with range 16-47"
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312 (and (match_code "const_vector")
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313 (match_test "nds32_valid_CVp5_p (op)")))
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314
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315 (define_constraint "CVs5"
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316 "Signed immediate 5-bit value"
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317 (and (match_code "const_vector")
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318 (match_test "nds32_valid_CVs5_p (op)")))
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319
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320 (define_constraint "CVs2"
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321 "Signed immediate 20-bit value"
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322 (and (match_code "const_vector")
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323 (match_test "nds32_valid_CVs2_p (op)")))
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324
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325 (define_constraint "CVhi"
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326 "The immediate value that can be simply set high 20-bit"
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327 (and (match_code "const_vector")
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328 (match_test "nds32_valid_CVhi_p (op)")))
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111
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329
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330 (define_memory_constraint "U33"
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331 "Memory constraint for 333 format"
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332 (and (match_code "mem")
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131
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333 (match_test "nds32_mem_format (op) == ADDRESS_POST_INC_LO_REG_IMM3U
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334 || nds32_mem_format (op) == ADDRESS_POST_MODIFY_LO_REG_IMM3U
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335 || nds32_mem_format (op) == ADDRESS_LO_REG_IMM3U")))
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111
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336
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337 (define_memory_constraint "U45"
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338 "Memory constraint for 45 format"
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339 (and (match_code "mem")
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340 (match_test "(nds32_mem_format (op) == ADDRESS_REG)
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131
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341 && ((GET_MODE (op) == SImode)
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342 || (GET_MODE (op) == SFmode))")))
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343
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344 (define_memory_constraint "Ufe"
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345 "Memory constraint for fe format"
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346 (and (match_code "mem")
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347 (match_test "nds32_mem_format (op) == ADDRESS_R8_IMM7U
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348 && (GET_MODE (op) == SImode
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349 || GET_MODE (op) == SFmode)")))
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111
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350
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351 (define_memory_constraint "U37"
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352 "Memory constraint for 37 format"
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353 (and (match_code "mem")
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354 (match_test "(nds32_mem_format (op) == ADDRESS_SP_IMM7U
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355 || nds32_mem_format (op) == ADDRESS_FP_IMM7U)
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131
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356 && (GET_MODE (op) == SImode
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357 || GET_MODE (op) == SFmode)")))
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358
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359 (define_memory_constraint "Umw"
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360 "Memory constraint for lwm/smw"
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361 (and (match_code "mem")
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362 (match_test "nds32_valid_smw_lwm_base_p (op)")))
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363
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364 (define_memory_constraint "Da"
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365 "Memory constraint for non-offset loads/stores"
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366 (and (match_code "mem")
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367 (match_test "REG_P (XEXP (op, 0))
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368 || (GET_CODE (XEXP (op, 0)) == POST_INC)")))
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369
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370 (define_memory_constraint "Q"
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371 "Memory constraint for no symbol_ref and const"
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372 (and (match_code "mem")
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373 (match_test "(TARGET_FPU_SINGLE || TARGET_FPU_DOUBLE)
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374 && nds32_float_mem_operand_p (op)")))
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375
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376 (define_constraint "S"
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377 "@internal
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378 A constant call address."
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379 (match_operand 0 "nds32_symbolic_operand"))
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111
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380
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381 ;; ------------------------------------------------------------------------
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