Mercurial > hg > CbC > CbC_gcc

comparison gcc/config/ia64/ia64.opt @ 0:a06113de4d67

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first commit
author kent <kent@cr.ie.u-ryukyu.ac.jp>
date Fri, 17 Jul 2009 14:47:48 +0900
parents
children 77e2b8dfacca
comparison
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-1:000000000000 0:a06113de4d67
1 mbig-endian
2 Target Report RejectNegative Mask(BIG_ENDIAN)
3 Generate big endian code
4
5 mlittle-endian
6 Target Report RejectNegative InverseMask(BIG_ENDIAN)
7 Generate little endian code
8
9 mgnu-as
10 Target Report Mask(GNU_AS)
11 Generate code for GNU as
12
13 mgnu-ld
14 Target Report Mask(GNU_LD)
15 Generate code for GNU ld
16
17 mvolatile-asm-stop
18 Target Report Mask(VOL_ASM_STOP)
19 Emit stop bits before and after volatile extended asms
20
21 mregister-names
22 Target Mask(REG_NAMES)
23 Use in/loc/out register names
24
25 mno-sdata
26 Target Report RejectNegative Mask(NO_SDATA)
27
28 msdata
29 Target Report RejectNegative InverseMask(NO_SDATA)
30 Enable use of sdata/scommon/sbss
31
32 mno-pic
33 Target Report RejectNegative Mask(NO_PIC)
34 Generate code without GP reg
35
36 mconstant-gp
37 Target Report RejectNegative Mask(CONST_GP)
38 gp is constant (but save/restore gp on indirect calls)
39
40 mauto-pic
41 Target Report RejectNegative Mask(AUTO_PIC)
42 Generate self-relocatable code
43
44 minline-float-divide-min-latency
45 Target Report RejectNegative Var(TARGET_INLINE_FLOAT_DIV, 1)
46 Generate inline floating point division, optimize for latency
47
48 minline-float-divide-max-throughput
49 Target Report RejectNegative Var(TARGET_INLINE_FLOAT_DIV, 2) Init(2)
50 Generate inline floating point division, optimize for throughput
51
52 mno-inline-float-divide
53 Target Report RejectNegative Var(TARGET_INLINE_FLOAT_DIV, 0)
54
55 minline-int-divide-min-latency
56 Target Report RejectNegative Var(TARGET_INLINE_INT_DIV, 1)
57 Generate inline integer division, optimize for latency
58
59 minline-int-divide-max-throughput
60 Target Report RejectNegative Var(TARGET_INLINE_INT_DIV, 2)
61 Generate inline integer division, optimize for throughput
62
63 mno-inline-int-divide
64 Target Report RejectNegative Var(TARGET_INLINE_INT_DIV, 0)
65 Do not inline integer division
66
67 minline-sqrt-min-latency
68 Target Report RejectNegative Var(TARGET_INLINE_SQRT, 1)
69 Generate inline square root, optimize for latency
70
71 minline-sqrt-max-throughput
72 Target Report RejectNegative Var(TARGET_INLINE_SQRT, 2)
73 Generate inline square root, optimize for throughput
74
75 mno-inline-sqrt
76 Target Report RejectNegative Var(TARGET_INLINE_SQRT, 0)
77 Do not inline square root
78
79 mdwarf2-asm
80 Target Report Mask(DWARF2_ASM)
81 Enable Dwarf 2 line debug info via GNU as
82
83 mearly-stop-bits
84 Target Report Mask(EARLY_STOP_BITS)
85 Enable earlier placing stop bits for better scheduling
86
87 mfixed-range=
88 Target RejectNegative Joined
89 Specify range of registers to make fixed
90
91 mtls-size=
92 Target RejectNegative Joined UInteger Var(ia64_tls_size) Init(22)
93 Specify bit size of immediate TLS offsets
94
95 mtune=
96 Target RejectNegative Joined
97 Schedule code for given CPU
98
99 msched-br-data-spec
100 Target Report Var(mflag_sched_br_data_spec) Init(0)
101 Use data speculation before reload
102
103 msched-ar-data-spec
104 Target Report Var(mflag_sched_ar_data_spec) Init(1)
105 Use data speculation after reload
106
107 msched-control-spec
108 Target Report Var(mflag_sched_control_spec) Init(2)
109 Use control speculation
110
111 msched-br-in-data-spec
112 Target Report Var(mflag_sched_br_in_data_spec) Init(1)
113 Use in block data speculation before reload
114
115 msched-ar-in-data-spec
116 Target Report Var(mflag_sched_ar_in_data_spec) Init(1)
117 Use in block data speculation after reload
118
119 msched-in-control-spec
120 Target Report Var(mflag_sched_in_control_spec) Init(1)
121 Use in block control speculation
122
123 msched-spec-ldc
124 Target Report Var(mflag_sched_spec_ldc) Init(1)
125 Use simple data speculation check
126
127 msched-spec-control-ldc
128 Target Report Var(mflag_sched_spec_control_ldc) Init(0)
129 Use simple data speculation check for control speculation
130
131 msched-prefer-non-data-spec-insns
132 Target Report Var(mflag_sched_prefer_non_data_spec_insns) Init(0)
133 If set, data speculative instructions will be chosen for schedule only if there are no other choices at the moment
134
135 msched-prefer-non-control-spec-insns
136 Target Report Var(mflag_sched_prefer_non_control_spec_insns) Init(0)
137 If set, control speculative instructions will be chosen for schedule only if there are no other choices at the moment
138
139 msched-count-spec-in-critical-path
140 Target Report Var(mflag_sched_count_spec_in_critical_path) Init(0)
141 Count speculative dependencies while calculating priority of instructions
142
143 msched-stop-bits-after-every-cycle
144 Target Report Var(mflag_sched_stop_bits_after_every_cycle) Init(1)
145 Place a stop bit after every cycle when scheduling
146
147 msched-fp-mem-deps-zero-cost
148 Target Report Var(mflag_sched_fp_mem_deps_zero_cost) Init(0)
149 Assume that floating-point stores and loads are not likely to cause conflict when placed into one instruction group
150
151 msched-max-memory-insns=
152 Target RejectNegative Joined UInteger Var(ia64_max_memory_insns) Init(1)
153 Soft limit on number of memory insns per instruction group, giving lower priority to subsequent memory insns attempting to schedule in the same insn group. Frequently useful to prevent cache bank conflicts. Default value is 1
154
155 msched-max-memory-insns-hard-limit
156 Target Report Var(mflag_sched_mem_insns_hard_limit) Init(0)
157 Disallow more than `msched-max-memory-insns' in instruction group. Otherwise, limit is `soft' (prefer non-memory operations when limit is reached)
158
159 msel-sched-dont-check-control-spec
160 Target Report Var(mflag_sel_sched_dont_check_control_spec) Init(0)
161 Don't generate checks for control speculation in selective scheduling
162
163 ; This comment is to ensure we retain the blank line above.