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1 mbig-endian
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2 Target Report RejectNegative Mask(BIG_ENDIAN)
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3 Generate big endian code
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4
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5 mlittle-endian
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6 Target Report RejectNegative InverseMask(BIG_ENDIAN)
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7 Generate little endian code
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8
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9 mgnu-as
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10 Target Report Mask(GNU_AS)
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11 Generate code for GNU as
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12
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13 mgnu-ld
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14 Target Report Mask(GNU_LD)
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15 Generate code for GNU ld
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16
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17 mvolatile-asm-stop
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18 Target Report Mask(VOL_ASM_STOP)
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19 Emit stop bits before and after volatile extended asms
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20
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21 mregister-names
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22 Target Mask(REG_NAMES)
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23 Use in/loc/out register names
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24
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25 mno-sdata
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26 Target Report RejectNegative Mask(NO_SDATA)
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27
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28 msdata
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29 Target Report RejectNegative InverseMask(NO_SDATA)
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30 Enable use of sdata/scommon/sbss
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31
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32 mno-pic
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33 Target Report RejectNegative Mask(NO_PIC)
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34 Generate code without GP reg
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35
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36 mconstant-gp
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37 Target Report RejectNegative Mask(CONST_GP)
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38 gp is constant (but save/restore gp on indirect calls)
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39
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40 mauto-pic
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41 Target Report RejectNegative Mask(AUTO_PIC)
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42 Generate self-relocatable code
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43
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44 minline-float-divide-min-latency
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45 Target Report RejectNegative Var(TARGET_INLINE_FLOAT_DIV, 1)
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46 Generate inline floating point division, optimize for latency
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47
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48 minline-float-divide-max-throughput
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49 Target Report RejectNegative Var(TARGET_INLINE_FLOAT_DIV, 2) Init(2)
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50 Generate inline floating point division, optimize for throughput
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51
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52 mno-inline-float-divide
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53 Target Report RejectNegative Var(TARGET_INLINE_FLOAT_DIV, 0)
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54
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55 minline-int-divide-min-latency
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56 Target Report RejectNegative Var(TARGET_INLINE_INT_DIV, 1)
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57 Generate inline integer division, optimize for latency
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58
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59 minline-int-divide-max-throughput
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60 Target Report RejectNegative Var(TARGET_INLINE_INT_DIV, 2)
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61 Generate inline integer division, optimize for throughput
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62
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63 mno-inline-int-divide
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64 Target Report RejectNegative Var(TARGET_INLINE_INT_DIV, 0)
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65 Do not inline integer division
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66
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67 minline-sqrt-min-latency
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68 Target Report RejectNegative Var(TARGET_INLINE_SQRT, 1)
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69 Generate inline square root, optimize for latency
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70
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71 minline-sqrt-max-throughput
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72 Target Report RejectNegative Var(TARGET_INLINE_SQRT, 2)
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73 Generate inline square root, optimize for throughput
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74
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75 mno-inline-sqrt
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76 Target Report RejectNegative Var(TARGET_INLINE_SQRT, 0)
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77 Do not inline square root
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78
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79 mdwarf2-asm
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80 Target Report Mask(DWARF2_ASM)
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81 Enable Dwarf 2 line debug info via GNU as
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82
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83 mearly-stop-bits
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84 Target Report Mask(EARLY_STOP_BITS)
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85 Enable earlier placing stop bits for better scheduling
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86
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87 mfixed-range=
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88 Target RejectNegative Joined
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89 Specify range of registers to make fixed
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90
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91 mtls-size=
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92 Target RejectNegative Joined UInteger Var(ia64_tls_size) Init(22)
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93 Specify bit size of immediate TLS offsets
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94
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95 mtune=
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96 Target RejectNegative Joined
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97 Schedule code for given CPU
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98
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99 msched-br-data-spec
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100 Target Report Var(mflag_sched_br_data_spec) Init(0)
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101 Use data speculation before reload
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102
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103 msched-ar-data-spec
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104 Target Report Var(mflag_sched_ar_data_spec) Init(1)
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105 Use data speculation after reload
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106
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107 msched-control-spec
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108 Target Report Var(mflag_sched_control_spec) Init(2)
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109 Use control speculation
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110
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111 msched-br-in-data-spec
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112 Target Report Var(mflag_sched_br_in_data_spec) Init(1)
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113 Use in block data speculation before reload
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114
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115 msched-ar-in-data-spec
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116 Target Report Var(mflag_sched_ar_in_data_spec) Init(1)
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117 Use in block data speculation after reload
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118
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119 msched-in-control-spec
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120 Target Report Var(mflag_sched_in_control_spec) Init(1)
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121 Use in block control speculation
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122
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123 msched-spec-ldc
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124 Target Report Var(mflag_sched_spec_ldc) Init(1)
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125 Use simple data speculation check
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126
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127 msched-spec-control-ldc
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128 Target Report Var(mflag_sched_spec_control_ldc) Init(0)
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129 Use simple data speculation check for control speculation
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130
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131 msched-prefer-non-data-spec-insns
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132 Target Report Var(mflag_sched_prefer_non_data_spec_insns) Init(0)
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133 If set, data speculative instructions will be chosen for schedule only if there are no other choices at the moment
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134
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135 msched-prefer-non-control-spec-insns
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136 Target Report Var(mflag_sched_prefer_non_control_spec_insns) Init(0)
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137 If set, control speculative instructions will be chosen for schedule only if there are no other choices at the moment
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138
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139 msched-count-spec-in-critical-path
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140 Target Report Var(mflag_sched_count_spec_in_critical_path) Init(0)
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141 Count speculative dependencies while calculating priority of instructions
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142
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143 msched-stop-bits-after-every-cycle
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144 Target Report Var(mflag_sched_stop_bits_after_every_cycle) Init(1)
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145 Place a stop bit after every cycle when scheduling
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146
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147 msched-fp-mem-deps-zero-cost
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148 Target Report Var(mflag_sched_fp_mem_deps_zero_cost) Init(0)
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149 Assume that floating-point stores and loads are not likely to cause conflict when placed into one instruction group
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150
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151 msched-max-memory-insns=
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152 Target RejectNegative Joined UInteger Var(ia64_max_memory_insns) Init(1)
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153 Soft limit on number of memory insns per instruction group, giving lower priority to subsequent memory insns attempting to schedule in the same insn group. Frequently useful to prevent cache bank conflicts. Default value is 1
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154
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155 msched-max-memory-insns-hard-limit
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156 Target Report Var(mflag_sched_mem_insns_hard_limit) Init(0)
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157 Disallow more than `msched-max-memory-insns' in instruction group. Otherwise, limit is `soft' (prefer non-memory operations when limit is reached)
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158
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159 msel-sched-dont-check-control-spec
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160 Target Report Var(mflag_sel_sched_dont_check_control_spec) Init(0)
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161 Don't generate checks for control speculation in selective scheduling
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162
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163 ; This comment is to ensure we retain the blank line above.
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