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comparison gcc/config/mips/24k.md @ 0:a06113de4d67

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author kent <kent@cr.ie.u-ryukyu.ac.jp>
date Fri, 17 Jul 2009 14:47:48 +0900
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1 ;; DFA-based pipeline descriptions for MIPS Technologies 24K core.
2 ;; Contributed by Chao-ying Fu (fu@mips.com), Nigel Stephens (nigel@mips.com)
3 ;; and David Ung (davidu@mips.com)
4 ;;
5 ;; The 24kf2_1 is a single-issue processor with a half-clocked fpu.
6 ;; The 24kf1_1 is 24k with 1:1 clocked fpu.
7 ;;
8 ;; References:
9 ;; "MIPS32 24K Processor Core Family Software User's Manual, Rev 3.04."
10 ;;
11 ;; Copyright (C) 2005, 2007 Free Software Foundation, Inc.
12 ;;
13 ;; This file is part of GCC.
14 ;;
15 ;; GCC is free software; you can redistribute it and/or modify it
16 ;; under the terms of the GNU General Public License as published
17 ;; by the Free Software Foundation; either version 3, or (at your
18 ;; option) any later version.
19
20 ;; GCC is distributed in the hope that it will be useful, but WITHOUT
21 ;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
22 ;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
23 ;; License for more details.
24
25 ;; You should have received a copy of the GNU General Public License
26 ;; along with GCC; see the file COPYING3. If not see
27 ;; <http://www.gnu.org/licenses/>.
28
29 (define_automaton "r24k_cpu, r24k_mdu, r24k_fpu")
30
31 ;; Integer execution unit.
32 (define_cpu_unit "r24k_iss" "r24k_cpu")
33 (define_cpu_unit "r24k_ixu_arith" "r24k_cpu")
34 (define_cpu_unit "r24k_mul3a" "r24k_mdu")
35 (define_cpu_unit "r24k_mul3b" "r24k_mdu")
36 (define_cpu_unit "r24k_mul3c" "r24k_mdu")
37
38 ;; --------------------------------------------------------------
39 ;; Producers
40 ;; --------------------------------------------------------------
41
42 ;; 1. Loads: lb, lbu, lh, lhu, ll, lw, lwl, lwr, lwpc, lwxs
43 (define_insn_reservation "r24k_int_load" 2
44 (and (eq_attr "cpu" "24kc,24kf2_1,24kf1_1")
45 (eq_attr "type" "load"))
46 "r24k_iss+r24k_ixu_arith")
47
48
49 ;; 2. Arithmetic: add, addi, addiu, addiupc, addu, and, andi, clo, clz,
50 ;; ext, ins, lui, movn, movz, nor, or, ori, rotr, rotrv, seb, seh, sll,
51 ;; sllv, slt, slti, sltiu, sltu, sra, srav, srl, srlv, sub, subu, wsbh,
52 ;; xor, xori
53 ;; (movn/movz is not matched, we'll need to split condmov to
54 ;; differentiate between integer/float moves)
55 (define_insn_reservation "r24k_int_arith" 1
56 (and (eq_attr "cpu" "24kc,24kf2_1,24kf1_1")
57 (eq_attr "type" "arith,const,logical,move,nop,shift,signext,slt"))
58 "r24k_iss+r24k_ixu_arith")
59
60
61 ;; 3. Links: bgezal, bgezall, bltzal, bltzall, jal, jalr, jalx
62 ;; 3a. jr/jalr consumer
63 (define_insn_reservation "r24k_int_jump" 1
64 (and (eq_attr "cpu" "24kc,24kf2_1,24kf1_1")
65 (eq_attr "type" "call,jump"))
66 "r24k_iss+r24k_ixu_arith")
67
68 ;; 3b. branch consumer
69 (define_insn_reservation "r24k_int_branch" 1
70 (and (eq_attr "cpu" "24kc,24kf2_1,24kf1_1")
71 (eq_attr "type" "branch"))
72 "r24k_iss+r24k_ixu_arith")
73
74
75 ;; 4. MDU: fully pipelined multiplier
76 ;; mult - delivers result to hi/lo in 1 cycle (pipelined)
77 (define_insn_reservation "r24k_int_mult" 1
78 (and (eq_attr "cpu" "24kc,24kf2_1,24kf1_1")
79 (eq_attr "type" "imul"))
80 "r24k_iss+(r24k_mul3a|r24k_mul3b|r24k_mul3c)")
81
82 ;; madd, msub - delivers result to hi/lo in 1 cycle (pipelined)
83 (define_insn_reservation "r24k_int_madd" 1
84 (and (eq_attr "cpu" "24kc,24kf2_1,24kf1_1")
85 (eq_attr "type" "imadd"))
86 "r24k_iss+(r24k_mul3a|r24k_mul3b|r24k_mul3c)")
87
88 ;; mul - delivers result to gpr in 5 cycles
89 (define_insn_reservation "r24k_int_mul3" 5
90 (and (eq_attr "cpu" "24kc,24kf2_1,24kf1_1")
91 (eq_attr "type" "imul3"))
92 "r24k_iss+(r24k_mul3a|r24k_mul3b|r24k_mul3c)*5")
93
94 ;; mfhi, mflo, mflhxu - deliver result to gpr in 5 cycles
95 (define_insn_reservation "r24k_int_mfhilo" 5
96 (and (eq_attr "cpu" "24kc,24kf2_1,24kf1_1")
97 (eq_attr "type" "mfhilo"))
98 "r24k_iss+(r24k_mul3a|r24k_mul3b|r24k_mul3c)")
99
100 ;; mthi, mtlo, mtlhx - deliver result to hi/lo, thence madd, handled as bypass
101 (define_insn_reservation "r24k_int_mthilo" 1
102 (and (eq_attr "cpu" "24kc,24kf2_1,24kf1_1")
103 (eq_attr "type" "mthilo"))
104 "r24k_iss+(r24k_mul3a|r24k_mul3b|r24k_mul3c)")
105
106 ;; div - default to 36 cycles for 32bit operands. Faster for 24bit, 16bit and
107 ;; 8bit, but is tricky to identify.
108 (define_insn_reservation "r24k_int_div" 36
109 (and (eq_attr "cpu" "24kc,24kf2_1,24kf1_1")
110 (eq_attr "type" "idiv"))
111 "r24k_iss+(r24k_mul3a+r24k_mul3b+r24k_mul3c)*36")
112
113
114 ;; 5. Cop: cfc1, di, ei, mfc0, mtc0
115 ;; (Disabled until we add proper cop0 support)
116 ;;(define_insn_reservation "r24k_int_cop" 3
117 ;; (and (eq_attr "cpu" "24kc,24kf2_1,24kf1_1")
118 ;; (eq_attr "type" "cop0"))
119 ;; "r24k_iss+r24k_ixu_arith")
120
121
122 ;; 6. Store
123 (define_insn_reservation "r24k_int_store" 1
124 (and (eq_attr "cpu" "24kc,24kf2_1,24kf1_1")
125 (and (eq_attr "type" "store")
126 (eq_attr "mode" "!unknown")))
127 "r24k_iss+r24k_ixu_arith")
128
129 ;; 6.1 Special case - matches the cprestore pattern which don't set the mode
130 ;; attrib. This avoids being set as r24k_int_store and have it checked
131 ;; against store_data_bypass_p, which would then fail because cprestore
132 ;; does not have a normal SET pattern.
133 (define_insn_reservation "r24k_unknown_store" 1
134 (and (eq_attr "cpu" "24kc,24kf2_1,24kf1_1")
135 (and (eq_attr "type" "store")
136 (eq_attr "mode" "unknown")))
137 "r24k_iss+r24k_ixu_arith")
138
139
140 ;; 7. Multiple instructions
141 (define_insn_reservation "r24k_int_multi" 1
142 (and (eq_attr "cpu" "24kc,24kf2_1,24kf1_1")
143 (eq_attr "type" "multi"))
144 "r24k_iss+r24k_ixu_arith+r24k_fpu_arith+(r24k_mul3a+r24k_mul3b+r24k_mul3c)")
145
146
147 ;; 8. Unknowns - Currently these include blockage, consttable and alignment
148 ;; rtls. They do not really affect scheduling latency, (blockage affects
149 ;; scheduling via log links, but not used here).
150 (define_insn_reservation "r24k_int_unknown" 0
151 (and (eq_attr "cpu" "24kc,24kf2_1,24kf1_1")
152 (eq_attr "type" "unknown"))
153 "r24k_iss")
154
155
156 ;; 9. Prefetch
157 (define_insn_reservation "r24k_int_prefetch" 1
158 (and (eq_attr "cpu" "24kc,24kf2_1,24kf1_1")
159 (eq_attr "type" "prefetch,prefetchx"))
160 "r24k_iss+r24k_ixu_arith")
161
162
163 ;; --------------------------------------------------------------
164 ;; Bypass to Consumer
165 ;; --------------------------------------------------------------
166
167 ;; load->next use : 2 cycles (Default)
168 ;; load->load base: 3 cycles
169 ;; load->store base: 3 cycles
170 ;; load->prefetch: 3 cycles
171 (define_bypass 3 "r24k_int_load" "r24k_int_load")
172 (define_bypass 3 "r24k_int_load" "r24k_int_store" "!store_data_bypass_p")
173 (define_bypass 3 "r24k_int_load" "r24k_int_prefetch")
174
175 ;; arith->next use : 1 cycles (Default)
176 ;; arith->load base: 2 cycles
177 ;; arith->store base: 2 cycles
178 ;; arith->prefetch: 2 cycles
179 (define_bypass 2 "r24k_int_arith" "r24k_int_load")
180 (define_bypass 2 "r24k_int_arith" "r24k_int_store" "!store_data_bypass_p")
181 (define_bypass 2 "r24k_int_arith" "r24k_int_prefetch")
182
183 ;; mul3->next use : 5 cycles (default)
184 ;; mul3->l/s base : 6 cycles
185 ;; mul3->prefetch : 6 cycles
186 (define_bypass 6 "r24k_int_mul3" "r24k_int_load")
187 (define_bypass 6 "r24k_int_mul3" "r24k_int_store" "!store_data_bypass_p")
188 (define_bypass 6 "r24k_int_mul3" "r24k_int_prefetch")
189
190 ;; mul3->madd/msub : 1 cycle
191 (define_bypass 1 "r24k_int_mul3" "r24k_int_madd" "mips_linked_madd_p")
192
193 ;; mfhilo->next use : 5 cycles (default)
194 ;; mfhilo->l/s base : 6 cycles
195 ;; mfhilo->prefetch : 6 cycles
196 ;; mthilo->madd/msub : 2 cycle (only for mthi/lo not mfhi/lo)
197 (define_bypass 6 "r24k_int_mfhilo" "r24k_int_load")
198 (define_bypass 6 "r24k_int_mfhilo" "r24k_int_store" "!store_data_bypass_p")
199 (define_bypass 6 "r24k_int_mfhilo" "r24k_int_prefetch")
200 (define_bypass 2 "r24k_int_mthilo" "r24k_int_madd")
201
202 ;; cop->next use : 3 cycles (Default)
203 ;; cop->l/s base : 4 cycles
204 ;; (define_bypass 4 "r24k_int_cop" "r24k_int_load")
205 ;; (define_bypass 4 "r24k_int_cop" "r24k_int_store" "!store_data_bypass_p")
206
207 ;; multi->next use : 1 cycles (Default)
208 ;; multi->l/s base : 2 cycles
209 ;; multi->prefetch : 2 cycles
210 (define_bypass 2 "r24k_int_multi" "r24k_int_load")
211 (define_bypass 2 "r24k_int_multi" "r24k_int_store" "!store_data_bypass_p")
212 (define_bypass 2 "r24k_int_multi" "r24k_int_prefetch")
213
214
215 ;; --------------------------------------------------------------
216 ;; Floating Point Instructions
217 ;; --------------------------------------------------------------
218
219 (define_cpu_unit "r24k_fpu_arith" "r24k_fpu")
220
221 ;; The 24k is a single issue cpu, and the fpu runs at half clock speed,
222 ;; so each fpu instruction ties up the shared instruction scheduler for
223 ;; 1 cycle, and the fpu scheduler for 2 cycles.
224 ;;
225 ;; These timings are therefore twice the values in the 24K manual,
226 ;; which are quoted in fpu clocks.
227 ;;
228 ;; The 24kf1_1 is a 24k configured with 1:1 cpu and fpu, so use
229 ;; the unscaled timings
230
231 (define_reservation "r24kf2_1_fpu_iss" "r24k_iss+(r24k_fpu_arith*2)")
232
233 ;; fadd, fabs, fneg
234 (define_insn_reservation "r24kf2_1_fadd" 8
235 (and (eq_attr "cpu" "24kf2_1")
236 (eq_attr "type" "fadd,fabs,fneg"))
237 "r24kf2_1_fpu_iss")
238
239 ;; fmove, fcmove
240 (define_insn_reservation "r24kf2_1_fmove" 8
241 (and (eq_attr "cpu" "24kf2_1")
242 (eq_attr "type" "fmove,condmove"))
243 "r24kf2_1_fpu_iss")
244
245 ;; fload
246 (define_insn_reservation "r24kf2_1_fload" 6
247 (and (eq_attr "cpu" "24kf2_1")
248 (eq_attr "type" "fpload,fpidxload"))
249 "r24kf2_1_fpu_iss")
250
251 ;; fstore
252 (define_insn_reservation "r24kf2_1_fstore" 2
253 (and (eq_attr "cpu" "24kf2_1")
254 (eq_attr "type" "fpstore"))
255 "r24kf2_1_fpu_iss")
256
257 ;; fmul, fmadd
258 (define_insn_reservation "r24kf2_1_fmul_sf" 8
259 (and (eq_attr "cpu" "24kf2_1")
260 (and (eq_attr "type" "fmul,fmadd")
261 (eq_attr "mode" "SF")))
262 "r24kf2_1_fpu_iss")
263
264 (define_insn_reservation "r24kf2_1_fmul_df" 10
265 (and (eq_attr "cpu" "24kf2_1")
266 (and (eq_attr "type" "fmul,fmadd")
267 (eq_attr "mode" "DF")))
268 "r24kf2_1_fpu_iss,(r24k_fpu_arith*2)")
269
270
271 ;; fdiv, fsqrt, frsqrt
272 (define_insn_reservation "r24kf2_1_fdiv_sf" 34
273 (and (eq_attr "cpu" "24kf2_1")
274 (and (eq_attr "type" "fdiv,fsqrt,frsqrt")
275 (eq_attr "mode" "SF")))
276 "r24kf2_1_fpu_iss,(r24k_fpu_arith*26)")
277
278 (define_insn_reservation "r24kf2_1_fdiv_df" 64
279 (and (eq_attr "cpu" "24kf2_1")
280 (and (eq_attr "type" "fdiv,fsqrt")
281 (eq_attr "mode" "DF")))
282 "r24kf2_1_fpu_iss,(r24k_fpu_arith*56)")
283
284 ;; frsqrt
285 (define_insn_reservation "r24kf2_1_frsqrt_df" 70
286 (and (eq_attr "cpu" "24kf2_1")
287 (and (eq_attr "type" "frsqrt")
288 (eq_attr "mode" "DF")))
289 "r24kf2_1_fpu_iss,(r24k_fpu_arith*60)")
290
291 ;; fcmp
292 (define_insn_reservation "r24kf2_1_fcmp" 4
293 (and (eq_attr "cpu" "24kf2_1")
294 (eq_attr "type" "fcmp"))
295 "r24kf2_1_fpu_iss")
296
297 ;; fcmp -> movf.fmt & movt.fmt bypass (dependency must be on the condition)
298 (define_bypass 2 "r24kf2_1_fcmp" "r24kf2_1_fmove")
299
300 ;; fcvt (cvt.d.s, cvt.[sd].[wl])
301 (define_insn_reservation "r24kf2_1_fcvt_i2f_s2d" 8
302 (and (eq_attr "cpu" "24kf2_1")
303 (and (eq_attr "type" "fcvt")
304 (eq_attr "cnv_mode" "I2S,I2D,S2D")))
305 "r24kf2_1_fpu_iss")
306
307 ;; fcvt (cvt.s.d)
308 (define_insn_reservation "r24kf2_1_fcvt_s2d" 12
309 (and (eq_attr "cpu" "24kf2_1")
310 (and (eq_attr "type" "fcvt")
311 (eq_attr "cnv_mode" "D2S")))
312 "r24kf2_1_fpu_iss")
313
314 ;; fcvt (cvt.[wl].[sd], etc)
315 (define_insn_reservation "r24kf2_1_fcvt_f2i" 10
316 (and (eq_attr "cpu" "24kf2_1")
317 (and (eq_attr "type" "fcvt")
318 (eq_attr "cnv_mode" "S2I,D2I")))
319 "r24kf2_1_fpu_iss")
320
321 ;; fxfer (mfc1, mfhc1, mtc1, mthc1)
322 (define_insn_reservation "r24kf2_1_fxfer" 4
323 (and (eq_attr "cpu" "24kf2_1")
324 (eq_attr "type" "mfc,mtc"))
325 "r24kf2_1_fpu_iss")
326
327 ;; --------------------------------------------------------------
328 ;; Bypass to Consumer
329 ;; --------------------------------------------------------------
330 ;; r24kf2_1_fcvt_f2i->l/s base : 11 cycles
331 ;; r24kf2_1_fcvt_f2i->prefetch : 11 cycles
332 (define_bypass 11 "r24kf2_1_fcvt_f2i" "r24k_int_load")
333 (define_bypass 11 "r24kf2_1_fcvt_f2i" "r24k_int_store" "!store_data_bypass_p")
334 (define_bypass 11 "r24kf2_1_fcvt_f2i" "r24k_int_prefetch")
335
336 ;; r24kf2_1_fxfer->l/s base : 5 cycles
337 ;; r24kf2_1_fxfer->prefetch : 5 cycles
338 (define_bypass 5 "r24kf2_1_fxfer" "r24k_int_load")
339 (define_bypass 5 "r24kf2_1_fxfer" "r24k_int_store" "!store_data_bypass_p")
340 (define_bypass 5 "r24kf2_1_fxfer" "r24k_int_prefetch")
341
342 ;; --------------------------------------------------------------
343 ;; The 24kf1_1 is a 24k configured with 1:1 cpu and fpu, so use
344 ;; the unscaled timings
345 ;; --------------------------------------------------------------
346
347 (define_reservation "r24kf1_1_fpu_iss" "r24k_iss+r24k_fpu_arith")
348
349 ;; fadd, fabs, fneg
350 (define_insn_reservation "r24kf1_1_fadd" 4
351 (and (eq_attr "cpu" "24kf1_1")
352 (eq_attr "type" "fadd,fabs,fneg"))
353 "r24kf1_1_fpu_iss")
354
355 ;; fmove, fcmove
356 (define_insn_reservation "r24kf1_1_fmove" 4
357 (and (eq_attr "cpu" "24kf1_1")
358 (eq_attr "type" "fmove,condmove"))
359 "r24kf1_1_fpu_iss")
360
361 ;; fload
362 (define_insn_reservation "r24kf1_1_fload" 3
363 (and (eq_attr "cpu" "24kf1_1")
364 (eq_attr "type" "fpload,fpidxload"))
365 "r24kf1_1_fpu_iss")
366
367 ;; fstore
368 (define_insn_reservation "r24kf1_1_fstore" 1
369 (and (eq_attr "cpu" "24kf1_1")
370 (eq_attr "type" "fpstore"))
371 "r24kf1_1_fpu_iss")
372
373 ;; fmul, fmadd
374 (define_insn_reservation "r24kf1_1_fmul_sf" 4
375 (and (eq_attr "cpu" "24kf1_1")
376 (and (eq_attr "type" "fmul,fmadd")
377 (eq_attr "mode" "SF")))
378 "r24kf1_1_fpu_iss")
379
380 (define_insn_reservation "r24kf1_1_fmul_df" 5
381 (and (eq_attr "cpu" "24kf1_1")
382 (and (eq_attr "type" "fmul,fmadd")
383 (eq_attr "mode" "DF")))
384 "r24kf1_1_fpu_iss,r24k_fpu_arith")
385
386
387 ;; fdiv, fsqrt, frsqrt
388 (define_insn_reservation "r24kf1_1_fdiv_sf" 17
389 (and (eq_attr "cpu" "24kf1_1")
390 (and (eq_attr "type" "fdiv,fsqrt,frsqrt")
391 (eq_attr "mode" "SF")))
392 "r24kf1_1_fpu_iss,(r24k_fpu_arith*13)")
393
394 (define_insn_reservation "r24kf1_1_fdiv_df" 32
395 (and (eq_attr "cpu" "24kf1_1")
396 (and (eq_attr "type" "fdiv,fsqrt")
397 (eq_attr "mode" "DF")))
398 "r24kf1_1_fpu_iss,(r24k_fpu_arith*28)")
399
400 ;; frsqrt
401 (define_insn_reservation "r24kf1_1_frsqrt_df" 35
402 (and (eq_attr "cpu" "24kf1_1")
403 (and (eq_attr "type" "frsqrt")
404 (eq_attr "mode" "DF")))
405 "r24kf1_1_fpu_iss,(r24k_fpu_arith*30)")
406
407 ;; fcmp
408 (define_insn_reservation "r24kf1_1_fcmp" 2
409 (and (eq_attr "cpu" "24kf1_1")
410 (eq_attr "type" "fcmp"))
411 "r24kf1_1_fpu_iss")
412
413 ;; fcmp -> movf.fmt & movt.fmt bypass (dependency must be on the condition)
414 (define_bypass 1 "r24kf1_1_fcmp" "r24kf1_1_fmove")
415
416 ;; fcvt (cvt.d.s, cvt.[sd].[wl])
417 (define_insn_reservation "r24kf1_1_fcvt_i2f_s2d" 4
418 (and (eq_attr "cpu" "24kf1_1")
419 (and (eq_attr "type" "fcvt")
420 (eq_attr "cnv_mode" "I2S,I2D,S2D")))
421 "r24kf1_1_fpu_iss")
422
423 ;; fcvt (cvt.s.d)
424 (define_insn_reservation "r24kf1_1_fcvt_s2d" 6
425 (and (eq_attr "cpu" "24kf1_1")
426 (and (eq_attr "type" "fcvt")
427 (eq_attr "cnv_mode" "D2S")))
428 "r24kf1_1_fpu_iss")
429
430 ;; fcvt (cvt.[wl].[sd], etc)
431 (define_insn_reservation "r24kf1_1_fcvt_f2i" 5
432 (and (eq_attr "cpu" "24kf1_1")
433 (and (eq_attr "type" "fcvt")
434 (eq_attr "cnv_mode" "S2I,D2I")))
435 "r24kf1_1_fpu_iss")
436
437 ;; fxfer (mfc1, mfhc1, mtc1, mthc1)
438 (define_insn_reservation "r24kf1_1_fxfer" 2
439 (and (eq_attr "cpu" "24kf1_1")
440 (eq_attr "type" "mfc,mtc"))
441 "r24kf1_1_fpu_iss")
442
443 ;; --------------------------------------------------------------
444 ;; Bypass to Consumer
445 ;; --------------------------------------------------------------
446 ;; r24kf1_1_fcvt_f2i->l/s base : 6 cycles
447 ;; r24kf1_1_fcvt_f2i->prefetch : 6 cycles
448 (define_bypass 6 "r24kf1_1_fcvt_f2i" "r24k_int_load")
449 (define_bypass 6 "r24kf1_1_fcvt_f2i" "r24k_int_store" "!store_data_bypass_p")
450 (define_bypass 6 "r24kf1_1_fcvt_f2i" "r24k_int_prefetch")
451
452 ;; r24kf1_1_fxfer->l/s base : 3 cycles
453 ;; r24kf1_1_fxfer->prefetch : 3 cycles
454 (define_bypass 3 "r24kf1_1_fxfer" "r24k_int_load")
455 (define_bypass 3 "r24kf1_1_fxfer" "r24k_int_store" "!store_data_bypass_p")
456 (define_bypass 3 "r24kf1_1_fxfer" "r24k_int_prefetch")
457