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1 ;; DFA-based pipeline descriptions for MIPS Technologies 24K core.
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2 ;; Contributed by Chao-ying Fu (fu@mips.com), Nigel Stephens (nigel@mips.com)
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3 ;; and David Ung (davidu@mips.com)
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4 ;;
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5 ;; The 24kf2_1 is a single-issue processor with a half-clocked fpu.
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6 ;; The 24kf1_1 is 24k with 1:1 clocked fpu.
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7 ;;
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8 ;; References:
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9 ;; "MIPS32 24K Processor Core Family Software User's Manual, Rev 3.04."
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10 ;;
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11 ;; Copyright (C) 2005, 2007 Free Software Foundation, Inc.
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12 ;;
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13 ;; This file is part of GCC.
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14 ;;
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15 ;; GCC is free software; you can redistribute it and/or modify it
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16 ;; under the terms of the GNU General Public License as published
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17 ;; by the Free Software Foundation; either version 3, or (at your
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18 ;; option) any later version.
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19
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20 ;; GCC is distributed in the hope that it will be useful, but WITHOUT
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21 ;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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22 ;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
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23 ;; License for more details.
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24
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25 ;; You should have received a copy of the GNU General Public License
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26 ;; along with GCC; see the file COPYING3. If not see
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27 ;; <http://www.gnu.org/licenses/>.
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28
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29 (define_automaton "r24k_cpu, r24k_mdu, r24k_fpu")
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30
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31 ;; Integer execution unit.
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32 (define_cpu_unit "r24k_iss" "r24k_cpu")
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33 (define_cpu_unit "r24k_ixu_arith" "r24k_cpu")
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34 (define_cpu_unit "r24k_mul3a" "r24k_mdu")
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35 (define_cpu_unit "r24k_mul3b" "r24k_mdu")
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36 (define_cpu_unit "r24k_mul3c" "r24k_mdu")
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37
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38 ;; --------------------------------------------------------------
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39 ;; Producers
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40 ;; --------------------------------------------------------------
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41
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42 ;; 1. Loads: lb, lbu, lh, lhu, ll, lw, lwl, lwr, lwpc, lwxs
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43 (define_insn_reservation "r24k_int_load" 2
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44 (and (eq_attr "cpu" "24kc,24kf2_1,24kf1_1")
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45 (eq_attr "type" "load"))
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46 "r24k_iss+r24k_ixu_arith")
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47
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48
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49 ;; 2. Arithmetic: add, addi, addiu, addiupc, addu, and, andi, clo, clz,
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50 ;; ext, ins, lui, movn, movz, nor, or, ori, rotr, rotrv, seb, seh, sll,
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51 ;; sllv, slt, slti, sltiu, sltu, sra, srav, srl, srlv, sub, subu, wsbh,
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52 ;; xor, xori
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53 ;; (movn/movz is not matched, we'll need to split condmov to
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54 ;; differentiate between integer/float moves)
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55 (define_insn_reservation "r24k_int_arith" 1
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56 (and (eq_attr "cpu" "24kc,24kf2_1,24kf1_1")
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57 (eq_attr "type" "arith,const,logical,move,nop,shift,signext,slt"))
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58 "r24k_iss+r24k_ixu_arith")
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59
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60
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61 ;; 3. Links: bgezal, bgezall, bltzal, bltzall, jal, jalr, jalx
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62 ;; 3a. jr/jalr consumer
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63 (define_insn_reservation "r24k_int_jump" 1
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64 (and (eq_attr "cpu" "24kc,24kf2_1,24kf1_1")
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65 (eq_attr "type" "call,jump"))
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66 "r24k_iss+r24k_ixu_arith")
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67
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68 ;; 3b. branch consumer
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69 (define_insn_reservation "r24k_int_branch" 1
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70 (and (eq_attr "cpu" "24kc,24kf2_1,24kf1_1")
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71 (eq_attr "type" "branch"))
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72 "r24k_iss+r24k_ixu_arith")
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73
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74
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75 ;; 4. MDU: fully pipelined multiplier
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76 ;; mult - delivers result to hi/lo in 1 cycle (pipelined)
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77 (define_insn_reservation "r24k_int_mult" 1
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78 (and (eq_attr "cpu" "24kc,24kf2_1,24kf1_1")
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79 (eq_attr "type" "imul"))
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80 "r24k_iss+(r24k_mul3a|r24k_mul3b|r24k_mul3c)")
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81
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82 ;; madd, msub - delivers result to hi/lo in 1 cycle (pipelined)
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83 (define_insn_reservation "r24k_int_madd" 1
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84 (and (eq_attr "cpu" "24kc,24kf2_1,24kf1_1")
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85 (eq_attr "type" "imadd"))
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86 "r24k_iss+(r24k_mul3a|r24k_mul3b|r24k_mul3c)")
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87
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88 ;; mul - delivers result to gpr in 5 cycles
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89 (define_insn_reservation "r24k_int_mul3" 5
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90 (and (eq_attr "cpu" "24kc,24kf2_1,24kf1_1")
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91 (eq_attr "type" "imul3"))
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92 "r24k_iss+(r24k_mul3a|r24k_mul3b|r24k_mul3c)*5")
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93
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94 ;; mfhi, mflo, mflhxu - deliver result to gpr in 5 cycles
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95 (define_insn_reservation "r24k_int_mfhilo" 5
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96 (and (eq_attr "cpu" "24kc,24kf2_1,24kf1_1")
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97 (eq_attr "type" "mfhilo"))
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98 "r24k_iss+(r24k_mul3a|r24k_mul3b|r24k_mul3c)")
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99
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100 ;; mthi, mtlo, mtlhx - deliver result to hi/lo, thence madd, handled as bypass
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101 (define_insn_reservation "r24k_int_mthilo" 1
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102 (and (eq_attr "cpu" "24kc,24kf2_1,24kf1_1")
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103 (eq_attr "type" "mthilo"))
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104 "r24k_iss+(r24k_mul3a|r24k_mul3b|r24k_mul3c)")
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105
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106 ;; div - default to 36 cycles for 32bit operands. Faster for 24bit, 16bit and
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107 ;; 8bit, but is tricky to identify.
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108 (define_insn_reservation "r24k_int_div" 36
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109 (and (eq_attr "cpu" "24kc,24kf2_1,24kf1_1")
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110 (eq_attr "type" "idiv"))
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111 "r24k_iss+(r24k_mul3a+r24k_mul3b+r24k_mul3c)*36")
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112
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113
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114 ;; 5. Cop: cfc1, di, ei, mfc0, mtc0
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115 ;; (Disabled until we add proper cop0 support)
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116 ;;(define_insn_reservation "r24k_int_cop" 3
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117 ;; (and (eq_attr "cpu" "24kc,24kf2_1,24kf1_1")
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118 ;; (eq_attr "type" "cop0"))
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119 ;; "r24k_iss+r24k_ixu_arith")
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120
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121
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122 ;; 6. Store
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123 (define_insn_reservation "r24k_int_store" 1
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124 (and (eq_attr "cpu" "24kc,24kf2_1,24kf1_1")
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125 (and (eq_attr "type" "store")
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126 (eq_attr "mode" "!unknown")))
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127 "r24k_iss+r24k_ixu_arith")
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128
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129 ;; 6.1 Special case - matches the cprestore pattern which don't set the mode
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130 ;; attrib. This avoids being set as r24k_int_store and have it checked
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131 ;; against store_data_bypass_p, which would then fail because cprestore
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132 ;; does not have a normal SET pattern.
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133 (define_insn_reservation "r24k_unknown_store" 1
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134 (and (eq_attr "cpu" "24kc,24kf2_1,24kf1_1")
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135 (and (eq_attr "type" "store")
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136 (eq_attr "mode" "unknown")))
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137 "r24k_iss+r24k_ixu_arith")
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138
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139
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140 ;; 7. Multiple instructions
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141 (define_insn_reservation "r24k_int_multi" 1
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142 (and (eq_attr "cpu" "24kc,24kf2_1,24kf1_1")
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143 (eq_attr "type" "multi"))
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144 "r24k_iss+r24k_ixu_arith+r24k_fpu_arith+(r24k_mul3a+r24k_mul3b+r24k_mul3c)")
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145
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146
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147 ;; 8. Unknowns - Currently these include blockage, consttable and alignment
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148 ;; rtls. They do not really affect scheduling latency, (blockage affects
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149 ;; scheduling via log links, but not used here).
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150 (define_insn_reservation "r24k_int_unknown" 0
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151 (and (eq_attr "cpu" "24kc,24kf2_1,24kf1_1")
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152 (eq_attr "type" "unknown"))
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153 "r24k_iss")
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154
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155
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156 ;; 9. Prefetch
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157 (define_insn_reservation "r24k_int_prefetch" 1
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158 (and (eq_attr "cpu" "24kc,24kf2_1,24kf1_1")
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159 (eq_attr "type" "prefetch,prefetchx"))
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160 "r24k_iss+r24k_ixu_arith")
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161
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162
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163 ;; --------------------------------------------------------------
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164 ;; Bypass to Consumer
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165 ;; --------------------------------------------------------------
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166
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167 ;; load->next use : 2 cycles (Default)
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168 ;; load->load base: 3 cycles
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169 ;; load->store base: 3 cycles
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170 ;; load->prefetch: 3 cycles
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171 (define_bypass 3 "r24k_int_load" "r24k_int_load")
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172 (define_bypass 3 "r24k_int_load" "r24k_int_store" "!store_data_bypass_p")
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173 (define_bypass 3 "r24k_int_load" "r24k_int_prefetch")
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174
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175 ;; arith->next use : 1 cycles (Default)
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176 ;; arith->load base: 2 cycles
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177 ;; arith->store base: 2 cycles
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178 ;; arith->prefetch: 2 cycles
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179 (define_bypass 2 "r24k_int_arith" "r24k_int_load")
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180 (define_bypass 2 "r24k_int_arith" "r24k_int_store" "!store_data_bypass_p")
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181 (define_bypass 2 "r24k_int_arith" "r24k_int_prefetch")
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182
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183 ;; mul3->next use : 5 cycles (default)
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184 ;; mul3->l/s base : 6 cycles
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185 ;; mul3->prefetch : 6 cycles
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186 (define_bypass 6 "r24k_int_mul3" "r24k_int_load")
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187 (define_bypass 6 "r24k_int_mul3" "r24k_int_store" "!store_data_bypass_p")
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188 (define_bypass 6 "r24k_int_mul3" "r24k_int_prefetch")
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189
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190 ;; mul3->madd/msub : 1 cycle
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191 (define_bypass 1 "r24k_int_mul3" "r24k_int_madd" "mips_linked_madd_p")
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192
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193 ;; mfhilo->next use : 5 cycles (default)
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194 ;; mfhilo->l/s base : 6 cycles
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195 ;; mfhilo->prefetch : 6 cycles
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196 ;; mthilo->madd/msub : 2 cycle (only for mthi/lo not mfhi/lo)
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197 (define_bypass 6 "r24k_int_mfhilo" "r24k_int_load")
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198 (define_bypass 6 "r24k_int_mfhilo" "r24k_int_store" "!store_data_bypass_p")
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199 (define_bypass 6 "r24k_int_mfhilo" "r24k_int_prefetch")
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200 (define_bypass 2 "r24k_int_mthilo" "r24k_int_madd")
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201
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202 ;; cop->next use : 3 cycles (Default)
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203 ;; cop->l/s base : 4 cycles
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204 ;; (define_bypass 4 "r24k_int_cop" "r24k_int_load")
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205 ;; (define_bypass 4 "r24k_int_cop" "r24k_int_store" "!store_data_bypass_p")
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206
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207 ;; multi->next use : 1 cycles (Default)
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208 ;; multi->l/s base : 2 cycles
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209 ;; multi->prefetch : 2 cycles
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210 (define_bypass 2 "r24k_int_multi" "r24k_int_load")
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211 (define_bypass 2 "r24k_int_multi" "r24k_int_store" "!store_data_bypass_p")
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212 (define_bypass 2 "r24k_int_multi" "r24k_int_prefetch")
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213
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214
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215 ;; --------------------------------------------------------------
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216 ;; Floating Point Instructions
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217 ;; --------------------------------------------------------------
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218
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219 (define_cpu_unit "r24k_fpu_arith" "r24k_fpu")
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220
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221 ;; The 24k is a single issue cpu, and the fpu runs at half clock speed,
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222 ;; so each fpu instruction ties up the shared instruction scheduler for
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223 ;; 1 cycle, and the fpu scheduler for 2 cycles.
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224 ;;
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225 ;; These timings are therefore twice the values in the 24K manual,
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226 ;; which are quoted in fpu clocks.
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227 ;;
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228 ;; The 24kf1_1 is a 24k configured with 1:1 cpu and fpu, so use
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229 ;; the unscaled timings
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230
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231 (define_reservation "r24kf2_1_fpu_iss" "r24k_iss+(r24k_fpu_arith*2)")
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232
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233 ;; fadd, fabs, fneg
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234 (define_insn_reservation "r24kf2_1_fadd" 8
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235 (and (eq_attr "cpu" "24kf2_1")
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236 (eq_attr "type" "fadd,fabs,fneg"))
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237 "r24kf2_1_fpu_iss")
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238
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239 ;; fmove, fcmove
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240 (define_insn_reservation "r24kf2_1_fmove" 8
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241 (and (eq_attr "cpu" "24kf2_1")
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242 (eq_attr "type" "fmove,condmove"))
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243 "r24kf2_1_fpu_iss")
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244
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245 ;; fload
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246 (define_insn_reservation "r24kf2_1_fload" 6
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247 (and (eq_attr "cpu" "24kf2_1")
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248 (eq_attr "type" "fpload,fpidxload"))
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249 "r24kf2_1_fpu_iss")
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250
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251 ;; fstore
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252 (define_insn_reservation "r24kf2_1_fstore" 2
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253 (and (eq_attr "cpu" "24kf2_1")
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254 (eq_attr "type" "fpstore"))
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255 "r24kf2_1_fpu_iss")
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256
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257 ;; fmul, fmadd
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258 (define_insn_reservation "r24kf2_1_fmul_sf" 8
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259 (and (eq_attr "cpu" "24kf2_1")
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260 (and (eq_attr "type" "fmul,fmadd")
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261 (eq_attr "mode" "SF")))
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262 "r24kf2_1_fpu_iss")
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263
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264 (define_insn_reservation "r24kf2_1_fmul_df" 10
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265 (and (eq_attr "cpu" "24kf2_1")
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266 (and (eq_attr "type" "fmul,fmadd")
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267 (eq_attr "mode" "DF")))
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268 "r24kf2_1_fpu_iss,(r24k_fpu_arith*2)")
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269
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270
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271 ;; fdiv, fsqrt, frsqrt
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272 (define_insn_reservation "r24kf2_1_fdiv_sf" 34
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273 (and (eq_attr "cpu" "24kf2_1")
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274 (and (eq_attr "type" "fdiv,fsqrt,frsqrt")
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275 (eq_attr "mode" "SF")))
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276 "r24kf2_1_fpu_iss,(r24k_fpu_arith*26)")
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277
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278 (define_insn_reservation "r24kf2_1_fdiv_df" 64
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279 (and (eq_attr "cpu" "24kf2_1")
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280 (and (eq_attr "type" "fdiv,fsqrt")
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281 (eq_attr "mode" "DF")))
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282 "r24kf2_1_fpu_iss,(r24k_fpu_arith*56)")
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283
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284 ;; frsqrt
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285 (define_insn_reservation "r24kf2_1_frsqrt_df" 70
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286 (and (eq_attr "cpu" "24kf2_1")
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287 (and (eq_attr "type" "frsqrt")
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288 (eq_attr "mode" "DF")))
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289 "r24kf2_1_fpu_iss,(r24k_fpu_arith*60)")
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290
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291 ;; fcmp
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292 (define_insn_reservation "r24kf2_1_fcmp" 4
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293 (and (eq_attr "cpu" "24kf2_1")
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294 (eq_attr "type" "fcmp"))
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295 "r24kf2_1_fpu_iss")
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296
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297 ;; fcmp -> movf.fmt & movt.fmt bypass (dependency must be on the condition)
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298 (define_bypass 2 "r24kf2_1_fcmp" "r24kf2_1_fmove")
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299
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300 ;; fcvt (cvt.d.s, cvt.[sd].[wl])
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301 (define_insn_reservation "r24kf2_1_fcvt_i2f_s2d" 8
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302 (and (eq_attr "cpu" "24kf2_1")
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303 (and (eq_attr "type" "fcvt")
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304 (eq_attr "cnv_mode" "I2S,I2D,S2D")))
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305 "r24kf2_1_fpu_iss")
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306
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307 ;; fcvt (cvt.s.d)
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308 (define_insn_reservation "r24kf2_1_fcvt_s2d" 12
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309 (and (eq_attr "cpu" "24kf2_1")
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310 (and (eq_attr "type" "fcvt")
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311 (eq_attr "cnv_mode" "D2S")))
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312 "r24kf2_1_fpu_iss")
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313
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314 ;; fcvt (cvt.[wl].[sd], etc)
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315 (define_insn_reservation "r24kf2_1_fcvt_f2i" 10
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316 (and (eq_attr "cpu" "24kf2_1")
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317 (and (eq_attr "type" "fcvt")
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318 (eq_attr "cnv_mode" "S2I,D2I")))
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319 "r24kf2_1_fpu_iss")
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320
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321 ;; fxfer (mfc1, mfhc1, mtc1, mthc1)
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322 (define_insn_reservation "r24kf2_1_fxfer" 4
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323 (and (eq_attr "cpu" "24kf2_1")
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324 (eq_attr "type" "mfc,mtc"))
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325 "r24kf2_1_fpu_iss")
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326
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327 ;; --------------------------------------------------------------
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328 ;; Bypass to Consumer
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329 ;; --------------------------------------------------------------
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330 ;; r24kf2_1_fcvt_f2i->l/s base : 11 cycles
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331 ;; r24kf2_1_fcvt_f2i->prefetch : 11 cycles
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332 (define_bypass 11 "r24kf2_1_fcvt_f2i" "r24k_int_load")
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333 (define_bypass 11 "r24kf2_1_fcvt_f2i" "r24k_int_store" "!store_data_bypass_p")
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334 (define_bypass 11 "r24kf2_1_fcvt_f2i" "r24k_int_prefetch")
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335
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336 ;; r24kf2_1_fxfer->l/s base : 5 cycles
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337 ;; r24kf2_1_fxfer->prefetch : 5 cycles
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338 (define_bypass 5 "r24kf2_1_fxfer" "r24k_int_load")
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339 (define_bypass 5 "r24kf2_1_fxfer" "r24k_int_store" "!store_data_bypass_p")
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340 (define_bypass 5 "r24kf2_1_fxfer" "r24k_int_prefetch")
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341
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342 ;; --------------------------------------------------------------
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343 ;; The 24kf1_1 is a 24k configured with 1:1 cpu and fpu, so use
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344 ;; the unscaled timings
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345 ;; --------------------------------------------------------------
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346
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347 (define_reservation "r24kf1_1_fpu_iss" "r24k_iss+r24k_fpu_arith")
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348
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349 ;; fadd, fabs, fneg
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350 (define_insn_reservation "r24kf1_1_fadd" 4
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351 (and (eq_attr "cpu" "24kf1_1")
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352 (eq_attr "type" "fadd,fabs,fneg"))
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353 "r24kf1_1_fpu_iss")
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354
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355 ;; fmove, fcmove
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356 (define_insn_reservation "r24kf1_1_fmove" 4
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357 (and (eq_attr "cpu" "24kf1_1")
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358 (eq_attr "type" "fmove,condmove"))
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359 "r24kf1_1_fpu_iss")
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360
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361 ;; fload
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362 (define_insn_reservation "r24kf1_1_fload" 3
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363 (and (eq_attr "cpu" "24kf1_1")
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364 (eq_attr "type" "fpload,fpidxload"))
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365 "r24kf1_1_fpu_iss")
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366
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367 ;; fstore
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368 (define_insn_reservation "r24kf1_1_fstore" 1
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369 (and (eq_attr "cpu" "24kf1_1")
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370 (eq_attr "type" "fpstore"))
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371 "r24kf1_1_fpu_iss")
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372
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373 ;; fmul, fmadd
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374 (define_insn_reservation "r24kf1_1_fmul_sf" 4
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375 (and (eq_attr "cpu" "24kf1_1")
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376 (and (eq_attr "type" "fmul,fmadd")
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377 (eq_attr "mode" "SF")))
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378 "r24kf1_1_fpu_iss")
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379
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380 (define_insn_reservation "r24kf1_1_fmul_df" 5
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381 (and (eq_attr "cpu" "24kf1_1")
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382 (and (eq_attr "type" "fmul,fmadd")
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383 (eq_attr "mode" "DF")))
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384 "r24kf1_1_fpu_iss,r24k_fpu_arith")
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385
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386
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387 ;; fdiv, fsqrt, frsqrt
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388 (define_insn_reservation "r24kf1_1_fdiv_sf" 17
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389 (and (eq_attr "cpu" "24kf1_1")
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390 (and (eq_attr "type" "fdiv,fsqrt,frsqrt")
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391 (eq_attr "mode" "SF")))
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392 "r24kf1_1_fpu_iss,(r24k_fpu_arith*13)")
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393
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394 (define_insn_reservation "r24kf1_1_fdiv_df" 32
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395 (and (eq_attr "cpu" "24kf1_1")
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396 (and (eq_attr "type" "fdiv,fsqrt")
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397 (eq_attr "mode" "DF")))
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398 "r24kf1_1_fpu_iss,(r24k_fpu_arith*28)")
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399
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400 ;; frsqrt
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401 (define_insn_reservation "r24kf1_1_frsqrt_df" 35
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402 (and (eq_attr "cpu" "24kf1_1")
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403 (and (eq_attr "type" "frsqrt")
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404 (eq_attr "mode" "DF")))
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405 "r24kf1_1_fpu_iss,(r24k_fpu_arith*30)")
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406
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407 ;; fcmp
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408 (define_insn_reservation "r24kf1_1_fcmp" 2
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409 (and (eq_attr "cpu" "24kf1_1")
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410 (eq_attr "type" "fcmp"))
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411 "r24kf1_1_fpu_iss")
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412
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413 ;; fcmp -> movf.fmt & movt.fmt bypass (dependency must be on the condition)
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414 (define_bypass 1 "r24kf1_1_fcmp" "r24kf1_1_fmove")
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415
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416 ;; fcvt (cvt.d.s, cvt.[sd].[wl])
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417 (define_insn_reservation "r24kf1_1_fcvt_i2f_s2d" 4
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418 (and (eq_attr "cpu" "24kf1_1")
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419 (and (eq_attr "type" "fcvt")
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420 (eq_attr "cnv_mode" "I2S,I2D,S2D")))
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421 "r24kf1_1_fpu_iss")
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422
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423 ;; fcvt (cvt.s.d)
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424 (define_insn_reservation "r24kf1_1_fcvt_s2d" 6
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425 (and (eq_attr "cpu" "24kf1_1")
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426 (and (eq_attr "type" "fcvt")
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427 (eq_attr "cnv_mode" "D2S")))
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428 "r24kf1_1_fpu_iss")
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429
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430 ;; fcvt (cvt.[wl].[sd], etc)
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431 (define_insn_reservation "r24kf1_1_fcvt_f2i" 5
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432 (and (eq_attr "cpu" "24kf1_1")
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433 (and (eq_attr "type" "fcvt")
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434 (eq_attr "cnv_mode" "S2I,D2I")))
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435 "r24kf1_1_fpu_iss")
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436
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437 ;; fxfer (mfc1, mfhc1, mtc1, mthc1)
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438 (define_insn_reservation "r24kf1_1_fxfer" 2
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439 (and (eq_attr "cpu" "24kf1_1")
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440 (eq_attr "type" "mfc,mtc"))
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441 "r24kf1_1_fpu_iss")
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442
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443 ;; --------------------------------------------------------------
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444 ;; Bypass to Consumer
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445 ;; --------------------------------------------------------------
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446 ;; r24kf1_1_fcvt_f2i->l/s base : 6 cycles
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447 ;; r24kf1_1_fcvt_f2i->prefetch : 6 cycles
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448 (define_bypass 6 "r24kf1_1_fcvt_f2i" "r24k_int_load")
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449 (define_bypass 6 "r24kf1_1_fcvt_f2i" "r24k_int_store" "!store_data_bypass_p")
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450 (define_bypass 6 "r24kf1_1_fcvt_f2i" "r24k_int_prefetch")
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451
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452 ;; r24kf1_1_fxfer->l/s base : 3 cycles
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453 ;; r24kf1_1_fxfer->prefetch : 3 cycles
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454 (define_bypass 3 "r24kf1_1_fxfer" "r24k_int_load")
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455 (define_bypass 3 "r24kf1_1_fxfer" "r24k_int_store" "!store_data_bypass_p")
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456 (define_bypass 3 "r24kf1_1_fxfer" "r24k_int_prefetch")
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457
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