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comparison gcc/config/mips/7000.md @ 0:a06113de4d67

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author kent <kent@cr.ie.u-ryukyu.ac.jp>
date Fri, 17 Jul 2009 14:47:48 +0900
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1 ;; DFA-based pipeline description for the RM7000.
2 ;; Copyright (C) 2003, 2004, 2005, 2007 Free Software Foundation, Inc.
3 ;;
4 ;; This file is part of GCC.
5
6 ;; GCC is free software; you can redistribute it and/or modify it
7 ;; under the terms of the GNU General Public License as published
8 ;; by the Free Software Foundation; either version 3, or (at your
9 ;; option) any later version.
10
11 ;; GCC is distributed in the hope that it will be useful, but WITHOUT
12 ;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
13 ;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
14 ;; License for more details.
15
16 ;; You should have received a copy of the GNU General Public License
17 ;; along with GCC; see the file COPYING3. If not see
18 ;; <http://www.gnu.org/licenses/>.
19
20 ;; .........................
21 ;;
22 ;; The RM7000 is a dual-issue processor that can bundle instructions as:
23 ;; {arith|load|store}{arith|imul|idiv|branch|float}
24 ;;
25 ;; Reference:
26 ;; "RM7000 Family User Manual, PMC-2002296"
27 ;;
28 ;; .........................
29
30 ;; Use three automata to isolate long latency operations, reducing space.
31 (define_automaton "rm7000_other, rm7000_fdiv, rm7000_idiv")
32
33 ;;
34 ;; Describe the resources.
35 ;;
36
37 ;; Global
38 (define_cpu_unit "rm7_iss0,rm7_iss1" "rm7000_other")
39
40 ;; Integer execution unit (M-Pipe).
41 (define_cpu_unit "ixum_addsub_agen" "rm7000_other")
42
43 ;; Integer execution unit (F-Pipe).
44 (define_cpu_unit "ixuf_addsub" "rm7000_other")
45 (define_cpu_unit "ixuf_branch" "rm7000_other")
46 (define_cpu_unit "ixuf_mpydiv" "rm7000_other")
47 (define_cpu_unit "ixuf_mpydiv_iter" "rm7000_idiv")
48 ;; Floating-point unit (F-Pipe).
49 (define_cpu_unit "fxuf_add" "rm7000_other")
50 (define_cpu_unit "fxuf_mpy" "rm7000_other")
51 (define_cpu_unit "fxuf_mpy_iter" "rm7000_fdiv")
52 (define_cpu_unit "fxuf_divsqrt" "rm7000_other")
53 (define_cpu_unit "fxuf_divsqrt_iter" "rm7000_fdiv")
54
55 (exclusion_set "ixuf_addsub"
56 "ixuf_branch,ixuf_mpydiv,fxuf_add,fxuf_mpy,fxuf_divsqrt")
57 (exclusion_set "ixuf_branch" "ixuf_mpydiv,fxuf_add,fxuf_mpy,fxuf_divsqrt")
58 (exclusion_set "ixuf_mpydiv" "fxuf_add,fxuf_mpy,fxuf_divsqrt")
59 (exclusion_set "fxuf_add" "fxuf_mpy,fxuf_divsqrt")
60 (exclusion_set "fxuf_mpy" "fxuf_divsqrt")
61
62 ;; After branch any insn cannot be issued.
63 (absence_set "rm7_iss0,rm7_iss1" "ixuf_branch")
64
65 ;;
66 ;; Define reservations for unit name mnemonics or combinations.
67 ;;
68
69 (define_reservation "rm7_iss" "rm7_iss0|rm7_iss1")
70 (define_reservation "rm7_single_dispatch" "rm7_iss0+rm7_iss1")
71
72 (define_reservation "rm7_iaddsub" "rm7_iss+(ixum_addsub_agen|ixuf_addsub)")
73 (define_reservation "rm7_imem" "rm7_iss+ixum_addsub_agen")
74 (define_reservation "rm7_impydiv" "rm7_iss+ixuf_mpydiv")
75 (define_reservation "rm7_impydiv_iter" "ixuf_mpydiv_iter")
76 (define_reservation "rm7_branch" "rm7_iss+ixuf_branch")
77
78 (define_reservation "rm7_fpadd" "rm7_iss+fxuf_add")
79 (define_reservation "rm7_fpmpy" "rm7_iss+fxuf_mpy")
80 (define_reservation "rm7_fpmpy_iter" "fxuf_mpy_iter")
81 (define_reservation "rm7_fpdivsqr" "rm7_iss+fxuf_divsqrt")
82 (define_reservation "rm7_fpdivsqr_iter" "fxuf_divsqrt_iter")
83
84 ;;
85 ;; Describe instruction reservations for integer operations.
86 ;;
87
88 (define_insn_reservation "rm7_int_other" 1
89 (and (eq_attr "cpu" "r7000")
90 (eq_attr "type" "arith,shift,signext,slt,clz,const,condmove,logical,move,nop,trap"))
91 "rm7_iaddsub")
92
93 (define_insn_reservation "rm7_ld" 2
94 (and (eq_attr "cpu" "r7000")
95 (eq_attr "type" "load,fpload,fpidxload"))
96 "rm7_imem")
97
98 (define_insn_reservation "rm7_st" 1
99 (and (eq_attr "cpu" "r7000")
100 (eq_attr "type" "store,fpstore,fpidxstore"))
101 "rm7_imem")
102
103 (define_insn_reservation "rm7_idiv_si" 36
104 (and (eq_attr "cpu" "r7000")
105 (and (eq_attr "type" "idiv")
106 (eq_attr "mode" "SI")))
107 "rm7_impydiv+(rm7_impydiv_iter*36)")
108
109 (define_insn_reservation "rm7_idiv_di" 68
110 (and (eq_attr "cpu" "r7000")
111 (and (eq_attr "type" "idiv")
112 (eq_attr "mode" "DI")))
113 "rm7_impydiv+(rm7_impydiv_iter*68)")
114
115 (define_insn_reservation "rm7_impy_si_mult" 5
116 (and (eq_attr "cpu" "r7000")
117 (and (eq_attr "type" "imul,imadd")
118 (eq_attr "mode" "SI")))
119 "rm7_impydiv+(rm7_impydiv_iter*3)")
120
121 ;; There are an additional 2 stall cycles.
122 (define_insn_reservation "rm7_impy_si_mul" 2
123 (and (eq_attr "cpu" "r7000")
124 (and (eq_attr "type" "imul3")
125 (eq_attr "mode" "SI")))
126 "rm7_impydiv")
127
128 (define_insn_reservation "rm7_impy_di" 9
129 (and (eq_attr "cpu" "r7000")
130 (and (eq_attr "type" "imul,imul3")
131 (eq_attr "mode" "DI")))
132 "rm7_impydiv+(rm7_impydiv_iter*8)")
133
134 ;; Move to/from HI/LO.
135 (define_insn_reservation "rm7_mthilo" 3
136 (and (eq_attr "cpu" "r7000")
137 (eq_attr "type" "mthilo"))
138 "rm7_impydiv")
139
140 (define_insn_reservation "rm7_mfhilo" 1
141 (and (eq_attr "cpu" "r7000")
142 (eq_attr "type" "mfhilo"))
143 "rm7_impydiv")
144
145 ;; Move to/from fp coprocessor.
146 (define_insn_reservation "rm7_ixfer" 2
147 (and (eq_attr "cpu" "r7000")
148 (eq_attr "type" "mfc,mtc"))
149 "rm7_iaddsub")
150
151 (define_insn_reservation "rm7_ibr" 3
152 (and (eq_attr "cpu" "r7000")
153 (eq_attr "type" "branch,jump,call"))
154 "rm7_branch")
155
156 ;;
157 ;; Describe instruction reservations for the floating-point operations.
158 ;;
159 (define_insn_reservation "rm7_fp_quick" 4
160 (and (eq_attr "cpu" "r7000")
161 (eq_attr "type" "fneg,fcmp,fabs,fmove"))
162 "rm7_fpadd")
163
164 (define_insn_reservation "rm7_fp_other" 4
165 (and (eq_attr "cpu" "r7000")
166 (eq_attr "type" "fadd"))
167 "rm7_fpadd")
168
169 (define_insn_reservation "rm7_fp_cvt" 4
170 (and (eq_attr "cpu" "r7000")
171 (eq_attr "type" "fcvt"))
172 "rm7_fpadd")
173
174 (define_insn_reservation "rm7_fp_divsqrt_df" 36
175 (and (eq_attr "cpu" "r7000")
176 (and (eq_attr "type" "fdiv,frdiv,fsqrt")
177 (eq_attr "mode" "DF")))
178 "rm7_fpdivsqr+(rm7_fpdivsqr_iter*36)")
179
180 (define_insn_reservation "rm7_fp_divsqrt_sf" 21
181 (and (eq_attr "cpu" "r7000")
182 (and (eq_attr "type" "fdiv,frdiv,fsqrt")
183 (eq_attr "mode" "SF")))
184 "rm7_fpdivsqr+(rm7_fpdivsqr_iter*21)")
185
186 (define_insn_reservation "rm7_fp_rsqrt_df" 68
187 (and (eq_attr "cpu" "r7000")
188 (and (eq_attr "type" "frsqrt")
189 (eq_attr "mode" "DF")))
190 "rm7_fpdivsqr+(rm7_fpdivsqr_iter*68)")
191
192 (define_insn_reservation "rm7_fp_rsqrt_sf" 38
193 (and (eq_attr "cpu" "r7000")
194 (and (eq_attr "type" "frsqrt")
195 (eq_attr "mode" "SF")))
196 "rm7_fpdivsqr+(rm7_fpdivsqr_iter*38)")
197
198 (define_insn_reservation "rm7_fp_mpy_sf" 4
199 (and (eq_attr "cpu" "r7000")
200 (and (eq_attr "type" "fmul,fmadd")
201 (eq_attr "mode" "SF")))
202 "rm7_fpmpy+rm7_fpmpy_iter")
203
204 (define_insn_reservation "rm7_fp_mpy_df" 5
205 (and (eq_attr "cpu" "r7000")
206 (and (eq_attr "type" "fmul,fmadd")
207 (eq_attr "mode" "DF")))
208 "rm7_fpmpy+(rm7_fpmpy_iter*2)")
209
210 ;; Force single-dispatch for unknown or multi.
211 (define_insn_reservation "rm7_unknown" 1
212 (and (eq_attr "cpu" "r7000")
213 (eq_attr "type" "unknown,multi"))
214 "rm7_single_dispatch")