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comparison gcc/config/pa/pa32-regs.h @ 0:a06113de4d67

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author kent <kent@cr.ie.u-ryukyu.ac.jp>
date Fri, 17 Jul 2009 14:47:48 +0900
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1 /* Standard register usage. */
2
3 /* Number of actual hardware registers.
4 The hardware registers are assigned numbers for the compiler
5 from 0 to just below FIRST_PSEUDO_REGISTER.
6 All registers that the compiler knows about must be given numbers,
7 even those that are not normally considered general registers.
8
9 HP-PA 1.0 has 32 fullword registers and 16 floating point
10 registers. The floating point registers hold either word or double
11 word values.
12
13 16 additional registers are reserved.
14
15 HP-PA 1.1 has 32 fullword registers and 32 floating point
16 registers. However, the floating point registers behave
17 differently: the left and right halves of registers are addressable
18 as 32-bit registers. So, we will set things up like the 68k which
19 has different fp units: define separate register sets for the 1.0
20 and 1.1 fp units. */
21
22 #define FIRST_PSEUDO_REGISTER 89 /* 32 general regs + 56 fp regs +
23 + 1 shift reg */
24
25 /* 1 for registers that have pervasive standard uses
26 and are not available for the register allocator.
27
28 On the HP-PA, these are:
29 Reg 0 = 0 (hardware). However, 0 is used for condition code,
30 so is not fixed.
31 Reg 1 = ADDIL target/Temporary (hardware).
32 Reg 2 = Return Pointer
33 Reg 3 = Frame Pointer
34 Reg 4 = Frame Pointer (>8k varying frame with HP compilers only)
35 Reg 4-18 = Preserved Registers
36 Reg 19 = Linkage Table Register in HPUX 8.0 shared library scheme.
37 Reg 20-22 = Temporary Registers
38 Reg 23-26 = Temporary/Parameter Registers
39 Reg 27 = Global Data Pointer (hp)
40 Reg 28 = Temporary/Return Value register
41 Reg 29 = Temporary/Static Chain/Return Value register #2
42 Reg 30 = stack pointer
43 Reg 31 = Temporary/Millicode Return Pointer (hp)
44
45 Freg 0-3 = Status Registers -- Not known to the compiler.
46 Freg 4-7 = Arguments/Return Value
47 Freg 8-11 = Temporary Registers
48 Freg 12-15 = Preserved Registers
49
50 Freg 16-31 = Reserved
51
52 On the Snake, fp regs are
53
54 Freg 0-3 = Status Registers -- Not known to the compiler.
55 Freg 4L-7R = Arguments/Return Value
56 Freg 8L-11R = Temporary Registers
57 Freg 12L-21R = Preserved Registers
58 Freg 22L-31R = Temporary Registers
59
60 */
61
62 #define FIXED_REGISTERS \
63 {0, 0, 0, 0, 0, 0, 0, 0, \
64 0, 0, 0, 0, 0, 0, 0, 0, \
65 0, 0, 0, 0, 0, 0, 0, 0, \
66 0, 0, 0, 1, 0, 0, 1, 0, \
67 /* fp registers */ \
68 0, 0, 0, 0, 0, 0, 0, 0, \
69 0, 0, 0, 0, 0, 0, 0, 0, \
70 0, 0, 0, 0, 0, 0, 0, 0, \
71 0, 0, 0, 0, 0, 0, 0, 0, \
72 0, 0, 0, 0, 0, 0, 0, 0, \
73 0, 0, 0, 0, 0, 0, 0, 0, \
74 0, 0, 0, 0, 0, 0, 0, 0, \
75 0}
76
77 /* 1 for registers not available across function calls.
78 These must include the FIXED_REGISTERS and also any
79 registers that can be used without being saved.
80 The latter must include the registers where values are returned
81 and the register where structure-value addresses are passed.
82 Aside from that, you can include as many other registers as you like. */
83 #define CALL_USED_REGISTERS \
84 {1, 1, 1, 0, 0, 0, 0, 0, \
85 0, 0, 0, 0, 0, 0, 0, 0, \
86 0, 0, 0, 1, 1, 1, 1, 1, \
87 1, 1, 1, 1, 1, 1, 1, 1, \
88 /* fp registers */ \
89 1, 1, 1, 1, 1, 1, 1, 1, \
90 1, 1, 1, 1, 1, 1, 1, 1, \
91 0, 0, 0, 0, 0, 0, 0, 0, \
92 0, 0, 0, 0, 0, 0, 0, 0, \
93 0, 0, 0, 0, 1, 1, 1, 1, \
94 1, 1, 1, 1, 1, 1, 1, 1, \
95 1, 1, 1, 1, 1, 1, 1, 1, \
96 1}
97
98 #define CONDITIONAL_REGISTER_USAGE \
99 { \
100 int i; \
101 if (!TARGET_PA_11) \
102 { \
103 for (i = 56; i < 88; i++) \
104 fixed_regs[i] = call_used_regs[i] = 1; \
105 for (i = 33; i < 88; i += 2) \
106 fixed_regs[i] = call_used_regs[i] = 1; \
107 } \
108 if (TARGET_DISABLE_FPREGS || TARGET_SOFT_FLOAT)\
109 { \
110 for (i = 32; i < 88; i++) \
111 fixed_regs[i] = call_used_regs[i] = 1; \
112 } \
113 if (flag_pic) \
114 fixed_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \
115 }
116
117 /* Allocate the call used registers first. This should minimize
118 the number of registers that need to be saved (as call used
119 registers will generally not be allocated across a call).
120
121 Experimentation has shown slightly better results by allocating
122 FP registers first. We allocate the caller-saved registers more
123 or less in reverse order to their allocation as arguments.
124
125 FP registers are ordered so that all L registers are selected before
126 R registers. This works around a false dependency interlock on the
127 PA8000 when accessing the high and low parts of an FP register
128 independently. */
129
130 #define REG_ALLOC_ORDER \
131 { \
132 /* caller-saved fp regs. */ \
133 68, 70, 72, 74, 76, 78, 80, 82, \
134 84, 86, 40, 42, 44, 46, 38, 36, \
135 34, 32, \
136 69, 71, 73, 75, 77, 79, 81, 83, \
137 85, 87, 41, 43, 45, 47, 39, 37, \
138 35, 33, \
139 /* caller-saved general regs. */ \
140 28, 19, 20, 21, 22, 31, 27, 29, \
141 23, 24, 25, 26, 2, \
142 /* callee-saved fp regs. */ \
143 48, 50, 52, 54, 56, 58, 60, 62, \
144 64, 66, \
145 49, 51, 53, 55, 57, 59, 61, 63, \
146 65, 67, \
147 /* callee-saved general regs. */ \
148 3, 4, 5, 6, 7, 8, 9, 10, \
149 11, 12, 13, 14, 15, 16, 17, 18, \
150 /* special registers. */ \
151 1, 30, 0, 88}
152
153
154 /* Return number of consecutive hard regs needed starting at reg REGNO
155 to hold something of mode MODE.
156 This is ordinarily the length in words of a value of mode MODE
157 but can be less for certain modes in special long registers.
158
159 On the HP-PA, general registers are 32 bits wide. The floating
160 point registers are 64 bits wide. Snake fp regs are treated as
161 32 bits wide since the left and right parts are independently
162 accessible. */
163 #define HARD_REGNO_NREGS(REGNO, MODE) \
164 (FP_REGNO_P (REGNO) \
165 ? (!TARGET_PA_11 \
166 ? COMPLEX_MODE_P (MODE) ? 2 : 1 \
167 : (GET_MODE_SIZE (MODE) + 4 - 1) / 4) \
168 : (GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
169
170 /* There are no instructions that use DImode in PA 1.0, so we only
171 allow it in PA 1.1 and later. */
172 #define VALID_FP_MODE_P(MODE) \
173 ((MODE) == SFmode || (MODE) == DFmode \
174 || (MODE) == SCmode || (MODE) == DCmode \
175 || (MODE) == SImode || (TARGET_PA_11 && (MODE) == DImode))
176
177 /* Value is 1 if hard register REGNO can hold a value of machine-mode MODE.
178
179 On the HP-PA, the cpu registers can hold any mode that fits in 32 bits.
180 For the 64-bit modes, we choose a set of non-overlapping general registers
181 that includes the incoming arguments and the return value. We specify a
182 set with no overlaps so that we don't have to specify that the destination
183 register is an early clobber in patterns using this mode. Except for the
184 return value, the starting registers are odd. For 128 and 256 bit modes,
185 we similarly specify non-overlapping sets of cpu registers. However,
186 there aren't any patterns defined for modes larger than 64 bits at the
187 moment.
188
189 We limit the modes allowed in the floating point registers to the
190 set of modes used in the machine definition. In addition, we allow
191 the complex modes SCmode and DCmode. The real and imaginary parts
192 of complex modes are allocated to separate registers. This might
193 allow patterns to be defined in the future to operate on these values.
194
195 The PA 2.0 architecture specifies that quad-precision floating-point
196 values should start on an even floating point register. Thus, we
197 choose non-overlapping sets of registers starting on even register
198 boundaries for large modes. However, there is currently no support
199 in the machine definition for modes larger than 64 bits. TFmode is
200 supported under HP-UX using libcalls. Since TFmode values are passed
201 by reference, they never need to be loaded into the floating-point
202 registers. */
203 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
204 ((REGNO) == 0 ? (MODE) == CCmode || (MODE) == CCFPmode \
205 : !TARGET_PA_11 && FP_REGNO_P (REGNO) \
206 ? (VALID_FP_MODE_P (MODE) \
207 && (GET_MODE_SIZE (MODE) <= 8 \
208 || (GET_MODE_SIZE (MODE) == 16 && ((REGNO) & 3) == 0))) \
209 : FP_REGNO_P (REGNO) \
210 ? (VALID_FP_MODE_P (MODE) \
211 && (GET_MODE_SIZE (MODE) <= 4 \
212 || (GET_MODE_SIZE (MODE) == 8 && ((REGNO) & 1) == 0) \
213 || (GET_MODE_SIZE (MODE) == 16 && ((REGNO) & 3) == 0) \
214 || (GET_MODE_SIZE (MODE) == 32 && ((REGNO) & 7) == 0))) \
215 : (GET_MODE_SIZE (MODE) <= UNITS_PER_WORD \
216 || (GET_MODE_SIZE (MODE) == 2 * UNITS_PER_WORD \
217 && ((((REGNO) & 1) == 1 && (REGNO) <= 25) || (REGNO) == 28)) \
218 || (GET_MODE_SIZE (MODE) == 4 * UNITS_PER_WORD \
219 && ((REGNO) & 3) == 3 && (REGNO) <= 23) \
220 || (GET_MODE_SIZE (MODE) == 8 * UNITS_PER_WORD \
221 && ((REGNO) & 7) == 3 && (REGNO) <= 19)))
222
223 /* How to renumber registers for dbx and gdb.
224
225 Registers 0 - 31 remain unchanged.
226
227 Registers 32 - 87 are mapped to 72 - 127
228
229 Register 88 is mapped to 32. */
230
231 #define DBX_REGISTER_NUMBER(REGNO) \
232 ((REGNO) <= 31 ? (REGNO) : \
233 ((REGNO) <= 87 ? (REGNO) + 40 : 32))
234
235 /* We must not use the DBX register numbers for the DWARF 2 CFA column
236 numbers because that maps to numbers beyond FIRST_PSEUDO_REGISTER.
237 Instead use the identity mapping. */
238 #define DWARF_FRAME_REGNUM(REG) REG
239
240 /* Define the classes of registers for register constraints in the
241 machine description. Also define ranges of constants.
242
243 One of the classes must always be named ALL_REGS and include all hard regs.
244 If there is more than one class, another class must be named NO_REGS
245 and contain no registers.
246
247 The name GENERAL_REGS must be the name of a class (or an alias for
248 another name such as ALL_REGS). This is the class of registers
249 that is allowed by "g" or "r" in a register constraint.
250 Also, registers outside this class are allocated only when
251 instructions express preferences for them.
252
253 The classes must be numbered in nondecreasing order; that is,
254 a larger-numbered class must never be contained completely
255 in a smaller-numbered class.
256
257 For any two classes, it is very desirable that there be another
258 class that represents their union. */
259
260 /* The HP-PA has four kinds of registers: general regs, 1.0 fp regs,
261 1.1 fp regs, and the high 1.1 fp regs, to which the operands of
262 fmpyadd and fmpysub are restricted. */
263
264 enum reg_class { NO_REGS, R1_REGS, GENERAL_REGS, FPUPPER_REGS, FP_REGS,
265 GENERAL_OR_FP_REGS, SHIFT_REGS, ALL_REGS, LIM_REG_CLASSES};
266
267 #define N_REG_CLASSES (int) LIM_REG_CLASSES
268
269 /* Give names of register classes as strings for dump file. */
270
271 #define REG_CLASS_NAMES \
272 {"NO_REGS", "R1_REGS", "GENERAL_REGS", "FPUPPER_REGS", "FP_REGS", \
273 "GENERAL_OR_FP_REGS", "SHIFT_REGS", "ALL_REGS"}
274
275 /* Define which registers fit in which classes.
276 This is an initializer for a vector of HARD_REG_SET
277 of length N_REG_CLASSES. Register 0, the "condition code" register,
278 is in no class. */
279
280 #define REG_CLASS_CONTENTS \
281 {{0x00000000, 0x00000000, 0x00000000}, /* NO_REGS */ \
282 {0x00000002, 0x00000000, 0x00000000}, /* R1_REGS */ \
283 {0xfffffffe, 0x00000000, 0x00000000}, /* GENERAL_REGS */ \
284 {0x00000000, 0xff000000, 0x00ffffff}, /* FPUPPER_REGS */ \
285 {0x00000000, 0xffffffff, 0x00ffffff}, /* FP_REGS */ \
286 {0xfffffffe, 0xffffffff, 0x00ffffff}, /* GENERAL_OR_FP_REGS */ \
287 {0x00000000, 0x00000000, 0x01000000}, /* SHIFT_REGS */ \
288 {0xfffffffe, 0xffffffff, 0x01ffffff}} /* ALL_REGS */
289
290 /* The following macro defines cover classes for Integrated Register
291 Allocator. Cover classes is a set of non-intersected register
292 classes covering all hard registers used for register allocation
293 purpose. Any move between two registers of a cover class should be
294 cheaper than load or store of the registers. The macro value is
295 array of register classes with LIM_REG_CLASSES used as the end
296 marker. */
297
298 #define IRA_COVER_CLASSES \
299 { \
300 GENERAL_REGS, FP_REGS, SHIFT_REGS, LIM_REG_CLASSES \
301 }
302
303 /* Defines invalid mode changes. */
304
305 #define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS) \
306 pa_cannot_change_mode_class (FROM, TO, CLASS)
307
308 /* Return the class number of the smallest class containing
309 reg number REGNO. This could be a conditional expression
310 or could index an array. */
311
312 #define REGNO_REG_CLASS(REGNO) \
313 ((REGNO) == 0 ? NO_REGS \
314 : (REGNO) == 1 ? R1_REGS \
315 : (REGNO) < 32 ? GENERAL_REGS \
316 : (REGNO) < 56 ? FP_REGS \
317 : (REGNO) < 88 ? FPUPPER_REGS \
318 : SHIFT_REGS)
319
320 /* Return the maximum number of consecutive registers
321 needed to represent mode MODE in a register of class CLASS. */
322 #define CLASS_MAX_NREGS(CLASS, MODE) \
323 ((CLASS) == FP_REGS || (CLASS) == FPUPPER_REGS \
324 ? (!TARGET_PA_11 \
325 ? COMPLEX_MODE_P (MODE) ? 2 : 1 \
326 : (GET_MODE_SIZE (MODE) + 4 - 1) / 4) \
327 : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD))
328
329 /* 1 if N is a possible register number for function argument passing. */
330
331 #define FUNCTION_ARG_REGNO_P(N) \
332 (((N) >= 23 && (N) <= 26) || (! TARGET_SOFT_FLOAT && (N) >= 32 && (N) <= 39))
333
334 /* How to refer to registers in assembler output.
335 This sequence is indexed by compiler's hard-register-number (see above). */
336
337 #define REGISTER_NAMES \
338 {"%r0", "%r1", "%r2", "%r3", "%r4", "%r5", "%r6", "%r7", \
339 "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15", \
340 "%r16", "%r17", "%r18", "%r19", "%r20", "%r21", "%r22", "%r23", \
341 "%r24", "%r25", "%r26", "%r27", "%r28", "%r29", "%r30", "%r31", \
342 "%fr4", "%fr4R", "%fr5", "%fr5R", "%fr6", "%fr6R", "%fr7", "%fr7R", \
343 "%fr8", "%fr8R", "%fr9", "%fr9R", "%fr10", "%fr10R", "%fr11", "%fr11R", \
344 "%fr12", "%fr12R", "%fr13", "%fr13R", "%fr14", "%fr14R", "%fr15", "%fr15R", \
345 "%fr16", "%fr16R", "%fr17", "%fr17R", "%fr18", "%fr18R", "%fr19", "%fr19R", \
346 "%fr20", "%fr20R", "%fr21", "%fr21R", "%fr22", "%fr22R", "%fr23", "%fr23R", \
347 "%fr24", "%fr24R", "%fr25", "%fr25R", "%fr26", "%fr26R", "%fr27", "%fr27R", \
348 "%fr28", "%fr28R", "%fr29", "%fr29R", "%fr30", "%fr30R", "%fr31", "%fr31R", \
349 "SAR"}
350
351 #define ADDITIONAL_REGISTER_NAMES \
352 {{"%fr4L",32}, {"%fr5L",34}, {"%fr6L",36}, {"%fr7L",38}, \
353 {"%fr8L",40}, {"%fr9L",42}, {"%fr10L",44}, {"%fr11L",46}, \
354 {"%fr12L",48}, {"%fr13L",50}, {"%fr14L",52}, {"%fr15L",54}, \
355 {"%fr16L",56}, {"%fr17L",58}, {"%fr18L",60}, {"%fr19L",62}, \
356 {"%fr20L",64}, {"%fr21L",66}, {"%fr22L",68}, {"%fr23L",70}, \
357 {"%fr24L",72}, {"%fr25L",74}, {"%fr26L",76}, {"%fr27L",78}, \
358 {"%fr28L",80}, {"%fr29L",82}, {"%fr30L",84}, {"%fr31R",86}, \
359 {"%cr11",88}}
360
361 #define FP_SAVED_REG_LAST 66
362 #define FP_SAVED_REG_FIRST 48
363 #define FP_REG_STEP 2
364 #define FP_REG_FIRST 32
365 #define FP_REG_LAST 87