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0
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1 /* Standard register usage. */
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2
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3 /* Number of actual hardware registers.
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4 The hardware registers are assigned numbers for the compiler
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5 from 0 to just below FIRST_PSEUDO_REGISTER.
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6 All registers that the compiler knows about must be given numbers,
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7 even those that are not normally considered general registers.
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8
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9 HP-PA 1.0 has 32 fullword registers and 16 floating point
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10 registers. The floating point registers hold either word or double
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11 word values.
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12
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13 16 additional registers are reserved.
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14
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15 HP-PA 1.1 has 32 fullword registers and 32 floating point
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16 registers. However, the floating point registers behave
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17 differently: the left and right halves of registers are addressable
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18 as 32-bit registers. So, we will set things up like the 68k which
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19 has different fp units: define separate register sets for the 1.0
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20 and 1.1 fp units. */
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21
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22 #define FIRST_PSEUDO_REGISTER 89 /* 32 general regs + 56 fp regs +
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23 + 1 shift reg */
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24
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25 /* 1 for registers that have pervasive standard uses
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26 and are not available for the register allocator.
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27
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28 On the HP-PA, these are:
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29 Reg 0 = 0 (hardware). However, 0 is used for condition code,
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30 so is not fixed.
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31 Reg 1 = ADDIL target/Temporary (hardware).
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32 Reg 2 = Return Pointer
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33 Reg 3 = Frame Pointer
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34 Reg 4 = Frame Pointer (>8k varying frame with HP compilers only)
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35 Reg 4-18 = Preserved Registers
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36 Reg 19 = Linkage Table Register in HPUX 8.0 shared library scheme.
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37 Reg 20-22 = Temporary Registers
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38 Reg 23-26 = Temporary/Parameter Registers
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39 Reg 27 = Global Data Pointer (hp)
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40 Reg 28 = Temporary/Return Value register
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41 Reg 29 = Temporary/Static Chain/Return Value register #2
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42 Reg 30 = stack pointer
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43 Reg 31 = Temporary/Millicode Return Pointer (hp)
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44
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45 Freg 0-3 = Status Registers -- Not known to the compiler.
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46 Freg 4-7 = Arguments/Return Value
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47 Freg 8-11 = Temporary Registers
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48 Freg 12-15 = Preserved Registers
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49
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50 Freg 16-31 = Reserved
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51
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52 On the Snake, fp regs are
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53
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54 Freg 0-3 = Status Registers -- Not known to the compiler.
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55 Freg 4L-7R = Arguments/Return Value
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56 Freg 8L-11R = Temporary Registers
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57 Freg 12L-21R = Preserved Registers
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58 Freg 22L-31R = Temporary Registers
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59
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60 */
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61
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62 #define FIXED_REGISTERS \
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63 {0, 0, 0, 0, 0, 0, 0, 0, \
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64 0, 0, 0, 0, 0, 0, 0, 0, \
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65 0, 0, 0, 0, 0, 0, 0, 0, \
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66 0, 0, 0, 1, 0, 0, 1, 0, \
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67 /* fp registers */ \
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68 0, 0, 0, 0, 0, 0, 0, 0, \
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69 0, 0, 0, 0, 0, 0, 0, 0, \
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70 0, 0, 0, 0, 0, 0, 0, 0, \
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71 0, 0, 0, 0, 0, 0, 0, 0, \
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72 0, 0, 0, 0, 0, 0, 0, 0, \
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73 0, 0, 0, 0, 0, 0, 0, 0, \
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74 0, 0, 0, 0, 0, 0, 0, 0, \
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75 0}
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76
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77 /* 1 for registers not available across function calls.
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78 These must include the FIXED_REGISTERS and also any
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79 registers that can be used without being saved.
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80 The latter must include the registers where values are returned
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81 and the register where structure-value addresses are passed.
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82 Aside from that, you can include as many other registers as you like. */
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83 #define CALL_USED_REGISTERS \
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84 {1, 1, 1, 0, 0, 0, 0, 0, \
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85 0, 0, 0, 0, 0, 0, 0, 0, \
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86 0, 0, 0, 1, 1, 1, 1, 1, \
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87 1, 1, 1, 1, 1, 1, 1, 1, \
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88 /* fp registers */ \
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89 1, 1, 1, 1, 1, 1, 1, 1, \
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90 1, 1, 1, 1, 1, 1, 1, 1, \
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91 0, 0, 0, 0, 0, 0, 0, 0, \
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92 0, 0, 0, 0, 0, 0, 0, 0, \
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93 0, 0, 0, 0, 1, 1, 1, 1, \
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94 1, 1, 1, 1, 1, 1, 1, 1, \
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95 1, 1, 1, 1, 1, 1, 1, 1, \
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96 1}
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97
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98 #define CONDITIONAL_REGISTER_USAGE \
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99 { \
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100 int i; \
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101 if (!TARGET_PA_11) \
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102 { \
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103 for (i = 56; i < 88; i++) \
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104 fixed_regs[i] = call_used_regs[i] = 1; \
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105 for (i = 33; i < 88; i += 2) \
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106 fixed_regs[i] = call_used_regs[i] = 1; \
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107 } \
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108 if (TARGET_DISABLE_FPREGS || TARGET_SOFT_FLOAT)\
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109 { \
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110 for (i = 32; i < 88; i++) \
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111 fixed_regs[i] = call_used_regs[i] = 1; \
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112 } \
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113 if (flag_pic) \
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114 fixed_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \
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115 }
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116
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117 /* Allocate the call used registers first. This should minimize
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118 the number of registers that need to be saved (as call used
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119 registers will generally not be allocated across a call).
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120
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121 Experimentation has shown slightly better results by allocating
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122 FP registers first. We allocate the caller-saved registers more
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123 or less in reverse order to their allocation as arguments.
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124
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125 FP registers are ordered so that all L registers are selected before
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126 R registers. This works around a false dependency interlock on the
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127 PA8000 when accessing the high and low parts of an FP register
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128 independently. */
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129
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130 #define REG_ALLOC_ORDER \
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131 { \
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132 /* caller-saved fp regs. */ \
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133 68, 70, 72, 74, 76, 78, 80, 82, \
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134 84, 86, 40, 42, 44, 46, 38, 36, \
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135 34, 32, \
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136 69, 71, 73, 75, 77, 79, 81, 83, \
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137 85, 87, 41, 43, 45, 47, 39, 37, \
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138 35, 33, \
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139 /* caller-saved general regs. */ \
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140 28, 19, 20, 21, 22, 31, 27, 29, \
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141 23, 24, 25, 26, 2, \
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142 /* callee-saved fp regs. */ \
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143 48, 50, 52, 54, 56, 58, 60, 62, \
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144 64, 66, \
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145 49, 51, 53, 55, 57, 59, 61, 63, \
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146 65, 67, \
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147 /* callee-saved general regs. */ \
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148 3, 4, 5, 6, 7, 8, 9, 10, \
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149 11, 12, 13, 14, 15, 16, 17, 18, \
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150 /* special registers. */ \
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151 1, 30, 0, 88}
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152
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153
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154 /* Return number of consecutive hard regs needed starting at reg REGNO
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155 to hold something of mode MODE.
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156 This is ordinarily the length in words of a value of mode MODE
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157 but can be less for certain modes in special long registers.
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158
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159 On the HP-PA, general registers are 32 bits wide. The floating
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160 point registers are 64 bits wide. Snake fp regs are treated as
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161 32 bits wide since the left and right parts are independently
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162 accessible. */
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163 #define HARD_REGNO_NREGS(REGNO, MODE) \
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164 (FP_REGNO_P (REGNO) \
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165 ? (!TARGET_PA_11 \
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166 ? COMPLEX_MODE_P (MODE) ? 2 : 1 \
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167 : (GET_MODE_SIZE (MODE) + 4 - 1) / 4) \
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168 : (GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
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169
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170 /* There are no instructions that use DImode in PA 1.0, so we only
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171 allow it in PA 1.1 and later. */
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172 #define VALID_FP_MODE_P(MODE) \
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173 ((MODE) == SFmode || (MODE) == DFmode \
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174 || (MODE) == SCmode || (MODE) == DCmode \
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175 || (MODE) == SImode || (TARGET_PA_11 && (MODE) == DImode))
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176
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177 /* Value is 1 if hard register REGNO can hold a value of machine-mode MODE.
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178
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179 On the HP-PA, the cpu registers can hold any mode that fits in 32 bits.
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180 For the 64-bit modes, we choose a set of non-overlapping general registers
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181 that includes the incoming arguments and the return value. We specify a
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182 set with no overlaps so that we don't have to specify that the destination
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183 register is an early clobber in patterns using this mode. Except for the
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184 return value, the starting registers are odd. For 128 and 256 bit modes,
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185 we similarly specify non-overlapping sets of cpu registers. However,
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186 there aren't any patterns defined for modes larger than 64 bits at the
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187 moment.
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188
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189 We limit the modes allowed in the floating point registers to the
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190 set of modes used in the machine definition. In addition, we allow
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191 the complex modes SCmode and DCmode. The real and imaginary parts
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192 of complex modes are allocated to separate registers. This might
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193 allow patterns to be defined in the future to operate on these values.
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194
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195 The PA 2.0 architecture specifies that quad-precision floating-point
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196 values should start on an even floating point register. Thus, we
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197 choose non-overlapping sets of registers starting on even register
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198 boundaries for large modes. However, there is currently no support
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199 in the machine definition for modes larger than 64 bits. TFmode is
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200 supported under HP-UX using libcalls. Since TFmode values are passed
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201 by reference, they never need to be loaded into the floating-point
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202 registers. */
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203 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
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204 ((REGNO) == 0 ? (MODE) == CCmode || (MODE) == CCFPmode \
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205 : !TARGET_PA_11 && FP_REGNO_P (REGNO) \
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206 ? (VALID_FP_MODE_P (MODE) \
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207 && (GET_MODE_SIZE (MODE) <= 8 \
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208 || (GET_MODE_SIZE (MODE) == 16 && ((REGNO) & 3) == 0))) \
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209 : FP_REGNO_P (REGNO) \
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210 ? (VALID_FP_MODE_P (MODE) \
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211 && (GET_MODE_SIZE (MODE) <= 4 \
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212 || (GET_MODE_SIZE (MODE) == 8 && ((REGNO) & 1) == 0) \
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213 || (GET_MODE_SIZE (MODE) == 16 && ((REGNO) & 3) == 0) \
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214 || (GET_MODE_SIZE (MODE) == 32 && ((REGNO) & 7) == 0))) \
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215 : (GET_MODE_SIZE (MODE) <= UNITS_PER_WORD \
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216 || (GET_MODE_SIZE (MODE) == 2 * UNITS_PER_WORD \
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217 && ((((REGNO) & 1) == 1 && (REGNO) <= 25) || (REGNO) == 28)) \
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218 || (GET_MODE_SIZE (MODE) == 4 * UNITS_PER_WORD \
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219 && ((REGNO) & 3) == 3 && (REGNO) <= 23) \
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220 || (GET_MODE_SIZE (MODE) == 8 * UNITS_PER_WORD \
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221 && ((REGNO) & 7) == 3 && (REGNO) <= 19)))
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222
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223 /* How to renumber registers for dbx and gdb.
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224
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225 Registers 0 - 31 remain unchanged.
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226
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227 Registers 32 - 87 are mapped to 72 - 127
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228
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229 Register 88 is mapped to 32. */
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230
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231 #define DBX_REGISTER_NUMBER(REGNO) \
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232 ((REGNO) <= 31 ? (REGNO) : \
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233 ((REGNO) <= 87 ? (REGNO) + 40 : 32))
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234
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235 /* We must not use the DBX register numbers for the DWARF 2 CFA column
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236 numbers because that maps to numbers beyond FIRST_PSEUDO_REGISTER.
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237 Instead use the identity mapping. */
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238 #define DWARF_FRAME_REGNUM(REG) REG
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239
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240 /* Define the classes of registers for register constraints in the
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241 machine description. Also define ranges of constants.
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242
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243 One of the classes must always be named ALL_REGS and include all hard regs.
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244 If there is more than one class, another class must be named NO_REGS
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245 and contain no registers.
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246
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247 The name GENERAL_REGS must be the name of a class (or an alias for
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248 another name such as ALL_REGS). This is the class of registers
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249 that is allowed by "g" or "r" in a register constraint.
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250 Also, registers outside this class are allocated only when
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251 instructions express preferences for them.
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252
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253 The classes must be numbered in nondecreasing order; that is,
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254 a larger-numbered class must never be contained completely
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255 in a smaller-numbered class.
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256
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257 For any two classes, it is very desirable that there be another
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258 class that represents their union. */
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259
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260 /* The HP-PA has four kinds of registers: general regs, 1.0 fp regs,
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261 1.1 fp regs, and the high 1.1 fp regs, to which the operands of
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262 fmpyadd and fmpysub are restricted. */
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263
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264 enum reg_class { NO_REGS, R1_REGS, GENERAL_REGS, FPUPPER_REGS, FP_REGS,
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265 GENERAL_OR_FP_REGS, SHIFT_REGS, ALL_REGS, LIM_REG_CLASSES};
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266
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267 #define N_REG_CLASSES (int) LIM_REG_CLASSES
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268
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269 /* Give names of register classes as strings for dump file. */
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270
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271 #define REG_CLASS_NAMES \
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272 {"NO_REGS", "R1_REGS", "GENERAL_REGS", "FPUPPER_REGS", "FP_REGS", \
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273 "GENERAL_OR_FP_REGS", "SHIFT_REGS", "ALL_REGS"}
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274
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275 /* Define which registers fit in which classes.
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276 This is an initializer for a vector of HARD_REG_SET
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277 of length N_REG_CLASSES. Register 0, the "condition code" register,
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278 is in no class. */
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279
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280 #define REG_CLASS_CONTENTS \
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281 {{0x00000000, 0x00000000, 0x00000000}, /* NO_REGS */ \
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282 {0x00000002, 0x00000000, 0x00000000}, /* R1_REGS */ \
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283 {0xfffffffe, 0x00000000, 0x00000000}, /* GENERAL_REGS */ \
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284 {0x00000000, 0xff000000, 0x00ffffff}, /* FPUPPER_REGS */ \
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285 {0x00000000, 0xffffffff, 0x00ffffff}, /* FP_REGS */ \
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286 {0xfffffffe, 0xffffffff, 0x00ffffff}, /* GENERAL_OR_FP_REGS */ \
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287 {0x00000000, 0x00000000, 0x01000000}, /* SHIFT_REGS */ \
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288 {0xfffffffe, 0xffffffff, 0x01ffffff}} /* ALL_REGS */
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289
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290 /* The following macro defines cover classes for Integrated Register
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291 Allocator. Cover classes is a set of non-intersected register
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292 classes covering all hard registers used for register allocation
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293 purpose. Any move between two registers of a cover class should be
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294 cheaper than load or store of the registers. The macro value is
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295 array of register classes with LIM_REG_CLASSES used as the end
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296 marker. */
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297
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298 #define IRA_COVER_CLASSES \
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299 { \
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300 GENERAL_REGS, FP_REGS, SHIFT_REGS, LIM_REG_CLASSES \
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301 }
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302
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303 /* Defines invalid mode changes. */
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304
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305 #define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS) \
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306 pa_cannot_change_mode_class (FROM, TO, CLASS)
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307
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308 /* Return the class number of the smallest class containing
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309 reg number REGNO. This could be a conditional expression
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310 or could index an array. */
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311
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312 #define REGNO_REG_CLASS(REGNO) \
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313 ((REGNO) == 0 ? NO_REGS \
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314 : (REGNO) == 1 ? R1_REGS \
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315 : (REGNO) < 32 ? GENERAL_REGS \
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316 : (REGNO) < 56 ? FP_REGS \
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317 : (REGNO) < 88 ? FPUPPER_REGS \
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318 : SHIFT_REGS)
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319
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320 /* Return the maximum number of consecutive registers
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321 needed to represent mode MODE in a register of class CLASS. */
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322 #define CLASS_MAX_NREGS(CLASS, MODE) \
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323 ((CLASS) == FP_REGS || (CLASS) == FPUPPER_REGS \
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324 ? (!TARGET_PA_11 \
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325 ? COMPLEX_MODE_P (MODE) ? 2 : 1 \
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326 : (GET_MODE_SIZE (MODE) + 4 - 1) / 4) \
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327 : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD))
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328
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329 /* 1 if N is a possible register number for function argument passing. */
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330
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331 #define FUNCTION_ARG_REGNO_P(N) \
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332 (((N) >= 23 && (N) <= 26) || (! TARGET_SOFT_FLOAT && (N) >= 32 && (N) <= 39))
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333
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334 /* How to refer to registers in assembler output.
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335 This sequence is indexed by compiler's hard-register-number (see above). */
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336
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337 #define REGISTER_NAMES \
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338 {"%r0", "%r1", "%r2", "%r3", "%r4", "%r5", "%r6", "%r7", \
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339 "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15", \
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340 "%r16", "%r17", "%r18", "%r19", "%r20", "%r21", "%r22", "%r23", \
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341 "%r24", "%r25", "%r26", "%r27", "%r28", "%r29", "%r30", "%r31", \
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342 "%fr4", "%fr4R", "%fr5", "%fr5R", "%fr6", "%fr6R", "%fr7", "%fr7R", \
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343 "%fr8", "%fr8R", "%fr9", "%fr9R", "%fr10", "%fr10R", "%fr11", "%fr11R", \
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344 "%fr12", "%fr12R", "%fr13", "%fr13R", "%fr14", "%fr14R", "%fr15", "%fr15R", \
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345 "%fr16", "%fr16R", "%fr17", "%fr17R", "%fr18", "%fr18R", "%fr19", "%fr19R", \
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346 "%fr20", "%fr20R", "%fr21", "%fr21R", "%fr22", "%fr22R", "%fr23", "%fr23R", \
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347 "%fr24", "%fr24R", "%fr25", "%fr25R", "%fr26", "%fr26R", "%fr27", "%fr27R", \
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348 "%fr28", "%fr28R", "%fr29", "%fr29R", "%fr30", "%fr30R", "%fr31", "%fr31R", \
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349 "SAR"}
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350
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351 #define ADDITIONAL_REGISTER_NAMES \
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352 {{"%fr4L",32}, {"%fr5L",34}, {"%fr6L",36}, {"%fr7L",38}, \
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353 {"%fr8L",40}, {"%fr9L",42}, {"%fr10L",44}, {"%fr11L",46}, \
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354 {"%fr12L",48}, {"%fr13L",50}, {"%fr14L",52}, {"%fr15L",54}, \
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355 {"%fr16L",56}, {"%fr17L",58}, {"%fr18L",60}, {"%fr19L",62}, \
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356 {"%fr20L",64}, {"%fr21L",66}, {"%fr22L",68}, {"%fr23L",70}, \
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357 {"%fr24L",72}, {"%fr25L",74}, {"%fr26L",76}, {"%fr27L",78}, \
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358 {"%fr28L",80}, {"%fr29L",82}, {"%fr30L",84}, {"%fr31R",86}, \
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359 {"%cr11",88}}
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360
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361 #define FP_SAVED_REG_LAST 66
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362 #define FP_SAVED_REG_FIRST 48
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363 #define FP_REG_STEP 2
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364 #define FP_REG_FIRST 32
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365 #define FP_REG_LAST 87
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