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comparison gcc/config/rs6000/603.md @ 0:a06113de4d67

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author kent <kent@cr.ie.u-ryukyu.ac.jp>
date Fri, 17 Jul 2009 14:47:48 +0900
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1 ;; Scheduling description for PowerPC 603 processor.
2 ;; Copyright (C) 2003, 2004, 2007 Free Software Foundation, Inc.
3 ;;
4 ;; This file is part of GCC.
5
6 ;; GCC is free software; you can redistribute it and/or modify it
7 ;; under the terms of the GNU General Public License as published
8 ;; by the Free Software Foundation; either version 3, or (at your
9 ;; option) any later version.
10
11 ;; GCC is distributed in the hope that it will be useful, but WITHOUT
12 ;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
13 ;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
14 ;; License for more details.
15
16 ;; You should have received a copy of the GNU General Public License
17 ;; along with GCC; see the file COPYING3. If not see
18 ;; <http://www.gnu.org/licenses/>.
19
20 (define_automaton "ppc603,ppc603fp")
21 (define_cpu_unit "iu_603" "ppc603")
22 (define_cpu_unit "fpu_603" "ppc603fp")
23 (define_cpu_unit "lsu_603,bpu_603,sru_603" "ppc603")
24
25 ;; PPC603/PPC603e 32-bit IU, LSU, FPU, BPU, SRU
26 ;; Max issue 3 insns/clock cycle (includes 1 branch)
27
28 ;; Branches go straight to the BPU. All other insns are handled
29 ;; by a dispatch unit which can issue a max of 2 insns per cycle.
30
31 ;; The PPC603e user's manual recommends that to reduce branch mispredictions,
32 ;; the insn that sets CR bits should be separated from the branch insn
33 ;; that evaluates them; separation by more than 9 insns ensures that the CR
34 ;; bits will be immediately available for execution.
35 ;; This could be artificially achieved by exaggerating the latency of
36 ;; compare insns but at the expense of a poorer schedule.
37
38 ;; CR insns get executed in the SRU. Not modelled.
39
40 (define_insn_reservation "ppc603-load" 2
41 (and (eq_attr "type" "load,load_ext,load_ux,load_u,load_l")
42 (eq_attr "cpu" "ppc603"))
43 "lsu_603")
44
45 (define_insn_reservation "ppc603-store" 2
46 (and (eq_attr "type" "store,store_ux,store_u,fpstore,fpstore_ux,fpstore_u")
47 (eq_attr "cpu" "ppc603"))
48 "lsu_603*2")
49
50 (define_insn_reservation "ppc603-fpload" 2
51 (and (eq_attr "type" "fpload,fpload_ux,fpload_u")
52 (eq_attr "cpu" "ppc603"))
53 "lsu_603")
54
55 (define_insn_reservation "ppc603-storec" 8
56 (and (eq_attr "type" "store_c")
57 (eq_attr "cpu" "ppc603"))
58 "lsu_603")
59
60 (define_insn_reservation "ppc603-integer" 1
61 (and (eq_attr "type" "integer,insert_word,insert_dword,shift,trap,\
62 var_shift_rotate,cntlz,exts")
63 (eq_attr "cpu" "ppc603"))
64 "iu_603")
65
66 (define_insn_reservation "ppc603-two" 1
67 (and (eq_attr "type" "two")
68 (eq_attr "cpu" "ppc603"))
69 "iu_603,iu_603")
70
71 (define_insn_reservation "ppc603-three" 1
72 (and (eq_attr "type" "three")
73 (eq_attr "cpu" "ppc603"))
74 "iu_603,iu_603,iu_603")
75
76 ; This takes 2 or 3 cycles
77 (define_insn_reservation "ppc603-imul" 3
78 (and (eq_attr "type" "imul,imul_compare")
79 (eq_attr "cpu" "ppc603"))
80 "iu_603*2")
81
82 (define_insn_reservation "ppc603-imul2" 2
83 (and (eq_attr "type" "imul2,imul3")
84 (eq_attr "cpu" "ppc603"))
85 "iu_603*2")
86
87 (define_insn_reservation "ppc603-idiv" 37
88 (and (eq_attr "type" "idiv")
89 (eq_attr "cpu" "ppc603"))
90 "iu_603*37")
91
92 (define_insn_reservation "ppc603-compare" 3
93 (and (eq_attr "type" "cmp,fast_compare,compare,delayed_compare,\
94 var_delayed_compare")
95 (eq_attr "cpu" "ppc603"))
96 "iu_603,nothing,bpu_603")
97
98 (define_insn_reservation "ppc603-fpcompare" 3
99 (and (eq_attr "type" "fpcompare")
100 (eq_attr "cpu" "ppc603"))
101 "(fpu_603+iu_603*2),bpu_603")
102
103 (define_insn_reservation "ppc603-fp" 3
104 (and (eq_attr "type" "fp")
105 (eq_attr "cpu" "ppc603"))
106 "fpu_603")
107
108 (define_insn_reservation "ppc603-dmul" 4
109 (and (eq_attr "type" "dmul")
110 (eq_attr "cpu" "ppc603"))
111 "fpu_603*2")
112
113 ; Divides are not pipelined
114 (define_insn_reservation "ppc603-sdiv" 18
115 (and (eq_attr "type" "sdiv")
116 (eq_attr "cpu" "ppc603"))
117 "fpu_603*18")
118
119 (define_insn_reservation "ppc603-ddiv" 33
120 (and (eq_attr "type" "ddiv")
121 (eq_attr "cpu" "ppc603"))
122 "fpu_603*33")
123
124 (define_insn_reservation "ppc603-crlogical" 2
125 (and (eq_attr "type" "cr_logical,delayed_cr,mfcr,mtcr")
126 (eq_attr "cpu" "ppc603"))
127 "sru_603")
128
129 (define_insn_reservation "ppc603-mtjmpr" 4
130 (and (eq_attr "type" "mtjmpr")
131 (eq_attr "cpu" "ppc603"))
132 "sru_603")
133
134 (define_insn_reservation "ppc603-mfjmpr" 2
135 (and (eq_attr "type" "mfjmpr,isync,sync")
136 (eq_attr "cpu" "ppc603"))
137 "sru_603")
138
139 (define_insn_reservation "ppc603-jmpreg" 1
140 (and (eq_attr "type" "jmpreg,branch")
141 (eq_attr "cpu" "ppc603"))
142 "bpu_603")
143