Mercurial > hg > CbC > CbC_gcc
comparison gcc/config/sparc/niagara2.md @ 0:a06113de4d67
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| author | kent <kent@cr.ie.u-ryukyu.ac.jp> |
|---|---|
| date | Fri, 17 Jul 2009 14:47:48 +0900 |
| parents | |
| children | 04ced10e8804 |
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| -1:000000000000 | 0:a06113de4d67 |
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| 1 ;; Scheduling description for Niagara-2. | |
| 2 ;; Copyright (C) 2007 Free Software Foundation, Inc. | |
| 3 ;; | |
| 4 ;; This file is part of GCC. | |
| 5 ;; | |
| 6 ;; GCC is free software; you can redistribute it and/or modify | |
| 7 ;; it under the terms of the GNU General Public License as published by | |
| 8 ;; the Free Software Foundation; either version 3, or (at your option) | |
| 9 ;; any later version. | |
| 10 ;; | |
| 11 ;; GCC is distributed in the hope that it will be useful, | |
| 12 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of | |
| 13 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
| 14 ;; GNU General Public License for more details. | |
| 15 ;; | |
| 16 ;; You should have received a copy of the GNU General Public License | |
| 17 ;; along with GCC; see the file COPYING3. If not see | |
| 18 ;; <http://www.gnu.org/licenses/>. | |
| 19 | |
| 20 ;; Niagara-2 is a single-issue processor. | |
| 21 | |
| 22 (define_automaton "niagara2_0") | |
| 23 | |
| 24 (define_cpu_unit "niag2_pipe" "niagara2_0") | |
| 25 | |
| 26 (define_insn_reservation "niag2_25cycle" 25 | |
| 27 (and (eq_attr "cpu" "niagara2") | |
| 28 (eq_attr "type" "flushw")) | |
| 29 "niag2_pipe*25") | |
| 30 | |
| 31 (define_insn_reservation "niag2_5cycle" 5 | |
| 32 (and (eq_attr "cpu" "niagara2") | |
| 33 (eq_attr "type" "multi,flushw,iflush,trap")) | |
| 34 "niag2_pipe*5") | |
| 35 | |
| 36 (define_insn_reservation "niag2_6cycle" 4 | |
| 37 (and (eq_attr "cpu" "niagara2") | |
| 38 (eq_attr "type" "savew")) | |
| 39 "niag2_pipe*4") | |
| 40 | |
| 41 /* Most basic operations are single-cycle. */ | |
| 42 (define_insn_reservation "niag2_ialu" 1 | |
| 43 (and (eq_attr "cpu" "niagara2") | |
| 44 (eq_attr "type" "ialu,shift,compare,cmove")) | |
| 45 "niag2_pipe") | |
| 46 | |
| 47 (define_insn_reservation "niag2_imul" 5 | |
| 48 (and (eq_attr "cpu" "niagara2") | |
| 49 (eq_attr "type" "imul")) | |
| 50 "niag2_pipe*5") | |
| 51 | |
| 52 (define_insn_reservation "niag2_idiv" 31 | |
| 53 (and (eq_attr "cpu" "niagara2") | |
| 54 (eq_attr "type" "idiv")) | |
| 55 "niag2_pipe*31") | |
| 56 | |
| 57 (define_insn_reservation "niag2_branch" 5 | |
| 58 (and (eq_attr "cpu" "niagara2") | |
| 59 (eq_attr "type" "call,sibcall,call_no_delay_slot,uncond_branch,branch")) | |
| 60 "niag2_pipe*5") | |
| 61 | |
| 62 (define_insn_reservation "niag2_3cycle_load" 3 | |
| 63 (and (eq_attr "cpu" "niagara2") | |
| 64 (eq_attr "type" "load,fpload")) | |
| 65 "niag2_pipe*3") | |
| 66 | |
| 67 (define_insn_reservation "niag2_1cycle_store" 1 | |
| 68 (and (eq_attr "cpu" "niagara2") | |
| 69 (eq_attr "type" "store,fpstore")) | |
| 70 "niag2_pipe") | |
| 71 | |
| 72 (define_insn_reservation "niag2_fp" 3 | |
| 73 (and (eq_attr "cpu" "niagara2") | |
| 74 (eq_attr "type" "fpmove,fpcmove,fpcrmove,fpcmp,fpmul")) | |
| 75 "niag2_pipe*3") | |
| 76 | |
| 77 (define_insn_reservation "niag2_fdivs" 19 | |
| 78 (and (eq_attr "cpu" "niagara2") | |
| 79 (eq_attr "type" "fpdivs")) | |
| 80 "niag2_pipe*19") | |
| 81 | |
| 82 (define_insn_reservation "niag2_fdivd" 33 | |
| 83 (and (eq_attr "cpu" "niagara2") | |
| 84 (eq_attr "type" "fpdivd")) | |
| 85 "niag2_pipe*33") | |
| 86 | |
| 87 (define_insn_reservation "niag2_vis" 6 | |
| 88 (and (eq_attr "cpu" "niagara2") | |
| 89 (eq_attr "type" "fga,fgm_pack,fgm_mul,fgm_cmp,fgm_pdist")) | |
| 90 "niag2_pipe*6") |