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comparison gcc/config/vax/vax.c @ 0:a06113de4d67

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first commit
author kent <kent@cr.ie.u-ryukyu.ac.jp>
date Fri, 17 Jul 2009 14:47:48 +0900
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children 58ad6c70ea60
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-1:000000000000 0:a06113de4d67
1 /* Subroutines for insn-output.c for VAX.
2 Copyright (C) 1987, 1994, 1995, 1997, 1998, 1999, 2000, 2001, 2002,
3 2004, 2005, 2006, 2007, 2008
4 Free Software Foundation, Inc.
5
6 This file is part of GCC.
7
8 GCC is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3, or (at your option)
11 any later version.
12
13 GCC is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
17
18 You should have received a copy of the GNU General Public License
19 along with GCC; see the file COPYING3. If not see
20 <http://www.gnu.org/licenses/>. */
21
22 #include "config.h"
23 #include "system.h"
24 #include "coretypes.h"
25 #include "tm.h"
26 #include "rtl.h"
27 #include "tree.h"
28 #include "regs.h"
29 #include "hard-reg-set.h"
30 #include "real.h"
31 #include "insn-config.h"
32 #include "conditions.h"
33 #include "function.h"
34 #include "output.h"
35 #include "insn-attr.h"
36 #include "recog.h"
37 #include "expr.h"
38 #include "optabs.h"
39 #include "flags.h"
40 #include "debug.h"
41 #include "toplev.h"
42 #include "tm_p.h"
43 #include "target.h"
44 #include "target-def.h"
45
46 static void vax_output_function_prologue (FILE *, HOST_WIDE_INT);
47 static void vax_file_start (void);
48 static void vax_init_libfuncs (void);
49 static void vax_output_mi_thunk (FILE *, tree, HOST_WIDE_INT,
50 HOST_WIDE_INT, tree);
51 static int vax_address_cost_1 (rtx);
52 static int vax_address_cost (rtx, bool);
53 static bool vax_rtx_costs (rtx, int, int, int *, bool);
54 static rtx vax_struct_value_rtx (tree, int);
55
56 /* Initialize the GCC target structure. */
57 #undef TARGET_ASM_ALIGNED_HI_OP
58 #define TARGET_ASM_ALIGNED_HI_OP "\t.word\t"
59
60 #undef TARGET_ASM_FUNCTION_PROLOGUE
61 #define TARGET_ASM_FUNCTION_PROLOGUE vax_output_function_prologue
62
63 #undef TARGET_ASM_FILE_START
64 #define TARGET_ASM_FILE_START vax_file_start
65 #undef TARGET_ASM_FILE_START_APP_OFF
66 #define TARGET_ASM_FILE_START_APP_OFF true
67
68 #undef TARGET_INIT_LIBFUNCS
69 #define TARGET_INIT_LIBFUNCS vax_init_libfuncs
70
71 #undef TARGET_ASM_OUTPUT_MI_THUNK
72 #define TARGET_ASM_OUTPUT_MI_THUNK vax_output_mi_thunk
73 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
74 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK default_can_output_mi_thunk_no_vcall
75
76 #undef TARGET_DEFAULT_TARGET_FLAGS
77 #define TARGET_DEFAULT_TARGET_FLAGS TARGET_DEFAULT
78
79 #undef TARGET_RTX_COSTS
80 #define TARGET_RTX_COSTS vax_rtx_costs
81 #undef TARGET_ADDRESS_COST
82 #define TARGET_ADDRESS_COST vax_address_cost
83
84 #undef TARGET_PROMOTE_PROTOTYPES
85 #define TARGET_PROMOTE_PROTOTYPES hook_bool_const_tree_true
86
87 #undef TARGET_STRUCT_VALUE_RTX
88 #define TARGET_STRUCT_VALUE_RTX vax_struct_value_rtx
89
90 struct gcc_target targetm = TARGET_INITIALIZER;
91
92 /* Set global variables as needed for the options enabled. */
93
94 void
95 override_options (void)
96 {
97 /* We're VAX floating point, not IEEE floating point. */
98 if (TARGET_G_FLOAT)
99 REAL_MODE_FORMAT (DFmode) = &vax_g_format;
100 }
101
102 /* Generate the assembly code for function entry. FILE is a stdio
103 stream to output the code to. SIZE is an int: how many units of
104 temporary storage to allocate.
105
106 Refer to the array `regs_ever_live' to determine which registers to
107 save; `regs_ever_live[I]' is nonzero if register number I is ever
108 used in the function. This function is responsible for knowing
109 which registers should not be saved even if used. */
110
111 static void
112 vax_output_function_prologue (FILE * file, HOST_WIDE_INT size)
113 {
114 int regno;
115 int mask = 0;
116
117 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
118 if (df_regs_ever_live_p (regno) && !call_used_regs[regno])
119 mask |= 1 << regno;
120
121 fprintf (file, "\t.word 0x%x\n", mask);
122
123 if (dwarf2out_do_frame ())
124 {
125 const char *label = dwarf2out_cfi_label ();
126 int offset = 0;
127
128 for (regno = FIRST_PSEUDO_REGISTER-1; regno >= 0; --regno)
129 if (df_regs_ever_live_p (regno) && !call_used_regs[regno])
130 dwarf2out_reg_save (label, regno, offset -= 4);
131
132 dwarf2out_reg_save (label, PC_REGNUM, offset -= 4);
133 dwarf2out_reg_save (label, FRAME_POINTER_REGNUM, offset -= 4);
134 dwarf2out_reg_save (label, ARG_POINTER_REGNUM, offset -= 4);
135 dwarf2out_def_cfa (label, FRAME_POINTER_REGNUM, -(offset - 4));
136 }
137
138 size -= STARTING_FRAME_OFFSET;
139 if (size >= 64)
140 asm_fprintf (file, "\tmovab %wd(%Rsp),%Rsp\n", -size);
141 else if (size)
142 asm_fprintf (file, "\tsubl2 $%wd,%Rsp\n", size);
143 }
144
145 /* When debugging with stabs, we want to output an extra dummy label
146 so that gas can distinguish between D_float and G_float prior to
147 processing the .stabs directive identifying type double. */
148 static void
149 vax_file_start (void)
150 {
151 default_file_start ();
152
153 if (write_symbols == DBX_DEBUG)
154 fprintf (asm_out_file, "___vax_%c_doubles:\n", ASM_DOUBLE_CHAR);
155 }
156
157 /* We can use the BSD C library routines for the libgcc calls that are
158 still generated, since that's what they boil down to anyways. When
159 ELF, avoid the user's namespace. */
160
161 static void
162 vax_init_libfuncs (void)
163 {
164 set_optab_libfunc (udiv_optab, SImode, TARGET_ELF ? "*__udiv" : "*udiv");
165 set_optab_libfunc (umod_optab, SImode, TARGET_ELF ? "*__urem" : "*urem");
166 }
167
168 /* This is like nonimmediate_operand with a restriction on the type of MEM. */
169
170 void
171 split_quadword_operands (rtx * operands, rtx * low, int n ATTRIBUTE_UNUSED)
172 {
173 int i;
174 /* Split operands. */
175
176 low[0] = low[1] = low[2] = 0;
177 for (i = 0; i < 3; i++)
178 {
179 if (low[i])
180 /* it's already been figured out */;
181 else if (MEM_P (operands[i])
182 && (GET_CODE (XEXP (operands[i], 0)) == POST_INC))
183 {
184 rtx addr = XEXP (operands[i], 0);
185 operands[i] = low[i] = gen_rtx_MEM (SImode, addr);
186 if (which_alternative == 0 && i == 0)
187 {
188 addr = XEXP (operands[i], 0);
189 operands[i+1] = low[i+1] = gen_rtx_MEM (SImode, addr);
190 }
191 }
192 else
193 {
194 low[i] = operand_subword (operands[i], 0, 0, DImode);
195 operands[i] = operand_subword (operands[i], 1, 0, DImode);
196 }
197 }
198 }
199
200 void
201 print_operand_address (FILE * file, rtx addr)
202 {
203 rtx reg1, breg, ireg;
204 rtx offset;
205
206 retry:
207 switch (GET_CODE (addr))
208 {
209 case MEM:
210 fprintf (file, "*");
211 addr = XEXP (addr, 0);
212 goto retry;
213
214 case REG:
215 fprintf (file, "(%s)", reg_names[REGNO (addr)]);
216 break;
217
218 case PRE_DEC:
219 fprintf (file, "-(%s)", reg_names[REGNO (XEXP (addr, 0))]);
220 break;
221
222 case POST_INC:
223 fprintf (file, "(%s)+", reg_names[REGNO (XEXP (addr, 0))]);
224 break;
225
226 case PLUS:
227 /* There can be either two or three things added here. One must be a
228 REG. One can be either a REG or a MULT of a REG and an appropriate
229 constant, and the third can only be a constant or a MEM.
230
231 We get these two or three things and put the constant or MEM in
232 OFFSET, the MULT or REG in IREG, and the REG in BREG. If we have
233 a register and can't tell yet if it is a base or index register,
234 put it into REG1. */
235
236 reg1 = 0; ireg = 0; breg = 0; offset = 0;
237
238 if (CONSTANT_ADDRESS_P (XEXP (addr, 0))
239 || MEM_P (XEXP (addr, 0)))
240 {
241 offset = XEXP (addr, 0);
242 addr = XEXP (addr, 1);
243 }
244 else if (CONSTANT_ADDRESS_P (XEXP (addr, 1))
245 || MEM_P (XEXP (addr, 1)))
246 {
247 offset = XEXP (addr, 1);
248 addr = XEXP (addr, 0);
249 }
250 else if (GET_CODE (XEXP (addr, 1)) == MULT)
251 {
252 ireg = XEXP (addr, 1);
253 addr = XEXP (addr, 0);
254 }
255 else if (GET_CODE (XEXP (addr, 0)) == MULT)
256 {
257 ireg = XEXP (addr, 0);
258 addr = XEXP (addr, 1);
259 }
260 else if (REG_P (XEXP (addr, 1)))
261 {
262 reg1 = XEXP (addr, 1);
263 addr = XEXP (addr, 0);
264 }
265 else if (REG_P (XEXP (addr, 0)))
266 {
267 reg1 = XEXP (addr, 0);
268 addr = XEXP (addr, 1);
269 }
270 else
271 gcc_unreachable ();
272
273 if (REG_P (addr))
274 {
275 if (reg1)
276 ireg = addr;
277 else
278 reg1 = addr;
279 }
280 else if (GET_CODE (addr) == MULT)
281 ireg = addr;
282 else
283 {
284 gcc_assert (GET_CODE (addr) == PLUS);
285 if (CONSTANT_ADDRESS_P (XEXP (addr, 0))
286 || MEM_P (XEXP (addr, 0)))
287 {
288 if (offset)
289 {
290 if (CONST_INT_P (offset))
291 offset = plus_constant (XEXP (addr, 0), INTVAL (offset));
292 else
293 {
294 gcc_assert (CONST_INT_P (XEXP (addr, 0)));
295 offset = plus_constant (offset, INTVAL (XEXP (addr, 0)));
296 }
297 }
298 offset = XEXP (addr, 0);
299 }
300 else if (REG_P (XEXP (addr, 0)))
301 {
302 if (reg1)
303 ireg = reg1, breg = XEXP (addr, 0), reg1 = 0;
304 else
305 reg1 = XEXP (addr, 0);
306 }
307 else
308 {
309 gcc_assert (GET_CODE (XEXP (addr, 0)) == MULT);
310 gcc_assert (!ireg);
311 ireg = XEXP (addr, 0);
312 }
313
314 if (CONSTANT_ADDRESS_P (XEXP (addr, 1))
315 || MEM_P (XEXP (addr, 1)))
316 {
317 if (offset)
318 {
319 if (CONST_INT_P (offset))
320 offset = plus_constant (XEXP (addr, 1), INTVAL (offset));
321 else
322 {
323 gcc_assert (CONST_INT_P (XEXP (addr, 1)));
324 offset = plus_constant (offset, INTVAL (XEXP (addr, 1)));
325 }
326 }
327 offset = XEXP (addr, 1);
328 }
329 else if (REG_P (XEXP (addr, 1)))
330 {
331 if (reg1)
332 ireg = reg1, breg = XEXP (addr, 1), reg1 = 0;
333 else
334 reg1 = XEXP (addr, 1);
335 }
336 else
337 {
338 gcc_assert (GET_CODE (XEXP (addr, 1)) == MULT);
339 gcc_assert (!ireg);
340 ireg = XEXP (addr, 1);
341 }
342 }
343
344 /* If REG1 is nonzero, figure out if it is a base or index register. */
345 if (reg1)
346 {
347 if (breg != 0 || (offset && MEM_P (offset)))
348 {
349 gcc_assert (!ireg);
350 ireg = reg1;
351 }
352 else
353 breg = reg1;
354 }
355
356 if (offset != 0)
357 output_address (offset);
358
359 if (breg != 0)
360 fprintf (file, "(%s)", reg_names[REGNO (breg)]);
361
362 if (ireg != 0)
363 {
364 if (GET_CODE (ireg) == MULT)
365 ireg = XEXP (ireg, 0);
366 gcc_assert (REG_P (ireg));
367 fprintf (file, "[%s]", reg_names[REGNO (ireg)]);
368 }
369 break;
370
371 default:
372 output_addr_const (file, addr);
373 }
374 }
375
376 const char *
377 rev_cond_name (rtx op)
378 {
379 switch (GET_CODE (op))
380 {
381 case EQ:
382 return "neq";
383 case NE:
384 return "eql";
385 case LT:
386 return "geq";
387 case LE:
388 return "gtr";
389 case GT:
390 return "leq";
391 case GE:
392 return "lss";
393 case LTU:
394 return "gequ";
395 case LEU:
396 return "gtru";
397 case GTU:
398 return "lequ";
399 case GEU:
400 return "lssu";
401
402 default:
403 gcc_unreachable ();
404 }
405 }
406
407 int
408 vax_float_literal(rtx c)
409 {
410 enum machine_mode mode;
411 REAL_VALUE_TYPE r, s;
412 int i;
413
414 if (GET_CODE (c) != CONST_DOUBLE)
415 return 0;
416
417 mode = GET_MODE (c);
418
419 if (c == const_tiny_rtx[(int) mode][0]
420 || c == const_tiny_rtx[(int) mode][1]
421 || c == const_tiny_rtx[(int) mode][2])
422 return 1;
423
424 REAL_VALUE_FROM_CONST_DOUBLE (r, c);
425
426 for (i = 0; i < 7; i++)
427 {
428 int x = 1 << i;
429 bool ok;
430 REAL_VALUE_FROM_INT (s, x, 0, mode);
431
432 if (REAL_VALUES_EQUAL (r, s))
433 return 1;
434 ok = exact_real_inverse (mode, &s);
435 gcc_assert (ok);
436 if (REAL_VALUES_EQUAL (r, s))
437 return 1;
438 }
439 return 0;
440 }
441
442
443 /* Return the cost in cycles of a memory address, relative to register
444 indirect.
445
446 Each of the following adds the indicated number of cycles:
447
448 1 - symbolic address
449 1 - pre-decrement
450 1 - indexing and/or offset(register)
451 2 - indirect */
452
453
454 static int
455 vax_address_cost_1 (rtx addr)
456 {
457 int reg = 0, indexed = 0, indir = 0, offset = 0, predec = 0;
458 rtx plus_op0 = 0, plus_op1 = 0;
459 restart:
460 switch (GET_CODE (addr))
461 {
462 case PRE_DEC:
463 predec = 1;
464 case REG:
465 case SUBREG:
466 case POST_INC:
467 reg = 1;
468 break;
469 case MULT:
470 indexed = 1; /* 2 on VAX 2 */
471 break;
472 case CONST_INT:
473 /* byte offsets cost nothing (on a VAX 2, they cost 1 cycle) */
474 if (offset == 0)
475 offset = (unsigned HOST_WIDE_INT)(INTVAL(addr)+128) > 256;
476 break;
477 case CONST:
478 case SYMBOL_REF:
479 offset = 1; /* 2 on VAX 2 */
480 break;
481 case LABEL_REF: /* this is probably a byte offset from the pc */
482 if (offset == 0)
483 offset = 1;
484 break;
485 case PLUS:
486 if (plus_op0)
487 plus_op1 = XEXP (addr, 0);
488 else
489 plus_op0 = XEXP (addr, 0);
490 addr = XEXP (addr, 1);
491 goto restart;
492 case MEM:
493 indir = 2; /* 3 on VAX 2 */
494 addr = XEXP (addr, 0);
495 goto restart;
496 default:
497 break;
498 }
499
500 /* Up to 3 things can be added in an address. They are stored in
501 plus_op0, plus_op1, and addr. */
502
503 if (plus_op0)
504 {
505 addr = plus_op0;
506 plus_op0 = 0;
507 goto restart;
508 }
509 if (plus_op1)
510 {
511 addr = plus_op1;
512 plus_op1 = 0;
513 goto restart;
514 }
515 /* Indexing and register+offset can both be used (except on a VAX 2)
516 without increasing execution time over either one alone. */
517 if (reg && indexed && offset)
518 return reg + indir + offset + predec;
519 return reg + indexed + indir + offset + predec;
520 }
521
522 static int
523 vax_address_cost (rtx x, bool speed ATTRIBUTE_UNUSED)
524 {
525 return (1 + (REG_P (x) ? 0 : vax_address_cost_1 (x)));
526 }
527
528 /* Cost of an expression on a VAX. This version has costs tuned for the
529 CVAX chip (found in the VAX 3 series) with comments for variations on
530 other models.
531
532 FIXME: The costs need review, particularly for TRUNCATE, FLOAT_EXTEND
533 and FLOAT_TRUNCATE. We need a -mcpu option to allow provision of
534 costs on a per cpu basis. */
535
536 static bool
537 vax_rtx_costs (rtx x, int code, int outer_code, int *total,
538 bool speed ATTRIBUTE_UNUSED)
539 {
540 enum machine_mode mode = GET_MODE (x);
541 int i = 0; /* may be modified in switch */
542 const char *fmt = GET_RTX_FORMAT (code); /* may be modified in switch */
543
544 switch (code)
545 {
546 /* On a VAX, constants from 0..63 are cheap because they can use the
547 1 byte literal constant format. Compare to -1 should be made cheap
548 so that decrement-and-branch insns can be formed more easily (if
549 the value -1 is copied to a register some decrement-and-branch
550 patterns will not match). */
551 case CONST_INT:
552 if (INTVAL (x) == 0)
553 return true;
554 if (outer_code == AND)
555 {
556 *total = ((unsigned HOST_WIDE_INT) ~INTVAL (x) <= 077) ? 1 : 2;
557 return true;
558 }
559 if ((unsigned HOST_WIDE_INT) INTVAL (x) <= 077
560 || (outer_code == COMPARE
561 && INTVAL (x) == -1)
562 || ((outer_code == PLUS || outer_code == MINUS)
563 && (unsigned HOST_WIDE_INT) -INTVAL (x) <= 077))
564 {
565 *total = 1;
566 return true;
567 }
568 /* FALLTHRU */
569
570 case CONST:
571 case LABEL_REF:
572 case SYMBOL_REF:
573 *total = 3;
574 return true;
575
576 case CONST_DOUBLE:
577 if (GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT)
578 *total = vax_float_literal (x) ? 5 : 8;
579 else
580 *total = ((CONST_DOUBLE_HIGH (x) == 0
581 && (unsigned HOST_WIDE_INT) CONST_DOUBLE_LOW (x) < 64)
582 || (outer_code == PLUS
583 && CONST_DOUBLE_HIGH (x) == -1
584 && (unsigned HOST_WIDE_INT)-CONST_DOUBLE_LOW (x) < 64))
585 ? 2 : 5;
586 return true;
587
588 case POST_INC:
589 *total = 2;
590 return true; /* Implies register operand. */
591
592 case PRE_DEC:
593 *total = 3;
594 return true; /* Implies register operand. */
595
596 case MULT:
597 switch (mode)
598 {
599 case DFmode:
600 *total = 16; /* 4 on VAX 9000 */
601 break;
602 case SFmode:
603 *total = 9; /* 4 on VAX 9000, 12 on VAX 2 */
604 break;
605 case DImode:
606 *total = 16; /* 6 on VAX 9000, 28 on VAX 2 */
607 break;
608 case SImode:
609 case HImode:
610 case QImode:
611 *total = 10; /* 3-4 on VAX 9000, 20-28 on VAX 2 */
612 break;
613 default:
614 *total = MAX_COST; /* Mode is not supported. */
615 return true;
616 }
617 break;
618
619 case UDIV:
620 if (mode != SImode)
621 {
622 *total = MAX_COST; /* Mode is not supported. */
623 return true;
624 }
625 *total = 17;
626 break;
627
628 case DIV:
629 if (mode == DImode)
630 *total = 30; /* Highly variable. */
631 else if (mode == DFmode)
632 /* divide takes 28 cycles if the result is not zero, 13 otherwise */
633 *total = 24;
634 else
635 *total = 11; /* 25 on VAX 2 */
636 break;
637
638 case MOD:
639 *total = 23;
640 break;
641
642 case UMOD:
643 if (mode != SImode)
644 {
645 *total = MAX_COST; /* Mode is not supported. */
646 return true;
647 }
648 *total = 29;
649 break;
650
651 case FLOAT:
652 *total = (6 /* 4 on VAX 9000 */
653 + (mode == DFmode) + (GET_MODE (XEXP (x, 0)) != SImode));
654 break;
655
656 case FIX:
657 *total = 7; /* 17 on VAX 2 */
658 break;
659
660 case ASHIFT:
661 case LSHIFTRT:
662 case ASHIFTRT:
663 if (mode == DImode)
664 *total = 12;
665 else
666 *total = 10; /* 6 on VAX 9000 */
667 break;
668
669 case ROTATE:
670 case ROTATERT:
671 *total = 6; /* 5 on VAX 2, 4 on VAX 9000 */
672 if (CONST_INT_P (XEXP (x, 1)))
673 fmt = "e"; /* all constant rotate counts are short */
674 break;
675
676 case PLUS:
677 case MINUS:
678 *total = (mode == DFmode) ? 13 : 8; /* 6/8 on VAX 9000, 16/15 on VAX 2 */
679 /* Small integer operands can use subl2 and addl2. */
680 if ((CONST_INT_P (XEXP (x, 1)))
681 && (unsigned HOST_WIDE_INT)(INTVAL (XEXP (x, 1)) + 63) < 127)
682 fmt = "e";
683 break;
684
685 case IOR:
686 case XOR:
687 *total = 3;
688 break;
689
690 case AND:
691 /* AND is special because the first operand is complemented. */
692 *total = 3;
693 if (CONST_INT_P (XEXP (x, 0)))
694 {
695 if ((unsigned HOST_WIDE_INT)~INTVAL (XEXP (x, 0)) > 63)
696 *total = 4;
697 fmt = "e";
698 i = 1;
699 }
700 break;
701
702 case NEG:
703 if (mode == DFmode)
704 *total = 9;
705 else if (mode == SFmode)
706 *total = 6;
707 else if (mode == DImode)
708 *total = 4;
709 else
710 *total = 2;
711 break;
712
713 case NOT:
714 *total = 2;
715 break;
716
717 case ZERO_EXTRACT:
718 case SIGN_EXTRACT:
719 *total = 15;
720 break;
721
722 case MEM:
723 if (mode == DImode || mode == DFmode)
724 *total = 5; /* 7 on VAX 2 */
725 else
726 *total = 3; /* 4 on VAX 2 */
727 x = XEXP (x, 0);
728 if (!REG_P (x) && GET_CODE (x) != POST_INC)
729 *total += vax_address_cost_1 (x);
730 return true;
731
732 case FLOAT_EXTEND:
733 case FLOAT_TRUNCATE:
734 case TRUNCATE:
735 *total = 3; /* FIXME: Costs need to be checked */
736 break;
737
738 default:
739 return false;
740 }
741
742 /* Now look inside the expression. Operands which are not registers or
743 short constants add to the cost.
744
745 FMT and I may have been adjusted in the switch above for instructions
746 which require special handling. */
747
748 while (*fmt++ == 'e')
749 {
750 rtx op = XEXP (x, i);
751
752 i += 1;
753 code = GET_CODE (op);
754
755 /* A NOT is likely to be found as the first operand of an AND
756 (in which case the relevant cost is of the operand inside
757 the not) and not likely to be found anywhere else. */
758 if (code == NOT)
759 op = XEXP (op, 0), code = GET_CODE (op);
760
761 switch (code)
762 {
763 case CONST_INT:
764 if ((unsigned HOST_WIDE_INT)INTVAL (op) > 63
765 && GET_MODE (x) != QImode)
766 *total += 1; /* 2 on VAX 2 */
767 break;
768 case CONST:
769 case LABEL_REF:
770 case SYMBOL_REF:
771 *total += 1; /* 2 on VAX 2 */
772 break;
773 case CONST_DOUBLE:
774 if (GET_MODE_CLASS (GET_MODE (op)) == MODE_FLOAT)
775 {
776 /* Registers are faster than floating point constants -- even
777 those constants which can be encoded in a single byte. */
778 if (vax_float_literal (op))
779 *total += 1;
780 else
781 *total += (GET_MODE (x) == DFmode) ? 3 : 2;
782 }
783 else
784 {
785 if (CONST_DOUBLE_HIGH (op) != 0
786 || (unsigned)CONST_DOUBLE_LOW (op) > 63)
787 *total += 2;
788 }
789 break;
790 case MEM:
791 *total += 1; /* 2 on VAX 2 */
792 if (!REG_P (XEXP (op, 0)))
793 *total += vax_address_cost_1 (XEXP (op, 0));
794 break;
795 case REG:
796 case SUBREG:
797 break;
798 default:
799 *total += 1;
800 break;
801 }
802 }
803 return true;
804 }
805
806 /* Output code to add DELTA to the first argument, and then jump to FUNCTION.
807 Used for C++ multiple inheritance.
808 .mask ^m<r2,r3,r4,r5,r6,r7,r8,r9,r10,r11> #conservative entry mask
809 addl2 $DELTA, 4(ap) #adjust first argument
810 jmp FUNCTION+2 #jump beyond FUNCTION's entry mask
811 */
812
813 static void
814 vax_output_mi_thunk (FILE * file,
815 tree thunk ATTRIBUTE_UNUSED,
816 HOST_WIDE_INT delta,
817 HOST_WIDE_INT vcall_offset ATTRIBUTE_UNUSED,
818 tree function)
819 {
820 fprintf (file, "\t.word 0x0ffc\n\taddl2 $" HOST_WIDE_INT_PRINT_DEC, delta);
821 asm_fprintf (file, ",4(%Rap)\n");
822 fprintf (file, "\tjmp ");
823 assemble_name (file, XSTR (XEXP (DECL_RTL (function), 0), 0));
824 fprintf (file, "+2\n");
825 }
826
827 static rtx
828 vax_struct_value_rtx (tree fntype ATTRIBUTE_UNUSED,
829 int incoming ATTRIBUTE_UNUSED)
830 {
831 return gen_rtx_REG (Pmode, VAX_STRUCT_VALUE_REGNUM);
832 }
833
834 /* Worker function for NOTICE_UPDATE_CC. */
835
836 void
837 vax_notice_update_cc (rtx exp, rtx insn ATTRIBUTE_UNUSED)
838 {
839 if (GET_CODE (exp) == SET)
840 {
841 if (GET_CODE (SET_SRC (exp)) == CALL)
842 CC_STATUS_INIT;
843 else if (GET_CODE (SET_DEST (exp)) != ZERO_EXTRACT
844 && GET_CODE (SET_DEST (exp)) != PC)
845 {
846 cc_status.flags = 0;
847 /* The integer operations below don't set carry or
848 set it in an incompatible way. That's ok though
849 as the Z bit is all we need when doing unsigned
850 comparisons on the result of these insns (since
851 they're always with 0). Set CC_NO_OVERFLOW to
852 generate the correct unsigned branches. */
853 switch (GET_CODE (SET_SRC (exp)))
854 {
855 case NEG:
856 if (GET_MODE_CLASS (GET_MODE (exp)) == MODE_FLOAT)
857 break;
858 case AND:
859 case IOR:
860 case XOR:
861 case NOT:
862 case MEM:
863 case REG:
864 cc_status.flags = CC_NO_OVERFLOW;
865 break;
866 default:
867 break;
868 }
869 cc_status.value1 = SET_DEST (exp);
870 cc_status.value2 = SET_SRC (exp);
871 }
872 }
873 else if (GET_CODE (exp) == PARALLEL
874 && GET_CODE (XVECEXP (exp, 0, 0)) == SET)
875 {
876 if (GET_CODE (SET_SRC (XVECEXP (exp, 0, 0))) == CALL)
877 CC_STATUS_INIT;
878 else if (GET_CODE (SET_DEST (XVECEXP (exp, 0, 0))) != PC)
879 {
880 cc_status.flags = 0;
881 cc_status.value1 = SET_DEST (XVECEXP (exp, 0, 0));
882 cc_status.value2 = SET_SRC (XVECEXP (exp, 0, 0));
883 }
884 else
885 /* PARALLELs whose first element sets the PC are aob,
886 sob insns. They do change the cc's. */
887 CC_STATUS_INIT;
888 }
889 else
890 CC_STATUS_INIT;
891 if (cc_status.value1 && REG_P (cc_status.value1)
892 && cc_status.value2
893 && reg_overlap_mentioned_p (cc_status.value1, cc_status.value2))
894 cc_status.value2 = 0;
895 if (cc_status.value1 && MEM_P (cc_status.value1)
896 && cc_status.value2
897 && MEM_P (cc_status.value2))
898 cc_status.value2 = 0;
899 /* Actual condition, one line up, should be that value2's address
900 depends on value1, but that is too much of a pain. */
901 }
902
903 /* Output integer move instructions. */
904
905 const char *
906 vax_output_int_move (rtx insn ATTRIBUTE_UNUSED, rtx *operands,
907 enum machine_mode mode)
908 {
909 switch (mode)
910 {
911 case SImode:
912 if (GET_CODE (operands[1]) == SYMBOL_REF || GET_CODE (operands[1]) == CONST)
913 {
914 if (push_operand (operands[0], SImode))
915 return "pushab %a1";
916 return "movab %a1,%0";
917 }
918 if (operands[1] == const0_rtx)
919 return "clrl %0";
920 if (CONST_INT_P (operands[1])
921 && (unsigned) INTVAL (operands[1]) >= 64)
922 {
923 int i = INTVAL (operands[1]);
924 if ((unsigned)(~i) < 64)
925 return "mcoml %N1,%0";
926 if ((unsigned)i < 0x100)
927 return "movzbl %1,%0";
928 if (i >= -0x80 && i < 0)
929 return "cvtbl %1,%0";
930 if ((unsigned)i < 0x10000)
931 return "movzwl %1,%0";
932 if (i >= -0x8000 && i < 0)
933 return "cvtwl %1,%0";
934 }
935 if (push_operand (operands[0], SImode))
936 return "pushl %1";
937 return "movl %1,%0";
938
939 case HImode:
940 if (CONST_INT_P (operands[1]))
941 {
942 int i = INTVAL (operands[1]);
943 if (i == 0)
944 return "clrw %0";
945 else if ((unsigned int)i < 64)
946 return "movw %1,%0";
947 else if ((unsigned int)~i < 64)
948 return "mcomw %H1,%0";
949 else if ((unsigned int)i < 256)
950 return "movzbw %1,%0";
951 }
952 return "movw %1,%0";
953
954 case QImode:
955 if (CONST_INT_P (operands[1]))
956 {
957 int i = INTVAL (operands[1]);
958 if (i == 0)
959 return "clrb %0";
960 else if ((unsigned int)~i < 64)
961 return "mcomb %B1,%0";
962 }
963 return "movb %1,%0";
964
965 default:
966 gcc_unreachable ();
967 }
968 }
969
970 /* Output integer add instructions.
971
972 The space-time-opcode tradeoffs for addition vary by model of VAX.
973
974 On a VAX 3 "movab (r1)[r2],r3" is faster than "addl3 r1,r2,r3",
975 but it not faster on other models.
976
977 "movab #(r1),r2" is usually shorter than "addl3 #,r1,r2", and is
978 faster on a VAX 3, but some VAXen (e.g. VAX 9000) will stall if
979 a register is used in an address too soon after it is set.
980 Compromise by using movab only when it is shorter than the add
981 or the base register in the address is one of sp, ap, and fp,
982 which are not modified very often. */
983
984 const char *
985 vax_output_int_add (rtx insn ATTRIBUTE_UNUSED, rtx *operands,
986 enum machine_mode mode)
987 {
988 switch (mode)
989 {
990 case SImode:
991 if (rtx_equal_p (operands[0], operands[1]))
992 {
993 if (operands[2] == const1_rtx)
994 return "incl %0";
995 if (operands[2] == constm1_rtx)
996 return "decl %0";
997 if (CONST_INT_P (operands[2])
998 && (unsigned) (- INTVAL (operands[2])) < 64)
999 return "subl2 $%n2,%0";
1000 if (CONST_INT_P (operands[2])
1001 && (unsigned) INTVAL (operands[2]) >= 64
1002 && REG_P (operands[1])
1003 && ((INTVAL (operands[2]) < 32767 && INTVAL (operands[2]) > -32768)
1004 || REGNO (operands[1]) > 11))
1005 return "movab %c2(%1),%0";
1006 return "addl2 %2,%0";
1007 }
1008
1009 if (rtx_equal_p (operands[0], operands[2]))
1010 return "addl2 %1,%0";
1011
1012 if (CONST_INT_P (operands[2])
1013 && INTVAL (operands[2]) < 32767
1014 && INTVAL (operands[2]) > -32768
1015 && REG_P (operands[1])
1016 && push_operand (operands[0], SImode))
1017 return "pushab %c2(%1)";
1018
1019 if (CONST_INT_P (operands[2])
1020 && (unsigned) (- INTVAL (operands[2])) < 64)
1021 return "subl3 $%n2,%1,%0";
1022
1023 if (CONST_INT_P (operands[2])
1024 && (unsigned) INTVAL (operands[2]) >= 64
1025 && REG_P (operands[1])
1026 && ((INTVAL (operands[2]) < 32767 && INTVAL (operands[2]) > -32768)
1027 || REGNO (operands[1]) > 11))
1028 return "movab %c2(%1),%0";
1029
1030 /* Add this if using gcc on a VAX 3xxx:
1031 if (REG_P (operands[1]) && REG_P (operands[2]))
1032 return "movab (%1)[%2],%0";
1033 */
1034 return "addl3 %1,%2,%0";
1035
1036 case HImode:
1037 if (rtx_equal_p (operands[0], operands[1]))
1038 {
1039 if (operands[2] == const1_rtx)
1040 return "incw %0";
1041 if (operands[2] == constm1_rtx)
1042 return "decw %0";
1043 if (CONST_INT_P (operands[2])
1044 && (unsigned) (- INTVAL (operands[2])) < 64)
1045 return "subw2 $%n2,%0";
1046 return "addw2 %2,%0";
1047 }
1048 if (rtx_equal_p (operands[0], operands[2]))
1049 return "addw2 %1,%0";
1050 if (CONST_INT_P (operands[2])
1051 && (unsigned) (- INTVAL (operands[2])) < 64)
1052 return "subw3 $%n2,%1,%0";
1053 return "addw3 %1,%2,%0";
1054
1055 case QImode:
1056 if (rtx_equal_p (operands[0], operands[1]))
1057 {
1058 if (operands[2] == const1_rtx)
1059 return "incb %0";
1060 if (operands[2] == constm1_rtx)
1061 return "decb %0";
1062 if (CONST_INT_P (operands[2])
1063 && (unsigned) (- INTVAL (operands[2])) < 64)
1064 return "subb2 $%n2,%0";
1065 return "addb2 %2,%0";
1066 }
1067 if (rtx_equal_p (operands[0], operands[2]))
1068 return "addb2 %1,%0";
1069 if (CONST_INT_P (operands[2])
1070 && (unsigned) (- INTVAL (operands[2])) < 64)
1071 return "subb3 $%n2,%1,%0";
1072 return "addb3 %1,%2,%0";
1073
1074 default:
1075 gcc_unreachable ();
1076 }
1077 }
1078
1079 /* Output a conditional branch. */
1080 const char *
1081 vax_output_conditional_branch (enum rtx_code code)
1082 {
1083 switch (code)
1084 {
1085 case EQ: return "jeql %l0";
1086 case NE: return "jneq %l0";
1087 case GT: return "jgtr %l0";
1088 case LT: return "jlss %l0";
1089 case GTU: return "jgtru %l0";
1090 case LTU: return "jlssu %l0";
1091 case GE: return "jgeq %l0";
1092 case LE: return "jleq %l0";
1093 case GEU: return "jgequ %l0";
1094 case LEU: return "jlequ %l0";
1095 default:
1096 gcc_unreachable ();
1097 }
1098 }
1099
1100 /* 1 if X is an rtx for a constant that is a valid address. */
1101
1102 int
1103 legitimate_constant_address_p (rtx x)
1104 {
1105 return (GET_CODE (x) == LABEL_REF || GET_CODE (x) == SYMBOL_REF
1106 || CONST_INT_P (x) || GET_CODE (x) == CONST
1107 || GET_CODE (x) == HIGH);
1108 }
1109
1110 /* Nonzero if the constant value X is a legitimate general operand.
1111 It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE. */
1112
1113 int
1114 legitimate_constant_p (rtx x ATTRIBUTE_UNUSED)
1115 {
1116 return 1;
1117 }
1118
1119 /* The other macros defined here are used only in legitimate_address_p (). */
1120
1121 /* Nonzero if X is a hard reg that can be used as an index
1122 or, if not strict, if it is a pseudo reg. */
1123 #define INDEX_REGISTER_P(X, STRICT) \
1124 (REG_P (X) && (!(STRICT) || REGNO_OK_FOR_INDEX_P (REGNO (X))))
1125
1126 /* Nonzero if X is a hard reg that can be used as a base reg
1127 or, if not strict, if it is a pseudo reg. */
1128 #define BASE_REGISTER_P(X, STRICT) \
1129 (REG_P (X) && (!(STRICT) || REGNO_OK_FOR_BASE_P (REGNO (X))))
1130
1131 #ifdef NO_EXTERNAL_INDIRECT_ADDRESS
1132
1133 /* Re-definition of CONSTANT_ADDRESS_P, which is true only when there
1134 are no SYMBOL_REFs for external symbols present. */
1135
1136 static int
1137 indirectable_constant_address_p (rtx x)
1138 {
1139 if (!CONSTANT_ADDRESS_P (x))
1140 return 0;
1141 if (GET_CODE (x) == CONST && GET_CODE (XEXP ((x), 0)) == PLUS)
1142 x = XEXP (XEXP (x, 0), 0);
1143 if (GET_CODE (x) == SYMBOL_REF && !SYMBOL_REF_LOCAL_P (x))
1144 return 0;
1145
1146 return 1;
1147 }
1148
1149 #else /* not NO_EXTERNAL_INDIRECT_ADDRESS */
1150
1151 static int
1152 indirectable_constant_address_p (rtx x)
1153 {
1154 return CONSTANT_ADDRESS_P (x);
1155 }
1156
1157 #endif /* not NO_EXTERNAL_INDIRECT_ADDRESS */
1158
1159 /* Nonzero if X is an address which can be indirected. External symbols
1160 could be in a sharable image library, so we disallow those. */
1161
1162 static int
1163 indirectable_address_p(rtx x, int strict)
1164 {
1165 if (indirectable_constant_address_p (x))
1166 return 1;
1167 if (BASE_REGISTER_P (x, strict))
1168 return 1;
1169 if (GET_CODE (x) == PLUS
1170 && BASE_REGISTER_P (XEXP (x, 0), strict)
1171 && indirectable_constant_address_p (XEXP (x, 1)))
1172 return 1;
1173 return 0;
1174 }
1175
1176 /* Return 1 if x is a valid address not using indexing.
1177 (This much is the easy part.) */
1178 static int
1179 nonindexed_address_p (rtx x, int strict)
1180 {
1181 rtx xfoo0;
1182 if (REG_P (x))
1183 {
1184 extern rtx *reg_equiv_mem;
1185 if (!reload_in_progress
1186 || reg_equiv_mem[REGNO (x)] == 0
1187 || indirectable_address_p (reg_equiv_mem[REGNO (x)], strict))
1188 return 1;
1189 }
1190 if (indirectable_constant_address_p (x))
1191 return 1;
1192 if (indirectable_address_p (x, strict))
1193 return 1;
1194 xfoo0 = XEXP (x, 0);
1195 if (MEM_P (x) && indirectable_address_p (xfoo0, strict))
1196 return 1;
1197 if ((GET_CODE (x) == PRE_DEC || GET_CODE (x) == POST_INC)
1198 && BASE_REGISTER_P (xfoo0, strict))
1199 return 1;
1200 return 0;
1201 }
1202
1203 /* 1 if PROD is either a reg times size of mode MODE and MODE is less
1204 than or equal 8 bytes, or just a reg if MODE is one byte. */
1205
1206 static int
1207 index_term_p (rtx prod, enum machine_mode mode, int strict)
1208 {
1209 rtx xfoo0, xfoo1;
1210
1211 if (GET_MODE_SIZE (mode) == 1)
1212 return BASE_REGISTER_P (prod, strict);
1213
1214 if (GET_CODE (prod) != MULT || GET_MODE_SIZE (mode) > 8)
1215 return 0;
1216
1217 xfoo0 = XEXP (prod, 0);
1218 xfoo1 = XEXP (prod, 1);
1219
1220 if (CONST_INT_P (xfoo0)
1221 && INTVAL (xfoo0) == (int)GET_MODE_SIZE (mode)
1222 && INDEX_REGISTER_P (xfoo1, strict))
1223 return 1;
1224
1225 if (CONST_INT_P (xfoo1)
1226 && INTVAL (xfoo1) == (int)GET_MODE_SIZE (mode)
1227 && INDEX_REGISTER_P (xfoo0, strict))
1228 return 1;
1229
1230 return 0;
1231 }
1232
1233 /* Return 1 if X is the sum of a register
1234 and a valid index term for mode MODE. */
1235 static int
1236 reg_plus_index_p (rtx x, enum machine_mode mode, int strict)
1237 {
1238 rtx xfoo0, xfoo1;
1239
1240 if (GET_CODE (x) != PLUS)
1241 return 0;
1242
1243 xfoo0 = XEXP (x, 0);
1244 xfoo1 = XEXP (x, 1);
1245
1246 if (BASE_REGISTER_P (xfoo0, strict) && index_term_p (xfoo1, mode, strict))
1247 return 1;
1248
1249 if (BASE_REGISTER_P (xfoo1, strict) && index_term_p (xfoo0, mode, strict))
1250 return 1;
1251
1252 return 0;
1253 }
1254
1255 /* legitimate_address_p returns 1 if it recognizes an RTL expression "x"
1256 that is a valid memory address for an instruction.
1257 The MODE argument is the machine mode for the MEM expression
1258 that wants to use this address. */
1259 int
1260 legitimate_address_p (enum machine_mode mode, rtx x, int strict)
1261 {
1262 rtx xfoo0, xfoo1;
1263
1264 if (nonindexed_address_p (x, strict))
1265 return 1;
1266
1267 if (GET_CODE (x) != PLUS)
1268 return 0;
1269
1270 /* Handle <address>[index] represented with index-sum outermost */
1271
1272 xfoo0 = XEXP (x, 0);
1273 xfoo1 = XEXP (x, 1);
1274
1275 if (index_term_p (xfoo0, mode, strict)
1276 && nonindexed_address_p (xfoo1, strict))
1277 return 1;
1278
1279 if (index_term_p (xfoo1, mode, strict)
1280 && nonindexed_address_p (xfoo0, strict))
1281 return 1;
1282
1283 /* Handle offset(reg)[index] with offset added outermost */
1284
1285 if (indirectable_constant_address_p (xfoo0)
1286 && (BASE_REGISTER_P (xfoo1, strict)
1287 || reg_plus_index_p (xfoo1, mode, strict)))
1288 return 1;
1289
1290 if (indirectable_constant_address_p (xfoo1)
1291 && (BASE_REGISTER_P (xfoo0, strict)
1292 || reg_plus_index_p (xfoo0, mode, strict)))
1293 return 1;
1294
1295 return 0;
1296 }
1297
1298 /* Return 1 if x (a legitimate address expression) has an effect that
1299 depends on the machine mode it is used for. On the VAX, the predecrement
1300 and postincrement address depend thus (the amount of decrement or
1301 increment being the length of the operand) and all indexed address depend
1302 thus (because the index scale factor is the length of the operand). */
1303
1304 int
1305 vax_mode_dependent_address_p (rtx x)
1306 {
1307 rtx xfoo0, xfoo1;
1308
1309 /* Auto-increment cases are now dealt with generically in recog.c. */
1310
1311 if (GET_CODE (x) != PLUS)
1312 return 0;
1313
1314 xfoo0 = XEXP (x, 0);
1315 xfoo1 = XEXP (x, 1);
1316
1317 if (CONSTANT_ADDRESS_P (xfoo0) && REG_P (xfoo1))
1318 return 0;
1319 if (CONSTANT_ADDRESS_P (xfoo1) && REG_P (xfoo0))
1320 return 0;
1321
1322 return 1;
1323 }