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comparison gcc/config/i386/sse.md @ 63:b7f97abdc517 gcc-4.6-20100522

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update gcc from gcc-4.5.0 to gcc-4.6
author ryoma <e075725@ie.u-ryukyu.ac.jp>
date Mon, 24 May 2010 12:47:05 +0900
parents 77e2b8dfacca
children f6334be47118
comparison
equal deleted inserted replaced
56:3c8a44c06a95 63:b7f97abdc517
1 ;; GCC machine description for SSE instructions 1 ;; GCC machine description for SSE instructions
2 ;; Copyright (C) 2005, 2006, 2007, 2008, 2009 2 ;; Copyright (C) 2005, 2006, 2007, 2008, 2009, 2010
3 ;; Free Software Foundation, Inc. 3 ;; Free Software Foundation, Inc.
4 ;; 4 ;;
5 ;; This file is part of GCC. 5 ;; This file is part of GCC.
6 ;; 6 ;;
7 ;; GCC is free software; you can redistribute it and/or modify 7 ;; GCC is free software; you can redistribute it and/or modify
192 case MODE_V8SF: 192 case MODE_V8SF:
193 case MODE_V4SF: 193 case MODE_V4SF:
194 return "vmovaps\t{%1, %0|%0, %1}"; 194 return "vmovaps\t{%1, %0|%0, %1}";
195 case MODE_V4DF: 195 case MODE_V4DF:
196 case MODE_V2DF: 196 case MODE_V2DF:
197 return "vmovapd\t{%1, %0|%0, %1}"; 197 if (TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL)
198 return "vmovaps\t{%1, %0|%0, %1}";
199 else
200 return "vmovapd\t{%1, %0|%0, %1}";
198 default: 201 default:
199 return "vmovdqa\t{%1, %0|%0, %1}"; 202 if (TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL)
203 return "vmovaps\t{%1, %0|%0, %1}";
204 else
205 return "vmovdqa\t{%1, %0|%0, %1}";
200 } 206 }
201 default: 207 default:
202 gcc_unreachable (); 208 gcc_unreachable ();
203 } 209 }
204 } 210 }
234 switch (get_attr_mode (insn)) 240 switch (get_attr_mode (insn))
235 { 241 {
236 case MODE_V4SF: 242 case MODE_V4SF:
237 return "movaps\t{%1, %0|%0, %1}"; 243 return "movaps\t{%1, %0|%0, %1}";
238 case MODE_V2DF: 244 case MODE_V2DF:
239 return "movapd\t{%1, %0|%0, %1}"; 245 if (TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL)
246 return "movaps\t{%1, %0|%0, %1}";
247 else
248 return "movapd\t{%1, %0|%0, %1}";
240 default: 249 default:
241 return "movdqa\t{%1, %0|%0, %1}"; 250 if (TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL)
251 return "movaps\t{%1, %0|%0, %1}";
252 else
253 return "movdqa\t{%1, %0|%0, %1}";
242 } 254 }
243 default: 255 default:
244 gcc_unreachable (); 256 gcc_unreachable ();
245 } 257 }
246 } 258 }
1013 (smaxmin:AVXMODEF2P 1025 (smaxmin:AVXMODEF2P
1014 (match_operand:AVXMODEF2P 1 "nonimmediate_operand" "%x") 1026 (match_operand:AVXMODEF2P 1 "nonimmediate_operand" "%x")
1015 (match_operand:AVXMODEF2P 2 "nonimmediate_operand" "xm")))] 1027 (match_operand:AVXMODEF2P 2 "nonimmediate_operand" "xm")))]
1016 "AVX_VEC_FLOAT_MODE_P (<MODE>mode) && flag_finite_math_only 1028 "AVX_VEC_FLOAT_MODE_P (<MODE>mode) && flag_finite_math_only
1017 && ix86_binary_operator_ok (<CODE>, <MODE>mode, operands)" 1029 && ix86_binary_operator_ok (<CODE>, <MODE>mode, operands)"
1018 "v<maxminfprefix>p<avxmodesuffixf2c>\t{%2, %1, %0|%0, %1, %2}" 1030 "v<maxmin_float>p<avxmodesuffixf2c>\t{%2, %1, %0|%0, %1, %2}"
1019 [(set_attr "type" "sseadd") 1031 [(set_attr "type" "sseadd")
1020 (set_attr "prefix" "vex") 1032 (set_attr "prefix" "vex")
1021 (set_attr "mode" "<MODE>")]) 1033 (set_attr "mode" "<MODE>")])
1022 1034
1023 (define_insn "*<code><mode>3_finite" 1035 (define_insn "*<code><mode>3_finite"
1025 (smaxmin:SSEMODEF2P 1037 (smaxmin:SSEMODEF2P
1026 (match_operand:SSEMODEF2P 1 "nonimmediate_operand" "%0") 1038 (match_operand:SSEMODEF2P 1 "nonimmediate_operand" "%0")
1027 (match_operand:SSEMODEF2P 2 "nonimmediate_operand" "xm")))] 1039 (match_operand:SSEMODEF2P 2 "nonimmediate_operand" "xm")))]
1028 "SSE_VEC_FLOAT_MODE_P (<MODE>mode) && flag_finite_math_only 1040 "SSE_VEC_FLOAT_MODE_P (<MODE>mode) && flag_finite_math_only
1029 && ix86_binary_operator_ok (<CODE>, <MODE>mode, operands)" 1041 && ix86_binary_operator_ok (<CODE>, <MODE>mode, operands)"
1030 "<maxminfprefix>p<ssemodesuffixf2c>\t{%2, %0|%0, %2}" 1042 "<maxmin_float>p<ssemodesuffixf2c>\t{%2, %0|%0, %2}"
1031 [(set_attr "type" "sseadd") 1043 [(set_attr "type" "sseadd")
1032 (set_attr "mode" "<MODE>")]) 1044 (set_attr "mode" "<MODE>")])
1033 1045
1034 (define_insn "*avx_<code><mode>3" 1046 (define_insn "*avx_<code><mode>3"
1035 [(set (match_operand:AVXMODEF2P 0 "register_operand" "=x") 1047 [(set (match_operand:AVXMODEF2P 0 "register_operand" "=x")
1036 (smaxmin:AVXMODEF2P 1048 (smaxmin:AVXMODEF2P
1037 (match_operand:AVXMODEF2P 1 "nonimmediate_operand" "%x") 1049 (match_operand:AVXMODEF2P 1 "nonimmediate_operand" "%x")
1038 (match_operand:AVXMODEF2P 2 "nonimmediate_operand" "xm")))] 1050 (match_operand:AVXMODEF2P 2 "nonimmediate_operand" "xm")))]
1039 "AVX_VEC_FLOAT_MODE_P (<MODE>mode)" 1051 "AVX_VEC_FLOAT_MODE_P (<MODE>mode)"
1040 "v<maxminfprefix>p<avxmodesuffixf2c>\t{%2, %1, %0|%0, %1, %2}" 1052 "v<maxmin_float>p<avxmodesuffixf2c>\t{%2, %1, %0|%0, %1, %2}"
1041 [(set_attr "type" "sseadd") 1053 [(set_attr "type" "sseadd")
1042 (set_attr "prefix" "vex") 1054 (set_attr "prefix" "vex")
1043 (set_attr "mode" "<avxvecmode>")]) 1055 (set_attr "mode" "<avxvecmode>")])
1044 1056
1045 (define_insn "*<code><mode>3" 1057 (define_insn "*<code><mode>3"
1046 [(set (match_operand:SSEMODEF2P 0 "register_operand" "=x") 1058 [(set (match_operand:SSEMODEF2P 0 "register_operand" "=x")
1047 (smaxmin:SSEMODEF2P 1059 (smaxmin:SSEMODEF2P
1048 (match_operand:SSEMODEF2P 1 "register_operand" "0") 1060 (match_operand:SSEMODEF2P 1 "register_operand" "0")
1049 (match_operand:SSEMODEF2P 2 "nonimmediate_operand" "xm")))] 1061 (match_operand:SSEMODEF2P 2 "nonimmediate_operand" "xm")))]
1050 "SSE_VEC_FLOAT_MODE_P (<MODE>mode)" 1062 "SSE_VEC_FLOAT_MODE_P (<MODE>mode)"
1051 "<maxminfprefix>p<ssemodesuffixf2c>\t{%2, %0|%0, %2}" 1063 "<maxmin_float>p<ssemodesuffixf2c>\t{%2, %0|%0, %2}"
1052 [(set_attr "type" "sseadd") 1064 [(set_attr "type" "sseadd")
1053 (set_attr "mode" "<MODE>")]) 1065 (set_attr "mode" "<MODE>")])
1054 1066
1055 (define_insn "*avx_vm<code><mode>3" 1067 (define_insn "*avx_vm<code><mode>3"
1056 [(set (match_operand:SSEMODEF2P 0 "register_operand" "=x") 1068 [(set (match_operand:SSEMODEF2P 0 "register_operand" "=x")
1059 (match_operand:SSEMODEF2P 1 "register_operand" "x") 1071 (match_operand:SSEMODEF2P 1 "register_operand" "x")
1060 (match_operand:SSEMODEF2P 2 "nonimmediate_operand" "xm")) 1072 (match_operand:SSEMODEF2P 2 "nonimmediate_operand" "xm"))
1061 (match_dup 1) 1073 (match_dup 1)
1062 (const_int 1)))] 1074 (const_int 1)))]
1063 "AVX128_VEC_FLOAT_MODE_P (<MODE>mode)" 1075 "AVX128_VEC_FLOAT_MODE_P (<MODE>mode)"
1064 "v<maxminfprefix>s<ssemodesuffixf2c>\t{%2, %1, %0|%0, %1, %2}" 1076 "v<maxmin_float>s<ssemodesuffixf2c>\t{%2, %1, %0|%0, %1, %2}"
1065 [(set_attr "type" "sse") 1077 [(set_attr "type" "sse")
1066 (set_attr "prefix" "vex") 1078 (set_attr "prefix" "vex")
1067 (set_attr "mode" "<ssescalarmode>")]) 1079 (set_attr "mode" "<ssescalarmode>")])
1068 1080
1069 (define_insn "<sse>_vm<code><mode>3" 1081 (define_insn "<sse>_vm<code><mode>3"
1073 (match_operand:SSEMODEF2P 1 "register_operand" "0") 1085 (match_operand:SSEMODEF2P 1 "register_operand" "0")
1074 (match_operand:SSEMODEF2P 2 "nonimmediate_operand" "xm")) 1086 (match_operand:SSEMODEF2P 2 "nonimmediate_operand" "xm"))
1075 (match_dup 1) 1087 (match_dup 1)
1076 (const_int 1)))] 1088 (const_int 1)))]
1077 "SSE_VEC_FLOAT_MODE_P (<MODE>mode)" 1089 "SSE_VEC_FLOAT_MODE_P (<MODE>mode)"
1078 "<maxminfprefix>s<ssemodesuffixf2c>\t{%2, %0|%0, %2}" 1090 "<maxmin_float>s<ssemodesuffixf2c>\t{%2, %0|%0, %2}"
1079 [(set_attr "type" "sseadd") 1091 [(set_attr "type" "sseadd")
1080 (set_attr "mode" "<ssescalarmode>")]) 1092 (set_attr "mode" "<ssescalarmode>")])
1081 1093
1082 ;; These versions of the min/max patterns implement exactly the operations 1094 ;; These versions of the min/max patterns implement exactly the operations
1083 ;; min = (op1 < op2 ? op1 : op2) 1095 ;; min = (op1 < op2 ? op1 : op2)
1481 "cmp%D3<ssemodesuffixf4>\t{%2, %0|%0, %2}" 1493 "cmp%D3<ssemodesuffixf4>\t{%2, %0|%0, %2}"
1482 [(set_attr "type" "ssecmp") 1494 [(set_attr "type" "ssecmp")
1483 (set_attr "length_immediate" "1") 1495 (set_attr "length_immediate" "1")
1484 (set_attr "mode" "<MODE>")]) 1496 (set_attr "mode" "<MODE>")])
1485 1497
1498 (define_insn "*avx_vmmaskcmp<mode>3"
1499 [(set (match_operand:SSEMODEF2P 0 "register_operand" "=x")
1500 (vec_merge:SSEMODEF2P
1501 (match_operator:SSEMODEF2P 3 "sse_comparison_operator"
1502 [(match_operand:SSEMODEF2P 1 "register_operand" "x")
1503 (match_operand:SSEMODEF2P 2 "nonimmediate_operand" "xm")])
1504 (match_dup 1)
1505 (const_int 1)))]
1506 "AVX_VEC_FLOAT_MODE_P (<MODE>mode)"
1507 "vcmp%D3s<ssemodesuffixf2c>\t{%2, %1, %0|%0, %1, %2}"
1508 [(set_attr "type" "ssecmp")
1509 (set_attr "prefix" "vex")
1510 (set_attr "mode" "<ssescalarmode>")])
1511
1486 (define_insn "<sse>_vmmaskcmp<mode>3" 1512 (define_insn "<sse>_vmmaskcmp<mode>3"
1487 [(set (match_operand:SSEMODEF2P 0 "register_operand" "=x") 1513 [(set (match_operand:SSEMODEF2P 0 "register_operand" "=x")
1488 (vec_merge:SSEMODEF2P 1514 (vec_merge:SSEMODEF2P
1489 (match_operator:SSEMODEF2P 3 "sse_comparison_operator" 1515 (match_operator:SSEMODEF2P 3 "sse_comparison_operator"
1490 [(match_operand:SSEMODEF2P 1 "register_operand" "0") 1516 [(match_operand:SSEMODEF2P 1 "register_operand" "0")
1536 (const_string "1") 1562 (const_string "1")
1537 (const_string "0"))) 1563 (const_string "0")))
1538 (set_attr "mode" "<MODE>")]) 1564 (set_attr "mode" "<MODE>")])
1539 1565
1540 (define_expand "vcond<mode>" 1566 (define_expand "vcond<mode>"
1541 [(set (match_operand:SSEMODEF2P 0 "register_operand" "") 1567 [(set (match_operand:AVXMODEF2P 0 "register_operand" "")
1542 (if_then_else:SSEMODEF2P 1568 (if_then_else:AVXMODEF2P
1543 (match_operator 3 "" 1569 (match_operator 3 ""
1544 [(match_operand:SSEMODEF2P 4 "nonimmediate_operand" "") 1570 [(match_operand:AVXMODEF2P 4 "nonimmediate_operand" "")
1545 (match_operand:SSEMODEF2P 5 "nonimmediate_operand" "")]) 1571 (match_operand:AVXMODEF2P 5 "nonimmediate_operand" "")])
1546 (match_operand:SSEMODEF2P 1 "general_operand" "") 1572 (match_operand:AVXMODEF2P 1 "general_operand" "")
1547 (match_operand:SSEMODEF2P 2 "general_operand" "")))] 1573 (match_operand:AVXMODEF2P 2 "general_operand" "")))]
1548 "SSE_VEC_FLOAT_MODE_P (<MODE>mode)" 1574 "(SSE_VEC_FLOAT_MODE_P (<MODE>mode)
1575 || AVX_VEC_FLOAT_MODE_P (<MODE>mode))"
1549 { 1576 {
1550 bool ok = ix86_expand_fp_vcond (operands); 1577 bool ok = ix86_expand_fp_vcond (operands);
1551 gcc_assert (ok); 1578 gcc_assert (ok);
1552 DONE; 1579 DONE;
1553 }) 1580 })
1594 (any_logic:AVXMODEF2P 1621 (any_logic:AVXMODEF2P
1595 (match_operand:AVXMODEF2P 1 "nonimmediate_operand" "%x") 1622 (match_operand:AVXMODEF2P 1 "nonimmediate_operand" "%x")
1596 (match_operand:AVXMODEF2P 2 "nonimmediate_operand" "xm")))] 1623 (match_operand:AVXMODEF2P 2 "nonimmediate_operand" "xm")))]
1597 "AVX_VEC_FLOAT_MODE_P (<MODE>mode) 1624 "AVX_VEC_FLOAT_MODE_P (<MODE>mode)
1598 && ix86_binary_operator_ok (<CODE>, <MODE>mode, operands)" 1625 && ix86_binary_operator_ok (<CODE>, <MODE>mode, operands)"
1599 "v<logicprefix>p<avxmodesuffixf2c>\t{%2, %1, %0|%0, %1, %2}" 1626 {
1627 if (TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL)
1628 return "v<logic>ps\t{%2, %1, %0|%0, %1, %2}";
1629 else
1630 return "v<logic>p<avxmodesuffixf2c>\t{%2, %1, %0|%0, %1, %2}";
1631 }
1600 [(set_attr "type" "sselog") 1632 [(set_attr "type" "sselog")
1601 (set_attr "prefix" "vex") 1633 (set_attr "prefix" "vex")
1602 (set_attr "mode" "<avxvecmode>")]) 1634 (set_attr "mode" "<avxvecmode>")])
1603 1635
1604 (define_expand "<code><mode>3" 1636 (define_expand "<code><mode>3"
1614 (any_logic:SSEMODEF2P 1646 (any_logic:SSEMODEF2P
1615 (match_operand:SSEMODEF2P 1 "nonimmediate_operand" "%0") 1647 (match_operand:SSEMODEF2P 1 "nonimmediate_operand" "%0")
1616 (match_operand:SSEMODEF2P 2 "nonimmediate_operand" "xm")))] 1648 (match_operand:SSEMODEF2P 2 "nonimmediate_operand" "xm")))]
1617 "SSE_VEC_FLOAT_MODE_P (<MODE>mode) 1649 "SSE_VEC_FLOAT_MODE_P (<MODE>mode)
1618 && ix86_binary_operator_ok (<CODE>, <MODE>mode, operands)" 1650 && ix86_binary_operator_ok (<CODE>, <MODE>mode, operands)"
1619 "<logicprefix>p<ssemodesuffixf2c>\t{%2, %0|%0, %2}" 1651 {
1652 if (TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL)
1653 return "<logic>ps\t{%2, %0|%0, %2}";
1654 else
1655 return "<logic>p<ssemodesuffixf2c>\t{%2, %0|%0, %2}";
1656 }
1620 [(set_attr "type" "sselog") 1657 [(set_attr "type" "sselog")
1621 (set_attr "mode" "<MODE>")]) 1658 (set_attr "mode" "<MODE>")])
1622 1659
1623 (define_expand "copysign<mode>3" 1660 (define_expand "copysign<mode>3"
1624 [(set (match_dup 4) 1661 [(set (match_dup 4)
1670 [(set (match_operand:MODEF 0 "register_operand" "=x") 1707 [(set (match_operand:MODEF 0 "register_operand" "=x")
1671 (any_logic:MODEF 1708 (any_logic:MODEF
1672 (match_operand:MODEF 1 "register_operand" "x") 1709 (match_operand:MODEF 1 "register_operand" "x")
1673 (match_operand:MODEF 2 "register_operand" "x")))] 1710 (match_operand:MODEF 2 "register_operand" "x")))]
1674 "AVX_FLOAT_MODE_P (<MODE>mode)" 1711 "AVX_FLOAT_MODE_P (<MODE>mode)"
1675 "v<logicprefix>p<ssemodefsuffix>\t{%2, %1, %0|%0, %1, %2}" 1712 {
1713 if (TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL)
1714 return "v<logic>ps\t{%2, %1, %0|%0, %1, %2}";
1715 else
1716 return "v<logic>p<ssemodefsuffix>\t{%2, %1, %0|%0, %1, %2}";
1717 }
1676 [(set_attr "type" "sselog") 1718 [(set_attr "type" "sselog")
1677 (set_attr "prefix" "vex") 1719 (set_attr "prefix" "vex")
1678 (set_attr "mode" "<ssevecmode>")]) 1720 (set_attr "mode" "<ssevecmode>")])
1679 1721
1680 (define_insn "*<code><mode>3" 1722 (define_insn "*<code><mode>3"
1681 [(set (match_operand:MODEF 0 "register_operand" "=x") 1723 [(set (match_operand:MODEF 0 "register_operand" "=x")
1682 (any_logic:MODEF 1724 (any_logic:MODEF
1683 (match_operand:MODEF 1 "register_operand" "0") 1725 (match_operand:MODEF 1 "register_operand" "0")
1684 (match_operand:MODEF 2 "register_operand" "x")))] 1726 (match_operand:MODEF 2 "register_operand" "x")))]
1685 "SSE_FLOAT_MODE_P (<MODE>mode)" 1727 "SSE_FLOAT_MODE_P (<MODE>mode)"
1686 "<logicprefix>p<ssemodefsuffix>\t{%2, %0|%0, %2}" 1728 {
1729 if (TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL)
1730 return "<logic>ps\t{%2, %0|%0, %2}";
1731 else
1732 return "<logic>p<ssemodefsuffix>\t{%2, %0|%0, %2}";
1733 }
1687 [(set_attr "type" "sselog") 1734 [(set_attr "type" "sselog")
1688 (set_attr "mode" "<ssevecmode>")]) 1735 (set_attr "mode" "<ssevecmode>")])
1689 1736
1690 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; 1737 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
1691 ;; 1738 ;;
6028 [(set (match_operand:SSEMODE124 0 "register_operand" "=x") 6075 [(set (match_operand:SSEMODE124 0 "register_operand" "=x")
6029 (maxmin:SSEMODE124 6076 (maxmin:SSEMODE124
6030 (match_operand:SSEMODE124 1 "nonimmediate_operand" "%x") 6077 (match_operand:SSEMODE124 1 "nonimmediate_operand" "%x")
6031 (match_operand:SSEMODE124 2 "nonimmediate_operand" "xm")))] 6078 (match_operand:SSEMODE124 2 "nonimmediate_operand" "xm")))]
6032 "TARGET_AVX && ix86_binary_operator_ok (<CODE>, <MODE>mode, operands)" 6079 "TARGET_AVX && ix86_binary_operator_ok (<CODE>, <MODE>mode, operands)"
6033 "vp<maxminiprefix><ssevecsize>\t{%2, %1, %0|%0, %1, %2}" 6080 "vp<maxmin_int><ssevecsize>\t{%2, %1, %0|%0, %1, %2}"
6034 [(set_attr "type" "sseiadd") 6081 [(set_attr "type" "sseiadd")
6035 (set (attr "prefix_extra") 6082 (set (attr "prefix_extra")
6036 (if_then_else 6083 (if_then_else
6037 (ne (symbol_ref "<MODE>mode != ((<CODE> == SMAX || <CODE> == SMIN) ? V8HImode : V16QImode)") 6084 (ne (symbol_ref "<MODE>mode != ((<CODE> == SMAX || <CODE> == SMIN) ? V8HImode : V16QImode)")
6038 (const_int 0)) 6085 (const_int 0))
6053 [(set (match_operand:V16QI 0 "register_operand" "=x") 6100 [(set (match_operand:V16QI 0 "register_operand" "=x")
6054 (umaxmin:V16QI 6101 (umaxmin:V16QI
6055 (match_operand:V16QI 1 "nonimmediate_operand" "%0") 6102 (match_operand:V16QI 1 "nonimmediate_operand" "%0")
6056 (match_operand:V16QI 2 "nonimmediate_operand" "xm")))] 6103 (match_operand:V16QI 2 "nonimmediate_operand" "xm")))]
6057 "TARGET_SSE2 && ix86_binary_operator_ok (<CODE>, V16QImode, operands)" 6104 "TARGET_SSE2 && ix86_binary_operator_ok (<CODE>, V16QImode, operands)"
6058 "p<maxminiprefix>b\t{%2, %0|%0, %2}" 6105 "p<maxmin_int>b\t{%2, %0|%0, %2}"
6059 [(set_attr "type" "sseiadd") 6106 [(set_attr "type" "sseiadd")
6060 (set_attr "prefix_data16" "1") 6107 (set_attr "prefix_data16" "1")
6061 (set_attr "mode" "TI")]) 6108 (set_attr "mode" "TI")])
6062 6109
6063 (define_expand "<code>v8hi3" 6110 (define_expand "<code>v8hi3"
6072 [(set (match_operand:V8HI 0 "register_operand" "=x") 6119 [(set (match_operand:V8HI 0 "register_operand" "=x")
6073 (smaxmin:V8HI 6120 (smaxmin:V8HI
6074 (match_operand:V8HI 1 "nonimmediate_operand" "%0") 6121 (match_operand:V8HI 1 "nonimmediate_operand" "%0")
6075 (match_operand:V8HI 2 "nonimmediate_operand" "xm")))] 6122 (match_operand:V8HI 2 "nonimmediate_operand" "xm")))]
6076 "TARGET_SSE2 && ix86_binary_operator_ok (<CODE>, V8HImode, operands)" 6123 "TARGET_SSE2 && ix86_binary_operator_ok (<CODE>, V8HImode, operands)"
6077 "p<maxminiprefix>w\t{%2, %0|%0, %2}" 6124 "p<maxmin_int>w\t{%2, %0|%0, %2}"
6078 [(set_attr "type" "sseiadd") 6125 [(set_attr "type" "sseiadd")
6079 (set_attr "prefix_data16" "1") 6126 (set_attr "prefix_data16" "1")
6080 (set_attr "mode" "TI")]) 6127 (set_attr "mode" "TI")])
6081 6128
6082 (define_expand "umaxv8hi3" 6129 (define_expand "umaxv8hi3"
6127 [(set (match_operand:SSEMODE14 0 "register_operand" "=x") 6174 [(set (match_operand:SSEMODE14 0 "register_operand" "=x")
6128 (smaxmin:SSEMODE14 6175 (smaxmin:SSEMODE14
6129 (match_operand:SSEMODE14 1 "nonimmediate_operand" "%0") 6176 (match_operand:SSEMODE14 1 "nonimmediate_operand" "%0")
6130 (match_operand:SSEMODE14 2 "nonimmediate_operand" "xm")))] 6177 (match_operand:SSEMODE14 2 "nonimmediate_operand" "xm")))]
6131 "TARGET_SSE4_1 && ix86_binary_operator_ok (<CODE>, <MODE>mode, operands)" 6178 "TARGET_SSE4_1 && ix86_binary_operator_ok (<CODE>, <MODE>mode, operands)"
6132 "p<maxminiprefix><ssevecsize>\t{%2, %0|%0, %2}" 6179 "p<maxmin_int><ssevecsize>\t{%2, %0|%0, %2}"
6133 [(set_attr "type" "sseiadd") 6180 [(set_attr "type" "sseiadd")
6134 (set_attr "prefix_extra" "1") 6181 (set_attr "prefix_extra" "1")
6135 (set_attr "mode" "TI")]) 6182 (set_attr "mode" "TI")])
6183
6184 (define_expand "smaxv2di3"
6185 [(set (match_operand:V2DI 0 "register_operand" "")
6186 (smax:V2DI (match_operand:V2DI 1 "register_operand" "")
6187 (match_operand:V2DI 2 "register_operand" "")))]
6188 "TARGET_SSE4_2"
6189 {
6190 rtx xops[6];
6191 bool ok;
6192
6193 xops[0] = operands[0];
6194 xops[1] = operands[1];
6195 xops[2] = operands[2];
6196 xops[3] = gen_rtx_GT (VOIDmode, operands[1], operands[2]);
6197 xops[4] = operands[1];
6198 xops[5] = operands[2];
6199 ok = ix86_expand_int_vcond (xops);
6200 gcc_assert (ok);
6201 DONE;
6202 })
6136 6203
6137 (define_expand "umaxv4si3" 6204 (define_expand "umaxv4si3"
6138 [(set (match_operand:V4SI 0 "register_operand" "") 6205 [(set (match_operand:V4SI 0 "register_operand" "")
6139 (umax:V4SI (match_operand:V4SI 1 "register_operand" "") 6206 (umax:V4SI (match_operand:V4SI 1 "register_operand" "")
6140 (match_operand:V4SI 2 "register_operand" "")))] 6207 (match_operand:V4SI 2 "register_operand" "")))]
6163 [(set (match_operand:SSEMODE24 0 "register_operand" "=x") 6230 [(set (match_operand:SSEMODE24 0 "register_operand" "=x")
6164 (umaxmin:SSEMODE24 6231 (umaxmin:SSEMODE24
6165 (match_operand:SSEMODE24 1 "nonimmediate_operand" "%0") 6232 (match_operand:SSEMODE24 1 "nonimmediate_operand" "%0")
6166 (match_operand:SSEMODE24 2 "nonimmediate_operand" "xm")))] 6233 (match_operand:SSEMODE24 2 "nonimmediate_operand" "xm")))]
6167 "TARGET_SSE4_1 && ix86_binary_operator_ok (<CODE>, <MODE>mode, operands)" 6234 "TARGET_SSE4_1 && ix86_binary_operator_ok (<CODE>, <MODE>mode, operands)"
6168 "p<maxminiprefix><ssevecsize>\t{%2, %0|%0, %2}" 6235 "p<maxmin_int><ssevecsize>\t{%2, %0|%0, %2}"
6169 [(set_attr "type" "sseiadd") 6236 [(set_attr "type" "sseiadd")
6170 (set_attr "prefix_extra" "1") 6237 (set_attr "prefix_extra" "1")
6171 (set_attr "mode" "TI")]) 6238 (set_attr "mode" "TI")])
6239
6240 (define_expand "umaxv2di3"
6241 [(set (match_operand:V2DI 0 "register_operand" "")
6242 (umax:V2DI (match_operand:V2DI 1 "register_operand" "")
6243 (match_operand:V2DI 2 "register_operand" "")))]
6244 "TARGET_SSE4_2"
6245 {
6246 rtx xops[6];
6247 bool ok;
6248
6249 xops[0] = operands[0];
6250 xops[1] = operands[1];
6251 xops[2] = operands[2];
6252 xops[3] = gen_rtx_GTU (VOIDmode, operands[1], operands[2]);
6253 xops[4] = operands[1];
6254 xops[5] = operands[2];
6255 ok = ix86_expand_int_vcond (xops);
6256 gcc_assert (ok);
6257 DONE;
6258 })
6172 6259
6173 (define_expand "smin<mode>3" 6260 (define_expand "smin<mode>3"
6174 [(set (match_operand:SSEMODE14 0 "register_operand" "") 6261 [(set (match_operand:SSEMODE14 0 "register_operand" "")
6175 (smin:SSEMODE14 (match_operand:SSEMODE14 1 "register_operand" "") 6262 (smin:SSEMODE14 (match_operand:SSEMODE14 1 "register_operand" "")
6176 (match_operand:SSEMODE14 2 "register_operand" "")))] 6263 (match_operand:SSEMODE14 2 "register_operand" "")))]
6193 gcc_assert (ok); 6280 gcc_assert (ok);
6194 DONE; 6281 DONE;
6195 } 6282 }
6196 }) 6283 })
6197 6284
6285 (define_expand "sminv2di3"
6286 [(set (match_operand:V2DI 0 "register_operand" "")
6287 (smin:V2DI (match_operand:V2DI 1 "register_operand" "")
6288 (match_operand:V2DI 2 "register_operand" "")))]
6289 "TARGET_SSE4_2"
6290 {
6291 rtx xops[6];
6292 bool ok;
6293
6294 xops[0] = operands[0];
6295 xops[1] = operands[2];
6296 xops[2] = operands[1];
6297 xops[3] = gen_rtx_GT (VOIDmode, operands[1], operands[2]);
6298 xops[4] = operands[1];
6299 xops[5] = operands[2];
6300 ok = ix86_expand_int_vcond (xops);
6301 gcc_assert (ok);
6302 DONE;
6303 })
6304
6198 (define_expand "umin<mode>3" 6305 (define_expand "umin<mode>3"
6199 [(set (match_operand:SSEMODE24 0 "register_operand" "") 6306 [(set (match_operand:SSEMODE24 0 "register_operand" "")
6200 (umin:SSEMODE24 (match_operand:SSEMODE24 1 "register_operand" "") 6307 (umin:SSEMODE24 (match_operand:SSEMODE24 1 "register_operand" "")
6201 (match_operand:SSEMODE24 2 "register_operand" "")))] 6308 (match_operand:SSEMODE24 2 "register_operand" "")))]
6202 "TARGET_SSE2" 6309 "TARGET_SSE2"
6216 xops[5] = operands[2]; 6323 xops[5] = operands[2];
6217 ok = ix86_expand_int_vcond (xops); 6324 ok = ix86_expand_int_vcond (xops);
6218 gcc_assert (ok); 6325 gcc_assert (ok);
6219 DONE; 6326 DONE;
6220 } 6327 }
6328 })
6329
6330 (define_expand "uminv2di3"
6331 [(set (match_operand:V2DI 0 "register_operand" "")
6332 (umin:V2DI (match_operand:V2DI 1 "register_operand" "")
6333 (match_operand:V2DI 2 "register_operand" "")))]
6334 "TARGET_SSE4_2"
6335 {
6336 rtx xops[6];
6337 bool ok;
6338
6339 xops[0] = operands[0];
6340 xops[1] = operands[2];
6341 xops[2] = operands[1];
6342 xops[3] = gen_rtx_GTU (VOIDmode, operands[1], operands[2]);
6343 xops[4] = operands[1];
6344 xops[5] = operands[2];
6345 ok = ix86_expand_int_vcond (xops);
6346 gcc_assert (ok);
6347 DONE;
6221 }) 6348 })
6222 6349
6223 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; 6350 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
6224 ;; 6351 ;;
6225 ;; Parallel integral comparisons 6352 ;; Parallel integral comparisons
6435 (any_logic:AVX256MODEI 6562 (any_logic:AVX256MODEI
6436 (match_operand:AVX256MODEI 1 "nonimmediate_operand" "%x") 6563 (match_operand:AVX256MODEI 1 "nonimmediate_operand" "%x")
6437 (match_operand:AVX256MODEI 2 "nonimmediate_operand" "xm")))] 6564 (match_operand:AVX256MODEI 2 "nonimmediate_operand" "xm")))]
6438 "TARGET_AVX 6565 "TARGET_AVX
6439 && ix86_binary_operator_ok (<CODE>, <MODE>mode, operands)" 6566 && ix86_binary_operator_ok (<CODE>, <MODE>mode, operands)"
6440 "v<logicprefix>ps\t{%2, %1, %0|%0, %1, %2}" 6567 "v<logic>ps\t{%2, %1, %0|%0, %1, %2}"
6441 [(set_attr "type" "sselog") 6568 [(set_attr "type" "sselog")
6442 (set_attr "prefix" "vex") 6569 (set_attr "prefix" "vex")
6443 (set_attr "mode" "<avxvecpsmode>")]) 6570 (set_attr "mode" "<avxvecpsmode>")])
6444 6571
6445 (define_insn "*sse_<code><mode>3" 6572 (define_insn "*sse_<code><mode>3"
6447 (any_logic:SSEMODEI 6574 (any_logic:SSEMODEI
6448 (match_operand:SSEMODEI 1 "nonimmediate_operand" "%0") 6575 (match_operand:SSEMODEI 1 "nonimmediate_operand" "%0")
6449 (match_operand:SSEMODEI 2 "nonimmediate_operand" "xm")))] 6576 (match_operand:SSEMODEI 2 "nonimmediate_operand" "xm")))]
6450 "(TARGET_SSE && !TARGET_SSE2) 6577 "(TARGET_SSE && !TARGET_SSE2)
6451 && ix86_binary_operator_ok (<CODE>, <MODE>mode, operands)" 6578 && ix86_binary_operator_ok (<CODE>, <MODE>mode, operands)"
6452 "<logicprefix>ps\t{%2, %0|%0, %2}" 6579 "<logic>ps\t{%2, %0|%0, %2}"
6453 [(set_attr "type" "sselog") 6580 [(set_attr "type" "sselog")
6454 (set_attr "mode" "V4SF")]) 6581 (set_attr "mode" "V4SF")])
6455 6582
6456 (define_insn "*avx_<code><mode>3" 6583 (define_insn "*avx_<code><mode>3"
6457 [(set (match_operand:SSEMODEI 0 "register_operand" "=x") 6584 [(set (match_operand:SSEMODEI 0 "register_operand" "=x")
6458 (any_logic:SSEMODEI 6585 (any_logic:SSEMODEI
6459 (match_operand:SSEMODEI 1 "nonimmediate_operand" "%x") 6586 (match_operand:SSEMODEI 1 "nonimmediate_operand" "%x")
6460 (match_operand:SSEMODEI 2 "nonimmediate_operand" "xm")))] 6587 (match_operand:SSEMODEI 2 "nonimmediate_operand" "xm")))]
6461 "TARGET_AVX 6588 "TARGET_AVX
6462 && ix86_binary_operator_ok (<CODE>, <MODE>mode, operands)" 6589 && ix86_binary_operator_ok (<CODE>, <MODE>mode, operands)"
6463 "vp<logicprefix>\t{%2, %1, %0|%0, %1, %2}" 6590 "vp<logic>\t{%2, %1, %0|%0, %1, %2}"
6464 [(set_attr "type" "sselog") 6591 [(set_attr "type" "sselog")
6465 (set_attr "prefix" "vex") 6592 (set_attr "prefix" "vex")
6466 (set_attr "mode" "TI")]) 6593 (set_attr "mode" "TI")])
6467 6594
6468 (define_insn "*sse2_<code><mode>3" 6595 (define_insn "*sse2_<code><mode>3"
6469 [(set (match_operand:SSEMODEI 0 "register_operand" "=x") 6596 [(set (match_operand:SSEMODEI 0 "register_operand" "=x")
6470 (any_logic:SSEMODEI 6597 (any_logic:SSEMODEI
6471 (match_operand:SSEMODEI 1 "nonimmediate_operand" "%0") 6598 (match_operand:SSEMODEI 1 "nonimmediate_operand" "%0")
6472 (match_operand:SSEMODEI 2 "nonimmediate_operand" "xm")))] 6599 (match_operand:SSEMODEI 2 "nonimmediate_operand" "xm")))]
6473 "TARGET_SSE2 && ix86_binary_operator_ok (<CODE>, <MODE>mode, operands)" 6600 "TARGET_SSE2 && ix86_binary_operator_ok (<CODE>, <MODE>mode, operands)"
6474 "p<logicprefix>\t{%2, %0|%0, %2}" 6601 "p<logic>\t{%2, %0|%0, %2}"
6475 [(set_attr "type" "sselog") 6602 [(set_attr "type" "sselog")
6476 (set_attr "prefix_data16" "1") 6603 (set_attr "prefix_data16" "1")
6477 (set_attr "mode" "TI")]) 6604 (set_attr "mode" "TI")])
6478 6605
6479 (define_expand "<code>tf3" 6606 (define_expand "<code>tf3"
6488 [(set (match_operand:TF 0 "register_operand" "=x") 6615 [(set (match_operand:TF 0 "register_operand" "=x")
6489 (any_logic:TF 6616 (any_logic:TF
6490 (match_operand:TF 1 "nonimmediate_operand" "%0") 6617 (match_operand:TF 1 "nonimmediate_operand" "%0")
6491 (match_operand:TF 2 "nonimmediate_operand" "xm")))] 6618 (match_operand:TF 2 "nonimmediate_operand" "xm")))]
6492 "TARGET_SSE2 && ix86_binary_operator_ok (<CODE>, TFmode, operands)" 6619 "TARGET_SSE2 && ix86_binary_operator_ok (<CODE>, TFmode, operands)"
6493 "p<logicprefix>\t{%2, %0|%0, %2}" 6620 "p<logic>\t{%2, %0|%0, %2}"
6494 [(set_attr "type" "sselog") 6621 [(set_attr "type" "sselog")
6495 (set_attr "prefix_data16" "1") 6622 (set_attr "prefix_data16" "1")
6496 (set_attr "mode" "TI")]) 6623 (set_attr "mode" "TI")])
6497 6624
6498 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; 6625 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
10340 (const_int 3)])))) 10467 (const_int 3)]))))
10341 (match_dup 0)))] 10468 (match_dup 0)))]
10342 { 10469 {
10343 operands[3] = CONST0_RTX (V2DImode); 10470 operands[3] = CONST0_RTX (V2DImode);
10344 } 10471 }
10345 [(set_attr "type" "ssemuladd") 10472 [(set_attr "type" "ssemul")
10346 (set_attr "mode" "TI")]) 10473 (set_attr "mode" "TI")])
10347 10474
10348 (define_insn "xop_pmacsdqh" 10475 (define_insn "xop_pmacsdqh"
10349 [(set (match_operand:V2DI 0 "register_operand" "=x") 10476 [(set (match_operand:V2DI 0 "register_operand" "=x")
10350 (plus:V2DI 10477 (plus:V2DI
10402 (const_int 2)])))) 10529 (const_int 2)]))))
10403 (match_dup 0)))] 10530 (match_dup 0)))]
10404 { 10531 {
10405 operands[3] = CONST0_RTX (V2DImode); 10532 operands[3] = CONST0_RTX (V2DImode);
10406 } 10533 }
10407 [(set_attr "type" "ssemuladd") 10534 [(set_attr "type" "ssemul")
10408 (set_attr "mode" "TI")]) 10535 (set_attr "mode" "TI")])
10409 10536
10410 ;; XOP parallel integer multiply/add instructions for the intrinisics 10537 ;; XOP parallel integer multiply/add instructions for the intrinisics
10411 (define_insn "xop_pmacsswd" 10538 (define_insn "xop_pmacsswd"
10412 [(set (match_operand:V4SI 0 "register_operand" "=x") 10539 [(set (match_operand:V4SI 0 "register_operand" "=x")
11457 (set_attr "prefix_data16" "0") 11584 (set_attr "prefix_data16" "0")
11458 (set_attr "prefix_extra" "2") 11585 (set_attr "prefix_extra" "2")
11459 (set_attr "length_immediate" "1") 11586 (set_attr "length_immediate" "1")
11460 (set_attr "mode" "TI")]) 11587 (set_attr "mode" "TI")])
11461 11588
11589 (define_insn "xop_vpermil2<mode>3"
11590 [(set (match_operand:AVXMODEF2P 0 "register_operand" "=x")
11591 (unspec:AVXMODEF2P
11592 [(match_operand:AVXMODEF2P 1 "register_operand" "x")
11593 (match_operand:AVXMODEF2P 2 "nonimmediate_operand" "%x")
11594 (match_operand:<avxpermvecmode> 3 "nonimmediate_operand" "xm")
11595 (match_operand:SI 4 "const_0_to_3_operand" "n")]
11596 UNSPEC_VPERMIL2))]
11597 "TARGET_XOP"
11598 "vpermil2p<avxmodesuffixf2c>\t{%4, %3, %2, %1, %0|%0, %1, %2, %3, %4}"
11599 [(set_attr "type" "sse4arg")
11600 (set_attr "length_immediate" "1")
11601 (set_attr "mode" "<MODE>")])
11602
11462 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; 11603 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
11463 (define_insn "*avx_aesenc" 11604 (define_insn "*avx_aesenc"
11464 [(set (match_operand:V2DI 0 "register_operand" "=x") 11605 [(set (match_operand:V2DI 0 "register_operand" "=x")
11465 (unspec:V2DI [(match_operand:V2DI 1 "register_operand" "x") 11606 (unspec:V2DI [(match_operand:V2DI 1 "register_operand" "x")
11466 (match_operand:V2DI 2 "nonimmediate_operand" "xm")] 11607 (match_operand:V2DI 2 "nonimmediate_operand" "xm")]
11853 (match_operand:AVX256MODE2P 2 "nonimmediate_operand" "") 11994 (match_operand:AVX256MODE2P 2 "nonimmediate_operand" "")
11854 (match_operand:SI 3 "const_0_to_255_operand" "")] 11995 (match_operand:SI 3 "const_0_to_255_operand" "")]
11855 UNSPEC_VPERMIL2F128))] 11996 UNSPEC_VPERMIL2F128))]
11856 "TARGET_AVX" 11997 "TARGET_AVX"
11857 { 11998 {
11858 int mask = INTVAL (operands[2]); 11999 int mask = INTVAL (operands[3]);
11859 if ((mask & 0x88) == 0) 12000 if ((mask & 0x88) == 0)
11860 { 12001 {
11861 rtx perm[<ssescalarnum>], t1, t2; 12002 rtx perm[<ssescalarnum>], t1, t2;
11862 int i, base, nelt = <ssescalarnum>, nelt2 = nelt / 2; 12003 int i, base, nelt = <ssescalarnum>, nelt2 = nelt / 2;
11863 12004