Mercurial > hg > CbC > CbC_gcc
diff gcc/config/i386/sse.md @ 63:b7f97abdc517 gcc-4.6-20100522
update gcc from gcc-4.5.0 to gcc-4.6
| author | ryoma <e075725@ie.u-ryukyu.ac.jp> |
|---|---|
| date | Mon, 24 May 2010 12:47:05 +0900 |
| parents | 77e2b8dfacca |
| children | f6334be47118 |
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--- a/gcc/config/i386/sse.md Fri Feb 12 23:41:23 2010 +0900 +++ b/gcc/config/i386/sse.md Mon May 24 12:47:05 2010 +0900 @@ -1,5 +1,5 @@ ;; GCC machine description for SSE instructions -;; Copyright (C) 2005, 2006, 2007, 2008, 2009 +;; Copyright (C) 2005, 2006, 2007, 2008, 2009, 2010 ;; Free Software Foundation, Inc. ;; ;; This file is part of GCC. @@ -194,9 +194,15 @@ return "vmovaps\t{%1, %0|%0, %1}"; case MODE_V4DF: case MODE_V2DF: - return "vmovapd\t{%1, %0|%0, %1}"; + if (TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL) + return "vmovaps\t{%1, %0|%0, %1}"; + else + return "vmovapd\t{%1, %0|%0, %1}"; default: - return "vmovdqa\t{%1, %0|%0, %1}"; + if (TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL) + return "vmovaps\t{%1, %0|%0, %1}"; + else + return "vmovdqa\t{%1, %0|%0, %1}"; } default: gcc_unreachable (); @@ -236,9 +242,15 @@ case MODE_V4SF: return "movaps\t{%1, %0|%0, %1}"; case MODE_V2DF: - return "movapd\t{%1, %0|%0, %1}"; + if (TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL) + return "movaps\t{%1, %0|%0, %1}"; + else + return "movapd\t{%1, %0|%0, %1}"; default: - return "movdqa\t{%1, %0|%0, %1}"; + if (TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL) + return "movaps\t{%1, %0|%0, %1}"; + else + return "movdqa\t{%1, %0|%0, %1}"; } default: gcc_unreachable (); @@ -1015,7 +1027,7 @@ (match_operand:AVXMODEF2P 2 "nonimmediate_operand" "xm")))] "AVX_VEC_FLOAT_MODE_P (<MODE>mode) && flag_finite_math_only && ix86_binary_operator_ok (<CODE>, <MODE>mode, operands)" - "v<maxminfprefix>p<avxmodesuffixf2c>\t{%2, %1, %0|%0, %1, %2}" + "v<maxmin_float>p<avxmodesuffixf2c>\t{%2, %1, %0|%0, %1, %2}" [(set_attr "type" "sseadd") (set_attr "prefix" "vex") (set_attr "mode" "<MODE>")]) @@ -1027,7 +1039,7 @@ (match_operand:SSEMODEF2P 2 "nonimmediate_operand" "xm")))] "SSE_VEC_FLOAT_MODE_P (<MODE>mode) && flag_finite_math_only && ix86_binary_operator_ok (<CODE>, <MODE>mode, operands)" - "<maxminfprefix>p<ssemodesuffixf2c>\t{%2, %0|%0, %2}" + "<maxmin_float>p<ssemodesuffixf2c>\t{%2, %0|%0, %2}" [(set_attr "type" "sseadd") (set_attr "mode" "<MODE>")]) @@ -1037,7 +1049,7 @@ (match_operand:AVXMODEF2P 1 "nonimmediate_operand" "%x") (match_operand:AVXMODEF2P 2 "nonimmediate_operand" "xm")))] "AVX_VEC_FLOAT_MODE_P (<MODE>mode)" - "v<maxminfprefix>p<avxmodesuffixf2c>\t{%2, %1, %0|%0, %1, %2}" + "v<maxmin_float>p<avxmodesuffixf2c>\t{%2, %1, %0|%0, %1, %2}" [(set_attr "type" "sseadd") (set_attr "prefix" "vex") (set_attr "mode" "<avxvecmode>")]) @@ -1048,7 +1060,7 @@ (match_operand:SSEMODEF2P 1 "register_operand" "0") (match_operand:SSEMODEF2P 2 "nonimmediate_operand" "xm")))] "SSE_VEC_FLOAT_MODE_P (<MODE>mode)" - "<maxminfprefix>p<ssemodesuffixf2c>\t{%2, %0|%0, %2}" + "<maxmin_float>p<ssemodesuffixf2c>\t{%2, %0|%0, %2}" [(set_attr "type" "sseadd") (set_attr "mode" "<MODE>")]) @@ -1061,7 +1073,7 @@ (match_dup 1) (const_int 1)))] "AVX128_VEC_FLOAT_MODE_P (<MODE>mode)" - "v<maxminfprefix>s<ssemodesuffixf2c>\t{%2, %1, %0|%0, %1, %2}" + "v<maxmin_float>s<ssemodesuffixf2c>\t{%2, %1, %0|%0, %1, %2}" [(set_attr "type" "sse") (set_attr "prefix" "vex") (set_attr "mode" "<ssescalarmode>")]) @@ -1075,7 +1087,7 @@ (match_dup 1) (const_int 1)))] "SSE_VEC_FLOAT_MODE_P (<MODE>mode)" - "<maxminfprefix>s<ssemodesuffixf2c>\t{%2, %0|%0, %2}" + "<maxmin_float>s<ssemodesuffixf2c>\t{%2, %0|%0, %2}" [(set_attr "type" "sseadd") (set_attr "mode" "<ssescalarmode>")]) @@ -1483,6 +1495,20 @@ (set_attr "length_immediate" "1") (set_attr "mode" "<MODE>")]) +(define_insn "*avx_vmmaskcmp<mode>3" + [(set (match_operand:SSEMODEF2P 0 "register_operand" "=x") + (vec_merge:SSEMODEF2P + (match_operator:SSEMODEF2P 3 "sse_comparison_operator" + [(match_operand:SSEMODEF2P 1 "register_operand" "x") + (match_operand:SSEMODEF2P 2 "nonimmediate_operand" "xm")]) + (match_dup 1) + (const_int 1)))] + "AVX_VEC_FLOAT_MODE_P (<MODE>mode)" + "vcmp%D3s<ssemodesuffixf2c>\t{%2, %1, %0|%0, %1, %2}" + [(set_attr "type" "ssecmp") + (set_attr "prefix" "vex") + (set_attr "mode" "<ssescalarmode>")]) + (define_insn "<sse>_vmmaskcmp<mode>3" [(set (match_operand:SSEMODEF2P 0 "register_operand" "=x") (vec_merge:SSEMODEF2P @@ -1538,14 +1564,15 @@ (set_attr "mode" "<MODE>")]) (define_expand "vcond<mode>" - [(set (match_operand:SSEMODEF2P 0 "register_operand" "") - (if_then_else:SSEMODEF2P + [(set (match_operand:AVXMODEF2P 0 "register_operand" "") + (if_then_else:AVXMODEF2P (match_operator 3 "" - [(match_operand:SSEMODEF2P 4 "nonimmediate_operand" "") - (match_operand:SSEMODEF2P 5 "nonimmediate_operand" "")]) - (match_operand:SSEMODEF2P 1 "general_operand" "") - (match_operand:SSEMODEF2P 2 "general_operand" "")))] - "SSE_VEC_FLOAT_MODE_P (<MODE>mode)" + [(match_operand:AVXMODEF2P 4 "nonimmediate_operand" "") + (match_operand:AVXMODEF2P 5 "nonimmediate_operand" "")]) + (match_operand:AVXMODEF2P 1 "general_operand" "") + (match_operand:AVXMODEF2P 2 "general_operand" "")))] + "(SSE_VEC_FLOAT_MODE_P (<MODE>mode) + || AVX_VEC_FLOAT_MODE_P (<MODE>mode))" { bool ok = ix86_expand_fp_vcond (operands); gcc_assert (ok); @@ -1596,7 +1623,12 @@ (match_operand:AVXMODEF2P 2 "nonimmediate_operand" "xm")))] "AVX_VEC_FLOAT_MODE_P (<MODE>mode) && ix86_binary_operator_ok (<CODE>, <MODE>mode, operands)" - "v<logicprefix>p<avxmodesuffixf2c>\t{%2, %1, %0|%0, %1, %2}" +{ + if (TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL) + return "v<logic>ps\t{%2, %1, %0|%0, %1, %2}"; + else + return "v<logic>p<avxmodesuffixf2c>\t{%2, %1, %0|%0, %1, %2}"; +} [(set_attr "type" "sselog") (set_attr "prefix" "vex") (set_attr "mode" "<avxvecmode>")]) @@ -1616,7 +1648,12 @@ (match_operand:SSEMODEF2P 2 "nonimmediate_operand" "xm")))] "SSE_VEC_FLOAT_MODE_P (<MODE>mode) && ix86_binary_operator_ok (<CODE>, <MODE>mode, operands)" - "<logicprefix>p<ssemodesuffixf2c>\t{%2, %0|%0, %2}" +{ + if (TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL) + return "<logic>ps\t{%2, %0|%0, %2}"; + else + return "<logic>p<ssemodesuffixf2c>\t{%2, %0|%0, %2}"; +} [(set_attr "type" "sselog") (set_attr "mode" "<MODE>")]) @@ -1672,7 +1709,12 @@ (match_operand:MODEF 1 "register_operand" "x") (match_operand:MODEF 2 "register_operand" "x")))] "AVX_FLOAT_MODE_P (<MODE>mode)" - "v<logicprefix>p<ssemodefsuffix>\t{%2, %1, %0|%0, %1, %2}" +{ + if (TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL) + return "v<logic>ps\t{%2, %1, %0|%0, %1, %2}"; + else + return "v<logic>p<ssemodefsuffix>\t{%2, %1, %0|%0, %1, %2}"; +} [(set_attr "type" "sselog") (set_attr "prefix" "vex") (set_attr "mode" "<ssevecmode>")]) @@ -1683,7 +1725,12 @@ (match_operand:MODEF 1 "register_operand" "0") (match_operand:MODEF 2 "register_operand" "x")))] "SSE_FLOAT_MODE_P (<MODE>mode)" - "<logicprefix>p<ssemodefsuffix>\t{%2, %0|%0, %2}" +{ + if (TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL) + return "<logic>ps\t{%2, %0|%0, %2}"; + else + return "<logic>p<ssemodefsuffix>\t{%2, %0|%0, %2}"; +} [(set_attr "type" "sselog") (set_attr "mode" "<ssevecmode>")]) @@ -6030,7 +6077,7 @@ (match_operand:SSEMODE124 1 "nonimmediate_operand" "%x") (match_operand:SSEMODE124 2 "nonimmediate_operand" "xm")))] "TARGET_AVX && ix86_binary_operator_ok (<CODE>, <MODE>mode, operands)" - "vp<maxminiprefix><ssevecsize>\t{%2, %1, %0|%0, %1, %2}" + "vp<maxmin_int><ssevecsize>\t{%2, %1, %0|%0, %1, %2}" [(set_attr "type" "sseiadd") (set (attr "prefix_extra") (if_then_else @@ -6055,7 +6102,7 @@ (match_operand:V16QI 1 "nonimmediate_operand" "%0") (match_operand:V16QI 2 "nonimmediate_operand" "xm")))] "TARGET_SSE2 && ix86_binary_operator_ok (<CODE>, V16QImode, operands)" - "p<maxminiprefix>b\t{%2, %0|%0, %2}" + "p<maxmin_int>b\t{%2, %0|%0, %2}" [(set_attr "type" "sseiadd") (set_attr "prefix_data16" "1") (set_attr "mode" "TI")]) @@ -6074,7 +6121,7 @@ (match_operand:V8HI 1 "nonimmediate_operand" "%0") (match_operand:V8HI 2 "nonimmediate_operand" "xm")))] "TARGET_SSE2 && ix86_binary_operator_ok (<CODE>, V8HImode, operands)" - "p<maxminiprefix>w\t{%2, %0|%0, %2}" + "p<maxmin_int>w\t{%2, %0|%0, %2}" [(set_attr "type" "sseiadd") (set_attr "prefix_data16" "1") (set_attr "mode" "TI")]) @@ -6129,11 +6176,31 @@ (match_operand:SSEMODE14 1 "nonimmediate_operand" "%0") (match_operand:SSEMODE14 2 "nonimmediate_operand" "xm")))] "TARGET_SSE4_1 && ix86_binary_operator_ok (<CODE>, <MODE>mode, operands)" - "p<maxminiprefix><ssevecsize>\t{%2, %0|%0, %2}" + "p<maxmin_int><ssevecsize>\t{%2, %0|%0, %2}" [(set_attr "type" "sseiadd") (set_attr "prefix_extra" "1") (set_attr "mode" "TI")]) +(define_expand "smaxv2di3" + [(set (match_operand:V2DI 0 "register_operand" "") + (smax:V2DI (match_operand:V2DI 1 "register_operand" "") + (match_operand:V2DI 2 "register_operand" "")))] + "TARGET_SSE4_2" +{ + rtx xops[6]; + bool ok; + + xops[0] = operands[0]; + xops[1] = operands[1]; + xops[2] = operands[2]; + xops[3] = gen_rtx_GT (VOIDmode, operands[1], operands[2]); + xops[4] = operands[1]; + xops[5] = operands[2]; + ok = ix86_expand_int_vcond (xops); + gcc_assert (ok); + DONE; +}) + (define_expand "umaxv4si3" [(set (match_operand:V4SI 0 "register_operand" "") (umax:V4SI (match_operand:V4SI 1 "register_operand" "") @@ -6165,11 +6232,31 @@ (match_operand:SSEMODE24 1 "nonimmediate_operand" "%0") (match_operand:SSEMODE24 2 "nonimmediate_operand" "xm")))] "TARGET_SSE4_1 && ix86_binary_operator_ok (<CODE>, <MODE>mode, operands)" - "p<maxminiprefix><ssevecsize>\t{%2, %0|%0, %2}" + "p<maxmin_int><ssevecsize>\t{%2, %0|%0, %2}" [(set_attr "type" "sseiadd") (set_attr "prefix_extra" "1") (set_attr "mode" "TI")]) +(define_expand "umaxv2di3" + [(set (match_operand:V2DI 0 "register_operand" "") + (umax:V2DI (match_operand:V2DI 1 "register_operand" "") + (match_operand:V2DI 2 "register_operand" "")))] + "TARGET_SSE4_2" +{ + rtx xops[6]; + bool ok; + + xops[0] = operands[0]; + xops[1] = operands[1]; + xops[2] = operands[2]; + xops[3] = gen_rtx_GTU (VOIDmode, operands[1], operands[2]); + xops[4] = operands[1]; + xops[5] = operands[2]; + ok = ix86_expand_int_vcond (xops); + gcc_assert (ok); + DONE; +}) + (define_expand "smin<mode>3" [(set (match_operand:SSEMODE14 0 "register_operand" "") (smin:SSEMODE14 (match_operand:SSEMODE14 1 "register_operand" "") @@ -6195,6 +6282,26 @@ } }) +(define_expand "sminv2di3" + [(set (match_operand:V2DI 0 "register_operand" "") + (smin:V2DI (match_operand:V2DI 1 "register_operand" "") + (match_operand:V2DI 2 "register_operand" "")))] + "TARGET_SSE4_2" +{ + rtx xops[6]; + bool ok; + + xops[0] = operands[0]; + xops[1] = operands[2]; + xops[2] = operands[1]; + xops[3] = gen_rtx_GT (VOIDmode, operands[1], operands[2]); + xops[4] = operands[1]; + xops[5] = operands[2]; + ok = ix86_expand_int_vcond (xops); + gcc_assert (ok); + DONE; +}) + (define_expand "umin<mode>3" [(set (match_operand:SSEMODE24 0 "register_operand" "") (umin:SSEMODE24 (match_operand:SSEMODE24 1 "register_operand" "") @@ -6220,6 +6327,26 @@ } }) +(define_expand "uminv2di3" + [(set (match_operand:V2DI 0 "register_operand" "") + (umin:V2DI (match_operand:V2DI 1 "register_operand" "") + (match_operand:V2DI 2 "register_operand" "")))] + "TARGET_SSE4_2" +{ + rtx xops[6]; + bool ok; + + xops[0] = operands[0]; + xops[1] = operands[2]; + xops[2] = operands[1]; + xops[3] = gen_rtx_GTU (VOIDmode, operands[1], operands[2]); + xops[4] = operands[1]; + xops[5] = operands[2]; + ok = ix86_expand_int_vcond (xops); + gcc_assert (ok); + DONE; +}) + ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ;; ;; Parallel integral comparisons @@ -6437,7 +6564,7 @@ (match_operand:AVX256MODEI 2 "nonimmediate_operand" "xm")))] "TARGET_AVX && ix86_binary_operator_ok (<CODE>, <MODE>mode, operands)" - "v<logicprefix>ps\t{%2, %1, %0|%0, %1, %2}" + "v<logic>ps\t{%2, %1, %0|%0, %1, %2}" [(set_attr "type" "sselog") (set_attr "prefix" "vex") (set_attr "mode" "<avxvecpsmode>")]) @@ -6449,7 +6576,7 @@ (match_operand:SSEMODEI 2 "nonimmediate_operand" "xm")))] "(TARGET_SSE && !TARGET_SSE2) && ix86_binary_operator_ok (<CODE>, <MODE>mode, operands)" - "<logicprefix>ps\t{%2, %0|%0, %2}" + "<logic>ps\t{%2, %0|%0, %2}" [(set_attr "type" "sselog") (set_attr "mode" "V4SF")]) @@ -6460,7 +6587,7 @@ (match_operand:SSEMODEI 2 "nonimmediate_operand" "xm")))] "TARGET_AVX && ix86_binary_operator_ok (<CODE>, <MODE>mode, operands)" - "vp<logicprefix>\t{%2, %1, %0|%0, %1, %2}" + "vp<logic>\t{%2, %1, %0|%0, %1, %2}" [(set_attr "type" "sselog") (set_attr "prefix" "vex") (set_attr "mode" "TI")]) @@ -6471,7 +6598,7 @@ (match_operand:SSEMODEI 1 "nonimmediate_operand" "%0") (match_operand:SSEMODEI 2 "nonimmediate_operand" "xm")))] "TARGET_SSE2 && ix86_binary_operator_ok (<CODE>, <MODE>mode, operands)" - "p<logicprefix>\t{%2, %0|%0, %2}" + "p<logic>\t{%2, %0|%0, %2}" [(set_attr "type" "sselog") (set_attr "prefix_data16" "1") (set_attr "mode" "TI")]) @@ -6490,7 +6617,7 @@ (match_operand:TF 1 "nonimmediate_operand" "%0") (match_operand:TF 2 "nonimmediate_operand" "xm")))] "TARGET_SSE2 && ix86_binary_operator_ok (<CODE>, TFmode, operands)" - "p<logicprefix>\t{%2, %0|%0, %2}" + "p<logic>\t{%2, %0|%0, %2}" [(set_attr "type" "sselog") (set_attr "prefix_data16" "1") (set_attr "mode" "TI")]) @@ -10342,7 +10469,7 @@ { operands[3] = CONST0_RTX (V2DImode); } - [(set_attr "type" "ssemuladd") + [(set_attr "type" "ssemul") (set_attr "mode" "TI")]) (define_insn "xop_pmacsdqh" @@ -10404,7 +10531,7 @@ { operands[3] = CONST0_RTX (V2DImode); } - [(set_attr "type" "ssemuladd") + [(set_attr "type" "ssemul") (set_attr "mode" "TI")]) ;; XOP parallel integer multiply/add instructions for the intrinisics @@ -11459,6 +11586,20 @@ (set_attr "length_immediate" "1") (set_attr "mode" "TI")]) +(define_insn "xop_vpermil2<mode>3" + [(set (match_operand:AVXMODEF2P 0 "register_operand" "=x") + (unspec:AVXMODEF2P + [(match_operand:AVXMODEF2P 1 "register_operand" "x") + (match_operand:AVXMODEF2P 2 "nonimmediate_operand" "%x") + (match_operand:<avxpermvecmode> 3 "nonimmediate_operand" "xm") + (match_operand:SI 4 "const_0_to_3_operand" "n")] + UNSPEC_VPERMIL2))] + "TARGET_XOP" + "vpermil2p<avxmodesuffixf2c>\t{%4, %3, %2, %1, %0|%0, %1, %2, %3, %4}" + [(set_attr "type" "sse4arg") + (set_attr "length_immediate" "1") + (set_attr "mode" "<MODE>")]) + ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; (define_insn "*avx_aesenc" [(set (match_operand:V2DI 0 "register_operand" "=x") @@ -11855,7 +11996,7 @@ UNSPEC_VPERMIL2F128))] "TARGET_AVX" { - int mask = INTVAL (operands[2]); + int mask = INTVAL (operands[3]); if ((mask & 0x88) == 0) { rtx perm[<ssescalarnum>], t1, t2;