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comparison gcc/config/rs6000/dfp.md @ 63:b7f97abdc517 gcc-4.6-20100522

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update gcc from gcc-4.5.0 to gcc-4.6
author ryoma <e075725@ie.u-ryukyu.ac.jp>
date Mon, 24 May 2010 12:47:05 +0900
parents 77e2b8dfacca
children 04ced10e8804
comparison
equal deleted inserted replaced
56:3c8a44c06a95 63:b7f97abdc517
1 ;; Decimal Floating Point (DFP) patterns. 1 ;; Decimal Floating Point (DFP) patterns.
2 ;; Copyright (C) 2007, 2008 2 ;; Copyright (C) 2007, 2008, 2010
3 ;; Free Software Foundation, Inc. 3 ;; Free Software Foundation, Inc.
4 ;; Contributed by Ben Elliston (bje@au.ibm.com) and Peter Bergner 4 ;; Contributed by Ben Elliston (bje@au.ibm.com) and Peter Bergner
5 ;; (bergner@vnet.ibm.com). 5 ;; (bergner@vnet.ibm.com).
6 6
7 ;; This file is part of GCC. 7 ;; This file is part of GCC.
291 switch (which_alternative) 291 switch (which_alternative)
292 { 292 {
293 default: 293 default:
294 gcc_unreachable (); 294 gcc_unreachable ();
295 case 0: 295 case 0:
296 /* We normally copy the low-numbered register first. However, if
297 the first register operand 0 is the same as the second register
298 of operand 1, we must copy in the opposite order. */
299 if (REGNO (operands[0]) == REGNO (operands[1]) + 1)
300 return \"mr %L0,%L1\;mr %0,%1\";
301 else
302 return \"mr %0,%1\;mr %L0,%L1\";
303 case 1: 296 case 1:
304 if (rs6000_offsettable_memref_p (operands[1])
305 || (GET_CODE (operands[1]) == MEM
306 && (GET_CODE (XEXP (operands[1], 0)) == LO_SUM
307 || GET_CODE (XEXP (operands[1], 0)) == PRE_INC
308 || GET_CODE (XEXP (operands[1], 0)) == PRE_DEC)))
309 {
310 /* If the low-address word is used in the address, we must load
311 it last. Otherwise, load it first. Note that we cannot have
312 auto-increment in that case since the address register is
313 known to be dead. */
314 if (refers_to_regno_p (REGNO (operands[0]), REGNO (operands[0]) + 1,
315 operands[1], 0))
316 return \"{l|lwz} %L0,%L1\;{l|lwz} %0,%1\";
317 else
318 return \"{l%U1|lwz%U1} %0,%1\;{l|lwz} %L0,%L1\";
319 }
320 else
321 {
322 rtx addreg;
323
324 addreg = find_addr_reg (XEXP (operands[1], 0));
325 if (refers_to_regno_p (REGNO (operands[0]),
326 REGNO (operands[0]) + 1,
327 operands[1], 0))
328 {
329 output_asm_insn (\"{cal|la} %0,4(%0)\", &addreg);
330 output_asm_insn (\"{lx|lwzx} %L0,%1\", operands);
331 output_asm_insn (\"{cal|la} %0,-4(%0)\", &addreg);
332 return \"{lx|lwzx} %0,%1\";
333 }
334 else
335 {
336 output_asm_insn (\"{lx|lwzx} %0,%1\", operands);
337 output_asm_insn (\"{cal|la} %0,4(%0)\", &addreg);
338 output_asm_insn (\"{lx|lwzx} %L0,%1\", operands);
339 output_asm_insn (\"{cal|la} %0,-4(%0)\", &addreg);
340 return \"\";
341 }
342 }
343 case 2: 297 case 2:
344 if (rs6000_offsettable_memref_p (operands[0]) 298 return \"#\";
345 || (GET_CODE (operands[0]) == MEM
346 && (GET_CODE (XEXP (operands[0], 0)) == LO_SUM
347 || GET_CODE (XEXP (operands[0], 0)) == PRE_INC
348 || GET_CODE (XEXP (operands[0], 0)) == PRE_DEC)))
349 return \"{st%U0|stw%U0} %1,%0\;{st|stw} %L1,%L0\";
350 else
351 {
352 rtx addreg;
353
354 addreg = find_addr_reg (XEXP (operands[0], 0));
355 output_asm_insn (\"{stx|stwx} %1,%0\", operands);
356 output_asm_insn (\"{cal|la} %0,4(%0)\", &addreg);
357 output_asm_insn (\"{stx|stwx} %L1,%0\", operands);
358 output_asm_insn (\"{cal|la} %0,-4(%0)\", &addreg);
359 return \"\";
360 }
361 case 3: 299 case 3:
362 return \"fmr %0,%1\"; 300 return \"fmr %0,%1\";
363 case 4: 301 case 4:
364 return \"lfd%U1%X1 %0,%1\"; 302 return \"lfd%U1%X1 %0,%1\";
365 case 5: 303 case 5:
377 [(set (match_operand:DD 0 "nonimmediate_operand" "=r,r,m,r,r,r") 315 [(set (match_operand:DD 0 "nonimmediate_operand" "=r,r,m,r,r,r")
378 (match_operand:DD 1 "input_operand" "r,m,r,G,H,F"))] 316 (match_operand:DD 1 "input_operand" "r,m,r,G,H,F"))]
379 "! TARGET_POWERPC64 && (TARGET_SOFT_FLOAT || !TARGET_FPRS) 317 "! TARGET_POWERPC64 && (TARGET_SOFT_FLOAT || !TARGET_FPRS)
380 && (gpc_reg_operand (operands[0], DDmode) 318 && (gpc_reg_operand (operands[0], DDmode)
381 || gpc_reg_operand (operands[1], DDmode))" 319 || gpc_reg_operand (operands[1], DDmode))"
382 "* 320 "#"
383 {
384 switch (which_alternative)
385 {
386 default:
387 gcc_unreachable ();
388 case 0:
389 /* We normally copy the low-numbered register first. However, if
390 the first register operand 0 is the same as the second register of
391 operand 1, we must copy in the opposite order. */
392 if (REGNO (operands[0]) == REGNO (operands[1]) + 1)
393 return \"mr %L0,%L1\;mr %0,%1\";
394 else
395 return \"mr %0,%1\;mr %L0,%L1\";
396 case 1:
397 /* If the low-address word is used in the address, we must load
398 it last. Otherwise, load it first. Note that we cannot have
399 auto-increment in that case since the address register is
400 known to be dead. */
401 if (refers_to_regno_p (REGNO (operands[0]), REGNO (operands[0]) + 1,
402 operands[1], 0))
403 return \"{l|lwz} %L0,%L1\;{l|lwz} %0,%1\";
404 else
405 return \"{l%U1|lwz%U1} %0,%1\;{l|lwz} %L0,%L1\";
406 case 2:
407 return \"{st%U0|stw%U0} %1,%0\;{st|stw} %L1,%L0\";
408 case 3:
409 case 4:
410 case 5:
411 return \"#\";
412 }
413 }"
414 [(set_attr "type" "two,load,store,*,*,*") 321 [(set_attr "type" "two,load,store,*,*,*")
415 (set_attr "length" "8,8,8,8,12,16")]) 322 (set_attr "length" "8,8,8,8,12,16")])
416 323
417 ; ld/std require word-aligned displacements -> 'Y' constraint. 324 ; ld/std require word-aligned displacements -> 'Y' constraint.
418 ; List Y->r and r->Y before r->r for reload. 325 ; List Y->r and r->Y before r->r for reload.