Mercurial > hg > CbC > CbC_gcc
annotate gcc/config/rs6000/dfp.md @ 63:b7f97abdc517 gcc-4.6-20100522
update gcc from gcc-4.5.0 to gcc-4.6
| author | ryoma <e075725@ie.u-ryukyu.ac.jp> |
|---|---|
| date | Mon, 24 May 2010 12:47:05 +0900 |
| parents | 77e2b8dfacca |
| children | 04ced10e8804 |
| rev | line source |
|---|---|
| 0 | 1 ;; Decimal Floating Point (DFP) patterns. |
|
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update gcc from gcc-4.5.0 to gcc-4.6
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parents:
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|
2 ;; Copyright (C) 2007, 2008, 2010 |
| 0 | 3 ;; Free Software Foundation, Inc. |
| 4 ;; Contributed by Ben Elliston (bje@au.ibm.com) and Peter Bergner | |
| 5 ;; (bergner@vnet.ibm.com). | |
| 6 | |
| 7 ;; This file is part of GCC. | |
| 8 | |
| 9 ;; GCC is free software; you can redistribute it and/or modify it | |
| 10 ;; under the terms of the GNU General Public License as published | |
| 11 ;; by the Free Software Foundation; either version 3, or (at your | |
| 12 ;; option) any later version. | |
| 13 | |
| 14 ;; GCC is distributed in the hope that it will be useful, but WITHOUT | |
| 15 ;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY | |
| 16 ;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public | |
| 17 ;; License for more details. | |
| 18 | |
| 19 ;; You should have received a copy of the GNU General Public License | |
| 20 ;; along with GCC; see the file COPYING3. If not see | |
| 21 ;; <http://www.gnu.org/licenses/>. | |
| 22 | |
| 23 ;; | |
| 24 ;; UNSPEC usage | |
| 25 ;; | |
| 26 | |
| 27 (define_constants | |
| 28 [(UNSPEC_MOVSD_LOAD 400) | |
| 29 (UNSPEC_MOVSD_STORE 401) | |
| 30 ]) | |
| 31 | |
| 32 | |
| 33 (define_expand "movsd" | |
| 34 [(set (match_operand:SD 0 "nonimmediate_operand" "") | |
| 35 (match_operand:SD 1 "any_operand" ""))] | |
| 36 "TARGET_HARD_FLOAT && TARGET_FPRS" | |
| 37 "{ rs6000_emit_move (operands[0], operands[1], SDmode); DONE; }") | |
| 38 | |
| 39 (define_split | |
| 40 [(set (match_operand:SD 0 "gpc_reg_operand" "") | |
| 41 (match_operand:SD 1 "const_double_operand" ""))] | |
| 42 "reload_completed | |
| 43 && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31) | |
| 44 || (GET_CODE (operands[0]) == SUBREG | |
| 45 && GET_CODE (SUBREG_REG (operands[0])) == REG | |
| 46 && REGNO (SUBREG_REG (operands[0])) <= 31))" | |
| 47 [(set (match_dup 2) (match_dup 3))] | |
| 48 " | |
| 49 { | |
| 50 long l; | |
| 51 REAL_VALUE_TYPE rv; | |
| 52 | |
| 53 REAL_VALUE_FROM_CONST_DOUBLE (rv, operands[1]); | |
| 54 REAL_VALUE_TO_TARGET_DECIMAL32 (rv, l); | |
| 55 | |
| 56 if (! TARGET_POWERPC64) | |
| 57 operands[2] = operand_subword (operands[0], 0, 0, SDmode); | |
| 58 else | |
| 59 operands[2] = gen_lowpart (SImode, operands[0]); | |
| 60 | |
| 61 operands[3] = gen_int_mode (l, SImode); | |
| 62 }") | |
| 63 | |
| 64 (define_insn "movsd_hardfloat" | |
| 65 [(set (match_operand:SD 0 "nonimmediate_operand" "=r,r,m,f,*c*l,*q,!r,*h,!r,!r") | |
| 66 (match_operand:SD 1 "input_operand" "r,m,r,f,r,r,h,0,G,Fn"))] | |
| 67 "(gpc_reg_operand (operands[0], SDmode) | |
| 68 || gpc_reg_operand (operands[1], SDmode)) | |
| 69 && (TARGET_HARD_FLOAT && TARGET_FPRS)" | |
| 70 "@ | |
| 71 mr %0,%1 | |
| 72 {l%U1%X1|lwz%U1%X1} %0,%1 | |
| 73 {st%U0%X0|stw%U0%X0} %1,%0 | |
| 74 fmr %0,%1 | |
| 75 mt%0 %1 | |
| 76 mt%0 %1 | |
| 77 mf%1 %0 | |
| 78 {cror 0,0,0|nop} | |
| 79 # | |
| 80 #" | |
| 81 [(set_attr "type" "*,load,store,fp,mtjmpr,*,mfjmpr,*,*,*") | |
| 82 (set_attr "length" "4,4,4,4,4,4,4,4,4,8")]) | |
| 83 | |
| 84 (define_insn "movsd_softfloat" | |
| 85 [(set (match_operand:SD 0 "nonimmediate_operand" "=r,cl,q,r,r,m,r,r,r,r,r,*h") | |
| 86 (match_operand:SD 1 "input_operand" "r,r,r,h,m,r,I,L,R,G,Fn,0"))] | |
| 87 "(gpc_reg_operand (operands[0], SDmode) | |
| 88 || gpc_reg_operand (operands[1], SDmode)) | |
| 89 && (TARGET_SOFT_FLOAT || !TARGET_FPRS)" | |
| 90 "@ | |
| 91 mr %0,%1 | |
| 92 mt%0 %1 | |
| 93 mt%0 %1 | |
| 94 mf%1 %0 | |
| 95 {l%U1%X1|lwz%U1%X1} %0,%1 | |
| 96 {st%U0%X0|stw%U0%X0} %1,%0 | |
| 97 {lil|li} %0,%1 | |
| 98 {liu|lis} %0,%v1 | |
| 99 {cal|la} %0,%a1 | |
| 100 # | |
| 101 # | |
| 102 {cror 0,0,0|nop}" | |
| 103 [(set_attr "type" "*,mtjmpr,*,mfjmpr,load,store,*,*,*,*,*,*") | |
| 104 (set_attr "length" "4,4,4,4,4,4,4,4,4,4,8,4")]) | |
| 105 | |
| 106 (define_insn "movsd_store" | |
| 107 [(set (match_operand:DD 0 "nonimmediate_operand" "=m") | |
|
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parents:
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108 (unspec:DD [(match_operand:SD 1 "input_operand" "d")] |
| 0 | 109 UNSPEC_MOVSD_STORE))] |
| 110 "(gpc_reg_operand (operands[0], DDmode) | |
| 111 || gpc_reg_operand (operands[1], SDmode)) | |
| 112 && TARGET_HARD_FLOAT && TARGET_FPRS" | |
| 113 "stfd%U0%X0 %1,%0" | |
| 114 [(set_attr "type" "fpstore") | |
| 115 (set_attr "length" "4")]) | |
| 116 | |
| 117 (define_insn "movsd_load" | |
| 118 [(set (match_operand:SD 0 "nonimmediate_operand" "=f") | |
| 119 (unspec:SD [(match_operand:DD 1 "input_operand" "m")] | |
| 120 UNSPEC_MOVSD_LOAD))] | |
| 121 "(gpc_reg_operand (operands[0], SDmode) | |
| 122 || gpc_reg_operand (operands[1], DDmode)) | |
| 123 && TARGET_HARD_FLOAT && TARGET_FPRS" | |
| 124 "lfd%U1%X1 %0,%1" | |
| 125 [(set_attr "type" "fpload") | |
| 126 (set_attr "length" "4")]) | |
| 127 | |
| 128 ;; Hardware support for decimal floating point operations. | |
| 129 | |
| 130 (define_insn "extendsddd2" | |
|
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131 [(set (match_operand:DD 0 "gpc_reg_operand" "=d") |
| 0 | 132 (float_extend:DD (match_operand:SD 1 "gpc_reg_operand" "f")))] |
| 133 "TARGET_DFP" | |
| 134 "dctdp %0,%1" | |
| 135 [(set_attr "type" "fp")]) | |
| 136 | |
| 137 (define_expand "extendsdtd2" | |
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138 [(set (match_operand:TD 0 "gpc_reg_operand" "=d") |
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77e2b8dfacca
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parents:
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139 (float_extend:TD (match_operand:SD 1 "gpc_reg_operand" "d")))] |
| 0 | 140 "TARGET_DFP" |
| 141 { | |
| 142 rtx tmp = gen_reg_rtx (DDmode); | |
| 143 emit_insn (gen_extendsddd2 (tmp, operands[1])); | |
| 144 emit_insn (gen_extendddtd2 (operands[0], tmp)); | |
| 145 DONE; | |
| 146 }) | |
| 147 | |
| 148 (define_insn "truncddsd2" | |
| 149 [(set (match_operand:SD 0 "gpc_reg_operand" "=f") | |
|
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150 (float_truncate:SD (match_operand:DD 1 "gpc_reg_operand" "d")))] |
| 0 | 151 "TARGET_DFP" |
| 152 "drsp %0,%1" | |
| 153 [(set_attr "type" "fp")]) | |
| 154 | |
| 155 (define_expand "negdd2" | |
| 156 [(set (match_operand:DD 0 "gpc_reg_operand" "") | |
| 157 (neg:DD (match_operand:DD 1 "gpc_reg_operand" "")))] | |
| 158 "TARGET_HARD_FLOAT && TARGET_FPRS" | |
| 159 "") | |
| 160 | |
| 161 (define_insn "*negdd2_fpr" | |
|
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162 [(set (match_operand:DD 0 "gpc_reg_operand" "=d") |
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163 (neg:DD (match_operand:DD 1 "gpc_reg_operand" "d")))] |
| 0 | 164 "TARGET_HARD_FLOAT && TARGET_FPRS" |
| 165 "fneg %0,%1" | |
| 166 [(set_attr "type" "fp")]) | |
| 167 | |
| 168 (define_expand "absdd2" | |
| 169 [(set (match_operand:DD 0 "gpc_reg_operand" "") | |
| 170 (abs:DD (match_operand:DD 1 "gpc_reg_operand" "")))] | |
| 171 "TARGET_HARD_FLOAT && TARGET_FPRS" | |
| 172 "") | |
| 173 | |
| 174 (define_insn "*absdd2_fpr" | |
|
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175 [(set (match_operand:DD 0 "gpc_reg_operand" "=d") |
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176 (abs:DD (match_operand:DD 1 "gpc_reg_operand" "d")))] |
| 0 | 177 "TARGET_HARD_FLOAT && TARGET_FPRS" |
| 178 "fabs %0,%1" | |
| 179 [(set_attr "type" "fp")]) | |
| 180 | |
| 181 (define_insn "*nabsdd2_fpr" | |
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182 [(set (match_operand:DD 0 "gpc_reg_operand" "=d") |
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77e2b8dfacca
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parents:
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183 (neg:DD (abs:DD (match_operand:DD 1 "gpc_reg_operand" "d"))))] |
| 0 | 184 "TARGET_HARD_FLOAT && TARGET_FPRS" |
| 185 "fnabs %0,%1" | |
| 186 [(set_attr "type" "fp")]) | |
| 187 | |
| 188 (define_expand "movdd" | |
| 189 [(set (match_operand:DD 0 "nonimmediate_operand" "") | |
| 190 (match_operand:DD 1 "any_operand" ""))] | |
| 191 "" | |
| 192 "{ rs6000_emit_move (operands[0], operands[1], DDmode); DONE; }") | |
| 193 | |
| 194 (define_split | |
| 195 [(set (match_operand:DD 0 "gpc_reg_operand" "") | |
| 196 (match_operand:DD 1 "const_int_operand" ""))] | |
| 197 "! TARGET_POWERPC64 && reload_completed | |
| 198 && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31) | |
| 199 || (GET_CODE (operands[0]) == SUBREG | |
| 200 && GET_CODE (SUBREG_REG (operands[0])) == REG | |
| 201 && REGNO (SUBREG_REG (operands[0])) <= 31))" | |
| 202 [(set (match_dup 2) (match_dup 4)) | |
| 203 (set (match_dup 3) (match_dup 1))] | |
| 204 " | |
| 205 { | |
| 206 int endian = (WORDS_BIG_ENDIAN == 0); | |
| 207 HOST_WIDE_INT value = INTVAL (operands[1]); | |
| 208 | |
| 209 operands[2] = operand_subword (operands[0], endian, 0, DDmode); | |
| 210 operands[3] = operand_subword (operands[0], 1 - endian, 0, DDmode); | |
| 211 #if HOST_BITS_PER_WIDE_INT == 32 | |
| 212 operands[4] = (value & 0x80000000) ? constm1_rtx : const0_rtx; | |
| 213 #else | |
| 214 operands[4] = GEN_INT (value >> 32); | |
| 215 operands[1] = GEN_INT (((value & 0xffffffff) ^ 0x80000000) - 0x80000000); | |
| 216 #endif | |
| 217 }") | |
| 218 | |
| 219 (define_split | |
| 220 [(set (match_operand:DD 0 "gpc_reg_operand" "") | |
| 221 (match_operand:DD 1 "const_double_operand" ""))] | |
| 222 "! TARGET_POWERPC64 && reload_completed | |
| 223 && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31) | |
| 224 || (GET_CODE (operands[0]) == SUBREG | |
| 225 && GET_CODE (SUBREG_REG (operands[0])) == REG | |
| 226 && REGNO (SUBREG_REG (operands[0])) <= 31))" | |
| 227 [(set (match_dup 2) (match_dup 4)) | |
| 228 (set (match_dup 3) (match_dup 5))] | |
| 229 " | |
| 230 { | |
| 231 int endian = (WORDS_BIG_ENDIAN == 0); | |
| 232 long l[2]; | |
| 233 REAL_VALUE_TYPE rv; | |
| 234 | |
| 235 REAL_VALUE_FROM_CONST_DOUBLE (rv, operands[1]); | |
| 236 REAL_VALUE_TO_TARGET_DECIMAL64 (rv, l); | |
| 237 | |
| 238 operands[2] = operand_subword (operands[0], endian, 0, DDmode); | |
| 239 operands[3] = operand_subword (operands[0], 1 - endian, 0, DDmode); | |
| 240 operands[4] = gen_int_mode (l[endian], SImode); | |
| 241 operands[5] = gen_int_mode (l[1 - endian], SImode); | |
| 242 }") | |
| 243 | |
| 244 (define_split | |
| 245 [(set (match_operand:DD 0 "gpc_reg_operand" "") | |
| 246 (match_operand:DD 1 "const_double_operand" ""))] | |
| 247 "TARGET_POWERPC64 && reload_completed | |
| 248 && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31) | |
| 249 || (GET_CODE (operands[0]) == SUBREG | |
| 250 && GET_CODE (SUBREG_REG (operands[0])) == REG | |
| 251 && REGNO (SUBREG_REG (operands[0])) <= 31))" | |
| 252 [(set (match_dup 2) (match_dup 3))] | |
| 253 " | |
| 254 { | |
| 255 int endian = (WORDS_BIG_ENDIAN == 0); | |
| 256 long l[2]; | |
| 257 REAL_VALUE_TYPE rv; | |
| 258 #if HOST_BITS_PER_WIDE_INT >= 64 | |
| 259 HOST_WIDE_INT val; | |
| 260 #endif | |
| 261 | |
| 262 REAL_VALUE_FROM_CONST_DOUBLE (rv, operands[1]); | |
| 263 REAL_VALUE_TO_TARGET_DECIMAL64 (rv, l); | |
| 264 | |
| 265 operands[2] = gen_lowpart (DImode, operands[0]); | |
| 266 /* HIGHPART is lower memory address when WORDS_BIG_ENDIAN. */ | |
| 267 #if HOST_BITS_PER_WIDE_INT >= 64 | |
| 268 val = ((HOST_WIDE_INT)(unsigned long)l[endian] << 32 | |
| 269 | ((HOST_WIDE_INT)(unsigned long)l[1 - endian])); | |
| 270 | |
| 271 operands[3] = gen_int_mode (val, DImode); | |
| 272 #else | |
| 273 operands[3] = immed_double_const (l[1 - endian], l[endian], DImode); | |
| 274 #endif | |
| 275 }") | |
| 276 | |
| 277 ;; Don't have reload use general registers to load a constant. First, | |
| 278 ;; it might not work if the output operand is the equivalent of | |
| 279 ;; a non-offsettable memref, but also it is less efficient than loading | |
| 280 ;; the constant into an FP register, since it will probably be used there. | |
| 281 ;; The "??" is a kludge until we can figure out a more reasonable way | |
| 282 ;; of handling these non-offsettable values. | |
| 283 (define_insn "*movdd_hardfloat32" | |
|
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284 [(set (match_operand:DD 0 "nonimmediate_operand" "=!r,??r,m,d,d,m,!r,!r,!r") |
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285 (match_operand:DD 1 "input_operand" "r,m,r,d,m,d,G,H,F"))] |
| 0 | 286 "! TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS |
| 287 && (gpc_reg_operand (operands[0], DDmode) | |
| 288 || gpc_reg_operand (operands[1], DDmode))" | |
| 289 "* | |
| 290 { | |
| 291 switch (which_alternative) | |
| 292 { | |
| 293 default: | |
| 294 gcc_unreachable (); | |
| 295 case 0: | |
| 296 case 1: | |
| 297 case 2: | |
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298 return \"#\"; |
| 0 | 299 case 3: |
| 300 return \"fmr %0,%1\"; | |
| 301 case 4: | |
| 302 return \"lfd%U1%X1 %0,%1\"; | |
| 303 case 5: | |
| 304 return \"stfd%U0%X0 %1,%0\"; | |
| 305 case 6: | |
| 306 case 7: | |
| 307 case 8: | |
| 308 return \"#\"; | |
| 309 } | |
| 310 }" | |
| 311 [(set_attr "type" "two,load,store,fp,fpload,fpstore,*,*,*") | |
| 312 (set_attr "length" "8,16,16,4,4,4,8,12,16")]) | |
| 313 | |
| 314 (define_insn "*movdd_softfloat32" | |
| 315 [(set (match_operand:DD 0 "nonimmediate_operand" "=r,r,m,r,r,r") | |
| 316 (match_operand:DD 1 "input_operand" "r,m,r,G,H,F"))] | |
| 317 "! TARGET_POWERPC64 && (TARGET_SOFT_FLOAT || !TARGET_FPRS) | |
| 318 && (gpc_reg_operand (operands[0], DDmode) | |
| 319 || gpc_reg_operand (operands[1], DDmode))" | |
|
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320 "#" |
| 0 | 321 [(set_attr "type" "two,load,store,*,*,*") |
| 322 (set_attr "length" "8,8,8,8,12,16")]) | |
| 323 | |
| 324 ; ld/std require word-aligned displacements -> 'Y' constraint. | |
| 325 ; List Y->r and r->Y before r->r for reload. | |
| 326 (define_insn "*movdd_hardfloat64_mfpgpr" | |
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327 [(set (match_operand:DD 0 "nonimmediate_operand" "=Y,r,!r,d,d,m,*c*l,!r,*h,!r,!r,!r,r,d") |
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328 (match_operand:DD 1 "input_operand" "r,Y,r,d,m,d,r,h,0,G,H,F,d,r"))] |
| 0 | 329 "TARGET_POWERPC64 && TARGET_MFPGPR && TARGET_HARD_FLOAT && TARGET_FPRS |
| 330 && (gpc_reg_operand (operands[0], DDmode) | |
| 331 || gpc_reg_operand (operands[1], DDmode))" | |
| 332 "@ | |
| 333 std%U0%X0 %1,%0 | |
| 334 ld%U1%X1 %0,%1 | |
| 335 mr %0,%1 | |
| 336 fmr %0,%1 | |
| 337 lfd%U1%X1 %0,%1 | |
| 338 stfd%U0%X0 %1,%0 | |
| 339 mt%0 %1 | |
| 340 mf%1 %0 | |
| 341 {cror 0,0,0|nop} | |
| 342 # | |
| 343 # | |
| 344 # | |
| 345 mftgpr %0,%1 | |
| 346 mffgpr %0,%1" | |
| 347 [(set_attr "type" "store,load,*,fp,fpload,fpstore,mtjmpr,mfjmpr,*,*,*,*,mftgpr,mffgpr") | |
| 348 (set_attr "length" "4,4,4,4,4,4,4,4,4,8,12,16,4,4")]) | |
| 349 | |
| 350 ; ld/std require word-aligned displacements -> 'Y' constraint. | |
| 351 ; List Y->r and r->Y before r->r for reload. | |
| 352 (define_insn "*movdd_hardfloat64" | |
|
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353 [(set (match_operand:DD 0 "nonimmediate_operand" "=Y,r,!r,d,d,m,*c*l,!r,*h,!r,!r,!r") |
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77e2b8dfacca
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354 (match_operand:DD 1 "input_operand" "r,Y,r,d,m,d,r,h,0,G,H,F"))] |
| 0 | 355 "TARGET_POWERPC64 && !TARGET_MFPGPR && TARGET_HARD_FLOAT && TARGET_FPRS |
| 356 && (gpc_reg_operand (operands[0], DDmode) | |
| 357 || gpc_reg_operand (operands[1], DDmode))" | |
| 358 "@ | |
| 359 std%U0%X0 %1,%0 | |
| 360 ld%U1%X1 %0,%1 | |
| 361 mr %0,%1 | |
| 362 fmr %0,%1 | |
| 363 lfd%U1%X1 %0,%1 | |
| 364 stfd%U0%X0 %1,%0 | |
| 365 mt%0 %1 | |
| 366 mf%1 %0 | |
| 367 {cror 0,0,0|nop} | |
| 368 # | |
| 369 # | |
| 370 #" | |
| 371 [(set_attr "type" "store,load,*,fp,fpload,fpstore,mtjmpr,mfjmpr,*,*,*,*") | |
| 372 (set_attr "length" "4,4,4,4,4,4,4,4,4,8,12,16")]) | |
| 373 | |
| 374 (define_insn "*movdd_softfloat64" | |
| 375 [(set (match_operand:DD 0 "nonimmediate_operand" "=r,Y,r,cl,r,r,r,r,*h") | |
| 376 (match_operand:DD 1 "input_operand" "Y,r,r,r,h,G,H,F,0"))] | |
| 377 "TARGET_POWERPC64 && (TARGET_SOFT_FLOAT || !TARGET_FPRS) | |
| 378 && (gpc_reg_operand (operands[0], DDmode) | |
| 379 || gpc_reg_operand (operands[1], DDmode))" | |
| 380 "@ | |
| 381 ld%U1%X1 %0,%1 | |
| 382 std%U0%X0 %1,%0 | |
| 383 mr %0,%1 | |
| 384 mt%0 %1 | |
| 385 mf%1 %0 | |
| 386 # | |
| 387 # | |
| 388 # | |
| 389 {cror 0,0,0|nop}" | |
| 390 [(set_attr "type" "load,store,*,mtjmpr,mfjmpr,*,*,*,*") | |
| 391 (set_attr "length" "4,4,4,4,4,8,12,16,4")]) | |
| 392 | |
| 393 (define_expand "negtd2" | |
| 394 [(set (match_operand:TD 0 "gpc_reg_operand" "") | |
| 395 (neg:TD (match_operand:TD 1 "gpc_reg_operand" "")))] | |
| 396 "TARGET_HARD_FLOAT && TARGET_FPRS" | |
| 397 "") | |
| 398 | |
| 399 (define_insn "*negtd2_fpr" | |
|
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400 [(set (match_operand:TD 0 "gpc_reg_operand" "=d") |
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401 (neg:TD (match_operand:TD 1 "gpc_reg_operand" "d")))] |
| 0 | 402 "TARGET_HARD_FLOAT && TARGET_FPRS" |
| 403 "fneg %0,%1" | |
| 404 [(set_attr "type" "fp")]) | |
| 405 | |
| 406 (define_expand "abstd2" | |
| 407 [(set (match_operand:TD 0 "gpc_reg_operand" "") | |
| 408 (abs:TD (match_operand:TD 1 "gpc_reg_operand" "")))] | |
| 409 "TARGET_HARD_FLOAT && TARGET_FPRS" | |
| 410 "") | |
| 411 | |
| 412 (define_insn "*abstd2_fpr" | |
|
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413 [(set (match_operand:TD 0 "gpc_reg_operand" "=d") |
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414 (abs:TD (match_operand:TD 1 "gpc_reg_operand" "d")))] |
| 0 | 415 "TARGET_HARD_FLOAT && TARGET_FPRS" |
| 416 "fabs %0,%1" | |
| 417 [(set_attr "type" "fp")]) | |
| 418 | |
| 419 (define_insn "*nabstd2_fpr" | |
|
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420 [(set (match_operand:TD 0 "gpc_reg_operand" "=d") |
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421 (neg:TD (abs:TD (match_operand:TD 1 "gpc_reg_operand" "d"))))] |
| 0 | 422 "TARGET_HARD_FLOAT && TARGET_FPRS" |
| 423 "fnabs %0,%1" | |
| 424 [(set_attr "type" "fp")]) | |
| 425 | |
| 426 (define_expand "movtd" | |
| 427 [(set (match_operand:TD 0 "general_operand" "") | |
| 428 (match_operand:TD 1 "any_operand" ""))] | |
| 429 "TARGET_HARD_FLOAT && TARGET_FPRS" | |
| 430 "{ rs6000_emit_move (operands[0], operands[1], TDmode); DONE; }") | |
| 431 | |
| 432 ; It's important to list the o->f and f->o moves before f->f because | |
| 433 ; otherwise reload, given m->f, will try to pick f->f and reload it, | |
| 434 ; which doesn't make progress. Likewise r->Y must be before r->r. | |
| 435 (define_insn_and_split "*movtd_internal" | |
|
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436 [(set (match_operand:TD 0 "nonimmediate_operand" "=o,d,d,r,Y,r") |
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437 (match_operand:TD 1 "input_operand" "d,o,d,YGHF,r,r"))] |
| 0 | 438 "TARGET_HARD_FLOAT && TARGET_FPRS |
| 439 && (gpc_reg_operand (operands[0], TDmode) | |
| 440 || gpc_reg_operand (operands[1], TDmode))" | |
| 441 "#" | |
| 442 "&& reload_completed" | |
| 443 [(pc)] | |
| 444 { rs6000_split_multireg_move (operands[0], operands[1]); DONE; } | |
| 445 [(set_attr "length" "8,8,8,20,20,16")]) | |
| 446 | |
| 447 ;; Hardware support for decimal floating point operations. | |
| 448 | |
| 449 (define_insn "extendddtd2" | |
|
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450 [(set (match_operand:TD 0 "gpc_reg_operand" "=d") |
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451 (float_extend:TD (match_operand:DD 1 "gpc_reg_operand" "d")))] |
| 0 | 452 "TARGET_DFP" |
| 453 "dctqpq %0,%1" | |
| 454 [(set_attr "type" "fp")]) | |
| 455 | |
| 456 ;; The result of drdpq is an even/odd register pair with the converted | |
| 457 ;; value in the even register and zero in the odd register. | |
| 458 ;; FIXME: Avoid the register move by using a reload constraint to ensure | |
| 459 ;; that the result is the first of the pair receiving the result of drdpq. | |
| 460 | |
| 461 (define_insn "trunctddd2" | |
|
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462 [(set (match_operand:DD 0 "gpc_reg_operand" "=d") |
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463 (float_truncate:DD (match_operand:TD 1 "gpc_reg_operand" "d"))) |
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464 (clobber (match_scratch:TD 2 "=d"))] |
| 0 | 465 "TARGET_DFP" |
| 466 "drdpq %2,%1\;fmr %0,%2" | |
| 467 [(set_attr "type" "fp")]) | |
| 468 | |
| 469 (define_insn "adddd3" | |
|
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470 [(set (match_operand:DD 0 "gpc_reg_operand" "=d") |
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471 (plus:DD (match_operand:DD 1 "gpc_reg_operand" "%d") |
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472 (match_operand:DD 2 "gpc_reg_operand" "d")))] |
| 0 | 473 "TARGET_DFP" |
| 474 "dadd %0,%1,%2" | |
| 475 [(set_attr "type" "fp")]) | |
| 476 | |
| 477 (define_insn "addtd3" | |
|
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478 [(set (match_operand:TD 0 "gpc_reg_operand" "=d") |
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479 (plus:TD (match_operand:TD 1 "gpc_reg_operand" "%d") |
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480 (match_operand:TD 2 "gpc_reg_operand" "d")))] |
| 0 | 481 "TARGET_DFP" |
| 482 "daddq %0,%1,%2" | |
| 483 [(set_attr "type" "fp")]) | |
| 484 | |
| 485 (define_insn "subdd3" | |
|
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486 [(set (match_operand:DD 0 "gpc_reg_operand" "=d") |
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487 (minus:DD (match_operand:DD 1 "gpc_reg_operand" "d") |
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488 (match_operand:DD 2 "gpc_reg_operand" "d")))] |
| 0 | 489 "TARGET_DFP" |
| 490 "dsub %0,%1,%2" | |
| 491 [(set_attr "type" "fp")]) | |
| 492 | |
| 493 (define_insn "subtd3" | |
|
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494 [(set (match_operand:TD 0 "gpc_reg_operand" "=d") |
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495 (minus:TD (match_operand:TD 1 "gpc_reg_operand" "d") |
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496 (match_operand:TD 2 "gpc_reg_operand" "d")))] |
| 0 | 497 "TARGET_DFP" |
| 498 "dsubq %0,%1,%2" | |
| 499 [(set_attr "type" "fp")]) | |
| 500 | |
| 501 (define_insn "muldd3" | |
|
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502 [(set (match_operand:DD 0 "gpc_reg_operand" "=d") |
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503 (mult:DD (match_operand:DD 1 "gpc_reg_operand" "%d") |
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504 (match_operand:DD 2 "gpc_reg_operand" "d")))] |
| 0 | 505 "TARGET_DFP" |
| 506 "dmul %0,%1,%2" | |
| 507 [(set_attr "type" "fp")]) | |
| 508 | |
| 509 (define_insn "multd3" | |
|
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510 [(set (match_operand:TD 0 "gpc_reg_operand" "=d") |
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511 (mult:TD (match_operand:TD 1 "gpc_reg_operand" "%d") |
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512 (match_operand:TD 2 "gpc_reg_operand" "d")))] |
| 0 | 513 "TARGET_DFP" |
| 514 "dmulq %0,%1,%2" | |
| 515 [(set_attr "type" "fp")]) | |
| 516 | |
| 517 (define_insn "divdd3" | |
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518 [(set (match_operand:DD 0 "gpc_reg_operand" "=d") |
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519 (div:DD (match_operand:DD 1 "gpc_reg_operand" "d") |
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520 (match_operand:DD 2 "gpc_reg_operand" "d")))] |
| 0 | 521 "TARGET_DFP" |
| 522 "ddiv %0,%1,%2" | |
| 523 [(set_attr "type" "fp")]) | |
| 524 | |
| 525 (define_insn "divtd3" | |
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526 [(set (match_operand:TD 0 "gpc_reg_operand" "=d") |
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527 (div:TD (match_operand:TD 1 "gpc_reg_operand" "d") |
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528 (match_operand:TD 2 "gpc_reg_operand" "d")))] |
| 0 | 529 "TARGET_DFP" |
| 530 "ddivq %0,%1,%2" | |
| 531 [(set_attr "type" "fp")]) | |
| 532 | |
| 533 (define_insn "*cmpdd_internal1" | |
| 534 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y") | |
|
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535 (compare:CCFP (match_operand:DD 1 "gpc_reg_operand" "d") |
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536 (match_operand:DD 2 "gpc_reg_operand" "d")))] |
| 0 | 537 "TARGET_DFP" |
| 538 "dcmpu %0,%1,%2" | |
| 539 [(set_attr "type" "fpcompare")]) | |
| 540 | |
| 541 (define_insn "*cmptd_internal1" | |
| 542 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y") | |
|
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543 (compare:CCFP (match_operand:TD 1 "gpc_reg_operand" "d") |
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544 (match_operand:TD 2 "gpc_reg_operand" "d")))] |
| 0 | 545 "TARGET_DFP" |
| 546 "dcmpuq %0,%1,%2" | |
| 547 [(set_attr "type" "fpcompare")]) | |
| 548 | |
| 549 (define_insn "floatditd2" | |
|
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550 [(set (match_operand:TD 0 "gpc_reg_operand" "=d") |
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551 (float:TD (match_operand:DI 1 "gpc_reg_operand" "d")))] |
| 0 | 552 "TARGET_DFP" |
| 553 "dcffixq %0,%1" | |
| 554 [(set_attr "type" "fp")]) | |
| 555 | |
| 556 ;; Convert a decimal64 to a decimal64 whose value is an integer. | |
| 557 ;; This is the first stage of converting it to an integer type. | |
| 558 | |
| 559 (define_insn "ftruncdd2" | |
|
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560 [(set (match_operand:DD 0 "gpc_reg_operand" "=d") |
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561 (fix:DD (match_operand:DD 1 "gpc_reg_operand" "d")))] |
| 0 | 562 "TARGET_DFP" |
| 563 "drintn. 0,%0,%1,1" | |
| 564 [(set_attr "type" "fp")]) | |
| 565 | |
| 566 ;; Convert a decimal64 whose value is an integer to an actual integer. | |
| 567 ;; This is the second stage of converting decimal float to integer type. | |
| 568 | |
| 569 (define_insn "fixdddi2" | |
|
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570 [(set (match_operand:DI 0 "gpc_reg_operand" "=d") |
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571 (fix:DI (match_operand:DD 1 "gpc_reg_operand" "d")))] |
| 0 | 572 "TARGET_DFP" |
| 573 "dctfix %0,%1" | |
| 574 [(set_attr "type" "fp")]) | |
| 575 | |
| 576 ;; Convert a decimal128 to a decimal128 whose value is an integer. | |
| 577 ;; This is the first stage of converting it to an integer type. | |
| 578 | |
| 579 (define_insn "ftrunctd2" | |
|
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580 [(set (match_operand:TD 0 "gpc_reg_operand" "=d") |
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581 (fix:TD (match_operand:TD 1 "gpc_reg_operand" "d")))] |
| 0 | 582 "TARGET_DFP" |
| 583 "drintnq. 0,%0,%1,1" | |
| 584 [(set_attr "type" "fp")]) | |
| 585 | |
| 586 ;; Convert a decimal128 whose value is an integer to an actual integer. | |
| 587 ;; This is the second stage of converting decimal float to integer type. | |
| 588 | |
| 589 (define_insn "fixtddi2" | |
|
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590 [(set (match_operand:DI 0 "gpc_reg_operand" "=d") |
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591 (fix:DI (match_operand:TD 1 "gpc_reg_operand" "d")))] |
| 0 | 592 "TARGET_DFP" |
| 593 "dctfixq %0,%1" | |
| 594 [(set_attr "type" "fp")]) |