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comparison gcc/config/s390/s390.md @ 63:b7f97abdc517 gcc-4.6-20100522

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update gcc from gcc-4.5.0 to gcc-4.6
author ryoma <e075725@ie.u-ryukyu.ac.jp>
date Mon, 24 May 2010 12:47:05 +0900
parents 77e2b8dfacca
children f6334be47118
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56:3c8a44c06a95 63:b7f97abdc517
1 ;;- Machine description for GNU compiler -- S/390 / zSeries version. 1 ;;- Machine description for GNU compiler -- S/390 / zSeries version.
2 ;; Copyright (C) 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2 ;; Copyright (C) 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008,
3 ;; 2009 Free Software Foundation, Inc. 3 ;; 2009, 2010 Free Software Foundation, Inc.
4 ;; Contributed by Hartmut Penner (hpenner@de.ibm.com) and 4 ;; Contributed by Hartmut Penner (hpenner@de.ibm.com) and
5 ;; Ulrich Weigand (uweigand@de.ibm.com) and 5 ;; Ulrich Weigand (uweigand@de.ibm.com) and
6 ;; Andreas Krebbel (Andreas.Krebbel@de.ibm.com) 6 ;; Andreas Krebbel (Andreas.Krebbel@de.ibm.com)
7 7
8 ;; This file is part of GCC. 8 ;; This file is part of GCC.
335 ;; from the same template. 335 ;; from the same template.
336 (define_mode_iterator TDSI [(TI "TARGET_64BIT") DI SI]) 336 (define_mode_iterator TDSI [(TI "TARGET_64BIT") DI SI])
337 337
338 ;; These mode iterators allow 31-bit and 64-bit GPR patterns to be generated 338 ;; These mode iterators allow 31-bit and 64-bit GPR patterns to be generated
339 ;; from the same template. 339 ;; from the same template.
340 (define_mode_iterator GPR [(DI "TARGET_64BIT") SI]) 340 (define_mode_iterator GPR [(DI "TARGET_ZARCH") SI])
341 (define_mode_iterator DSI [DI SI]) 341 (define_mode_iterator DSI [DI SI])
342 342
343 ;; These mode iterators allow :P to be used for patterns that operate on 343 ;; These mode iterators allow :P to be used for patterns that operate on
344 ;; pointer-sized quantities. Exactly one of the two alternatives will match. 344 ;; pointer-sized quantities. Exactly one of the two alternatives will match.
345 (define_mode_iterator DP [(TI "TARGET_64BIT") (DI "!TARGET_64BIT")])
346 (define_mode_iterator P [(DI "TARGET_64BIT") (SI "!TARGET_64BIT")]) 345 (define_mode_iterator P [(DI "TARGET_64BIT") (SI "!TARGET_64BIT")])
346
347 ;; These macros refer to the actual word_mode of the configuration. This is equal
348 ;; to Pmode except on 31-bit machines in zarch mode.
349 (define_mode_iterator DW [(TI "TARGET_ZARCH") (DI "!TARGET_ZARCH")])
350 (define_mode_iterator W [(DI "TARGET_ZARCH") (SI "!TARGET_ZARCH")])
347 351
348 ;; This mode iterator allows the QI and HI patterns to be defined from 352 ;; This mode iterator allows the QI and HI patterns to be defined from
349 ;; the same template. 353 ;; the same template.
350 (define_mode_iterator HQI [HI QI]) 354 (define_mode_iterator HQI [HI QI])
351 355
352 ;; This mode iterator allows the integer patterns to be defined from the 356 ;; This mode iterator allows the integer patterns to be defined from the
353 ;; same template. 357 ;; same template.
354 (define_mode_iterator INT [(DI "TARGET_64BIT") SI HI QI]) 358 (define_mode_iterator INT [(DI "TARGET_ZARCH") SI HI QI])
355 (define_mode_iterator INTALL [TI DI SI HI QI]) 359 (define_mode_iterator INTALL [TI DI SI HI QI])
356 360
357 ;; This iterator allows some 'ashift' and 'lshiftrt' pattern to be defined from 361 ;; This iterator allows some 'ashift' and 'lshiftrt' pattern to be defined from
358 ;; the same template. 362 ;; the same template.
359 (define_code_iterator SHIFT [ashift lshiftrt]) 363 (define_code_iterator SHIFT [ashift lshiftrt])
453 ;; and "sly" in SImode. This is useful because on 64bit the ..g instructions 457 ;; and "sly" in SImode. This is useful because on 64bit the ..g instructions
454 ;; were enhanced with long displacements whereas 31bit instructions got a ..y 458 ;; were enhanced with long displacements whereas 31bit instructions got a ..y
455 ;; variant for long displacements. 459 ;; variant for long displacements.
456 (define_mode_attr y [(DI "g") (SI "y")]) 460 (define_mode_attr y [(DI "g") (SI "y")])
457 461
458 ;; In DP templates, a string like "cds<g>" will expand to "cdsg" in TImode 462 ;; In DW templates, a string like "cds<g>" will expand to "cdsg" in TImode
459 ;; and "cds" in DImode. 463 ;; and "cds" in DImode.
460 (define_mode_attr tg [(TI "g") (DI "")]) 464 (define_mode_attr tg [(TI "g") (DI "")])
461 465
462 ;; In GPR templates, a string like "c<gf>dbr" will expand to "cgdbr" in DImode 466 ;; In GPR templates, a string like "c<gf>dbr" will expand to "cgdbr" in DImode
463 ;; and "cfdbr" in SImode. 467 ;; and "cfdbr" in SImode.
504 [(set (reg CC_REGNUM) 508 [(set (reg CC_REGNUM)
505 (compare (and:DI (match_operand:DI 0 "nonimmediate_operand" "d,d,d,d") 509 (compare (and:DI (match_operand:DI 0 "nonimmediate_operand" "d,d,d,d")
506 (match_operand:DI 1 "immediate_operand" 510 (match_operand:DI 1 "immediate_operand"
507 "N0HD0,N1HD0,N2HD0,N3HD0")) 511 "N0HD0,N1HD0,N2HD0,N3HD0"))
508 (match_operand:DI 2 "immediate_operand" "n,n,n,n")))] 512 (match_operand:DI 2 "immediate_operand" "n,n,n,n")))]
509 "TARGET_64BIT 513 "TARGET_ZARCH
510 && s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], true)) 514 && s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], true))
511 && s390_single_part (operands[1], DImode, HImode, 0) >= 0" 515 && s390_single_part (operands[1], DImode, HImode, 0) >= 0"
512 "@ 516 "@
513 tmhh\t%0,%i1 517 tmhh\t%0,%i1
514 tmhl\t%0,%i1 518 tmhl\t%0,%i1
554 (subreg:DI (match_operand:SI 0 "nonimmediate_operand" "d,RT") 0) 558 (subreg:DI (match_operand:SI 0 "nonimmediate_operand" "d,RT") 0)
555 (const_int 32)) (const_int 32)) 559 (const_int 32)) (const_int 32))
556 (match_operand:DI 1 "const0_operand" ""))) 560 (match_operand:DI 1 "const0_operand" "")))
557 (set (match_operand:DI 2 "register_operand" "=d,d") 561 (set (match_operand:DI 2 "register_operand" "=d,d")
558 (sign_extend:DI (match_dup 0)))] 562 (sign_extend:DI (match_dup 0)))]
559 "s390_match_ccmode(insn, CCSmode) && TARGET_64BIT" 563 "s390_match_ccmode(insn, CCSmode) && TARGET_ZARCH"
560 "ltgfr\t%2,%0 564 "ltgfr\t%2,%0
561 ltgf\t%2,%0" 565 ltgf\t%2,%0"
562 [(set_attr "op_type" "RRE,RXY") 566 [(set_attr "op_type" "RRE,RXY")
563 (set_attr "cpu_facility" "*,z10") 567 (set_attr "cpu_facility" "*,z10")
564 (set_attr "z10prop" "z10_super_E1,z10_super_E1") ]) 568 (set_attr "z10prop" "z10_super_E1,z10_super_E1") ])
594 [(set (reg CC_REGNUM) 598 [(set (reg CC_REGNUM)
595 (compare (match_operand:DI 0 "register_operand" "d") 599 (compare (match_operand:DI 0 "register_operand" "d")
596 (match_operand:DI 1 "const0_operand" ""))) 600 (match_operand:DI 1 "const0_operand" "")))
597 (set (match_operand:DI 2 "register_operand" "=d") 601 (set (match_operand:DI 2 "register_operand" "=d")
598 (match_dup 0))] 602 (match_dup 0))]
599 "s390_match_ccmode(insn, CCSmode) && TARGET_64BIT && !TARGET_EXTIMM" 603 "s390_match_ccmode(insn, CCSmode) && TARGET_ZARCH && !TARGET_EXTIMM"
600 "ltgr\t%2,%0" 604 "ltgr\t%2,%0"
601 [(set_attr "op_type" "RRE") 605 [(set_attr "op_type" "RRE")
602 (set_attr "z10prop" "z10_fr_E1")]) 606 (set_attr "z10prop" "z10_fr_E1")])
603 607
604 (define_insn "*tstsi" 608 (define_insn "*tstsi"
630 634
631 (define_insn "*tstdi_cconly_31" 635 (define_insn "*tstdi_cconly_31"
632 [(set (reg CC_REGNUM) 636 [(set (reg CC_REGNUM)
633 (compare (match_operand:DI 0 "register_operand" "d") 637 (compare (match_operand:DI 0 "register_operand" "d")
634 (match_operand:DI 1 "const0_operand" "")))] 638 (match_operand:DI 1 "const0_operand" "")))]
635 "s390_match_ccmode(insn, CCSmode) && !TARGET_64BIT" 639 "s390_match_ccmode(insn, CCSmode) && !TARGET_ZARCH"
636 "srda\t%0,0" 640 "srda\t%0,0"
637 [(set_attr "op_type" "RS") 641 [(set_attr "op_type" "RS")
638 (set_attr "atype" "reg")]) 642 (set_attr "atype" "reg")])
639 643
640 ; ltr, ltgr 644 ; ltr, ltgr
718 722
719 (define_insn "*cmpdi_cct" 723 (define_insn "*cmpdi_cct"
720 [(set (reg CC_REGNUM) 724 [(set (reg CC_REGNUM)
721 (compare (match_operand:DI 0 "nonimmediate_operand" "%d,d,d,d,Q") 725 (compare (match_operand:DI 0 "nonimmediate_operand" "%d,d,d,d,Q")
722 (match_operand:DI 1 "general_operand" "d,K,Os,RT,BQ")))] 726 (match_operand:DI 1 "general_operand" "d,K,Os,RT,BQ")))]
723 "s390_match_ccmode (insn, CCTmode) && TARGET_64BIT" 727 "s390_match_ccmode (insn, CCTmode) && TARGET_ZARCH"
724 "@ 728 "@
725 cgr\t%0,%1 729 cgr\t%0,%1
726 cghi\t%0,%h1 730 cghi\t%0,%h1
727 cgfi\t%0,%1 731 cgfi\t%0,%1
728 cg\t%0,%1 732 cg\t%0,%1
750 (define_insn "*cmpdi_ccs_sign" 754 (define_insn "*cmpdi_ccs_sign"
751 [(set (reg CC_REGNUM) 755 [(set (reg CC_REGNUM)
752 (compare (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" 756 (compare (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand"
753 "d,RT,b")) 757 "d,RT,b"))
754 (match_operand:DI 0 "register_operand" "d, d,d")))] 758 (match_operand:DI 0 "register_operand" "d, d,d")))]
755 "s390_match_ccmode(insn, CCSRmode) && TARGET_64BIT" 759 "s390_match_ccmode(insn, CCSRmode) && TARGET_ZARCH"
756 "@ 760 "@
757 cgfr\t%0,%1 761 cgfr\t%0,%1
758 cgf\t%0,%1 762 cgf\t%0,%1
759 cgfrl\t%0,%1" 763 cgfrl\t%0,%1"
760 [(set_attr "op_type" "RRE,RXY,RIL") 764 [(set_attr "op_type" "RRE,RXY,RIL")
845 (define_insn "*cmpdi_ccu_zero" 849 (define_insn "*cmpdi_ccu_zero"
846 [(set (reg CC_REGNUM) 850 [(set (reg CC_REGNUM)
847 (compare (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" 851 (compare (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand"
848 "d,RT,b")) 852 "d,RT,b"))
849 (match_operand:DI 0 "register_operand" "d, d,d")))] 853 (match_operand:DI 0 "register_operand" "d, d,d")))]
850 "s390_match_ccmode (insn, CCURmode) && TARGET_64BIT" 854 "s390_match_ccmode (insn, CCURmode) && TARGET_ZARCH"
851 "@ 855 "@
852 clgfr\t%0,%1 856 clgfr\t%0,%1
853 clgf\t%0,%1 857 clgf\t%0,%1
854 clgfrl\t%0,%1" 858 clgfrl\t%0,%1"
855 [(set_attr "op_type" "RRE,RXY,RIL") 859 [(set_attr "op_type" "RRE,RXY,RIL")
861 [(set (reg CC_REGNUM) 865 [(set (reg CC_REGNUM)
862 (compare (match_operand:DI 0 "nonimmediate_operand" 866 (compare (match_operand:DI 0 "nonimmediate_operand"
863 "d, d,d,Q, d, Q,BQ") 867 "d, d,d,Q, d, Q,BQ")
864 (match_operand:DI 1 "general_operand" 868 (match_operand:DI 1 "general_operand"
865 "d,Op,b,D,RT,BQ,Q")))] 869 "d,Op,b,D,RT,BQ,Q")))]
866 "s390_match_ccmode (insn, CCUmode) && TARGET_64BIT" 870 "s390_match_ccmode (insn, CCUmode) && TARGET_ZARCH"
867 "@ 871 "@
868 clgr\t%0,%1 872 clgr\t%0,%1
869 clgfi\t%0,%1 873 clgfi\t%0,%1
870 clgrl\t%0,%1 874 clgrl\t%0,%1
871 clghsi\t%0,%x1 875 clghsi\t%0,%x1
1113 ; 1117 ;
1114 1118
1115 (define_insn "movti" 1119 (define_insn "movti"
1116 [(set (match_operand:TI 0 "nonimmediate_operand" "=d,QS,d,o") 1120 [(set (match_operand:TI 0 "nonimmediate_operand" "=d,QS,d,o")
1117 (match_operand:TI 1 "general_operand" "QS,d,dPRT,d"))] 1121 (match_operand:TI 1 "general_operand" "QS,d,dPRT,d"))]
1118 "TARGET_64BIT" 1122 "TARGET_ZARCH"
1119 "@ 1123 "@
1120 lmg\t%0,%N0,%S1 1124 lmg\t%0,%N0,%S1
1121 stmg\t%1,%N1,%S0 1125 stmg\t%1,%N1,%S0
1122 # 1126 #
1123 #" 1127 #"
1125 (set_attr "type" "lm,stm,*,*")]) 1129 (set_attr "type" "lm,stm,*,*")])
1126 1130
1127 (define_split 1131 (define_split
1128 [(set (match_operand:TI 0 "nonimmediate_operand" "") 1132 [(set (match_operand:TI 0 "nonimmediate_operand" "")
1129 (match_operand:TI 1 "general_operand" ""))] 1133 (match_operand:TI 1 "general_operand" ""))]
1130 "TARGET_64BIT && reload_completed 1134 "TARGET_ZARCH && reload_completed
1131 && s390_split_ok_p (operands[0], operands[1], TImode, 0)" 1135 && s390_split_ok_p (operands[0], operands[1], TImode, 0)"
1132 [(set (match_dup 2) (match_dup 4)) 1136 [(set (match_dup 2) (match_dup 4))
1133 (set (match_dup 3) (match_dup 5))] 1137 (set (match_dup 3) (match_dup 5))]
1134 { 1138 {
1135 operands[2] = operand_subword (operands[0], 0, 0, TImode); 1139 operands[2] = operand_subword (operands[0], 0, 0, TImode);
1139 }) 1143 })
1140 1144
1141 (define_split 1145 (define_split
1142 [(set (match_operand:TI 0 "nonimmediate_operand" "") 1146 [(set (match_operand:TI 0 "nonimmediate_operand" "")
1143 (match_operand:TI 1 "general_operand" ""))] 1147 (match_operand:TI 1 "general_operand" ""))]
1144 "TARGET_64BIT && reload_completed 1148 "TARGET_ZARCH && reload_completed
1145 && s390_split_ok_p (operands[0], operands[1], TImode, 1)" 1149 && s390_split_ok_p (operands[0], operands[1], TImode, 1)"
1146 [(set (match_dup 2) (match_dup 4)) 1150 [(set (match_dup 2) (match_dup 4))
1147 (set (match_dup 3) (match_dup 5))] 1151 (set (match_dup 3) (match_dup 5))]
1148 { 1152 {
1149 operands[2] = operand_subword (operands[0], 1, 0, TImode); 1153 operands[2] = operand_subword (operands[0], 1, 0, TImode);
1153 }) 1157 })
1154 1158
1155 (define_split 1159 (define_split
1156 [(set (match_operand:TI 0 "register_operand" "") 1160 [(set (match_operand:TI 0 "register_operand" "")
1157 (match_operand:TI 1 "memory_operand" ""))] 1161 (match_operand:TI 1 "memory_operand" ""))]
1158 "TARGET_64BIT && reload_completed 1162 "TARGET_ZARCH && reload_completed
1159 && !s_operand (operands[1], VOIDmode)" 1163 && !s_operand (operands[1], VOIDmode)"
1160 [(set (match_dup 0) (match_dup 1))] 1164 [(set (match_dup 0) (match_dup 1))]
1161 { 1165 {
1162 rtx addr = operand_subword (operands[0], 1, 0, TImode); 1166 rtx addr = operand_subword (operands[0], 1, 0, TImode);
1167 addr = gen_lowpart (Pmode, addr);
1163 s390_load_address (addr, XEXP (operands[1], 0)); 1168 s390_load_address (addr, XEXP (operands[1], 0));
1164 operands[1] = replace_equiv_address (operands[1], addr); 1169 operands[1] = replace_equiv_address (operands[1], addr);
1165 }) 1170 })
1166 1171
1167 1172
1306 "=d,d,d,d,d,d,d,d,f,d,d,d,d,d, 1311 "=d,d,d,d,d,d,d,d,f,d,d,d,d,d,
1307 RT,!*f,!*f,!*f,!R,!T,b,Q,d,t,Q,t") 1312 RT,!*f,!*f,!*f,!R,!T,b,Q,d,t,Q,t")
1308 (match_operand:DI 1 "general_operand" 1313 (match_operand:DI 1 "general_operand"
1309 "K,N0HD0,N1HD0,N2HD0,N3HD0,Os,N0SD0,N1SD0,d,f,L,b,d,RT, 1314 "K,N0HD0,N1HD0,N2HD0,N3HD0,Os,N0SD0,N1SD0,d,f,L,b,d,RT,
1310 d,*f,R,T,*f,*f,d,K,t,d,t,Q"))] 1315 d,*f,R,T,*f,*f,d,K,t,d,t,Q"))]
1311 "TARGET_64BIT" 1316 "TARGET_ZARCH"
1312 "@ 1317 "@
1313 lghi\t%0,%h1 1318 lghi\t%0,%h1
1314 llihh\t%0,%i1 1319 llihh\t%0,%i1
1315 llihl\t%0,%i1 1320 llihl\t%0,%i1
1316 llilh\t%0,%i1 1321 llilh\t%0,%i1
1373 ]) 1378 ])
1374 1379
1375 (define_split 1380 (define_split
1376 [(set (match_operand:DI 0 "register_operand" "") 1381 [(set (match_operand:DI 0 "register_operand" "")
1377 (match_operand:DI 1 "register_operand" ""))] 1382 (match_operand:DI 1 "register_operand" ""))]
1378 "TARGET_64BIT && ACCESS_REG_P (operands[1])" 1383 "TARGET_ZARCH && ACCESS_REG_P (operands[1])"
1379 [(set (match_dup 2) (match_dup 3)) 1384 [(set (match_dup 2) (match_dup 3))
1380 (set (match_dup 0) (ashift:DI (match_dup 0) (const_int 32))) 1385 (set (match_dup 0) (ashift:DI (match_dup 0) (const_int 32)))
1381 (set (strict_low_part (match_dup 2)) (match_dup 4))] 1386 (set (strict_low_part (match_dup 2)) (match_dup 4))]
1382 "operands[2] = gen_lowpart (SImode, operands[0]); 1387 "operands[2] = gen_lowpart (SImode, operands[0]);
1383 s390_split_access_reg (operands[1], &operands[4], &operands[3]);") 1388 s390_split_access_reg (operands[1], &operands[4], &operands[3]);")
1384 1389
1385 (define_split 1390 (define_split
1386 [(set (match_operand:DI 0 "register_operand" "") 1391 [(set (match_operand:DI 0 "register_operand" "")
1387 (match_operand:DI 1 "register_operand" ""))] 1392 (match_operand:DI 1 "register_operand" ""))]
1388 "TARGET_64BIT && ACCESS_REG_P (operands[0]) 1393 "TARGET_ZARCH && ACCESS_REG_P (operands[0])
1389 && dead_or_set_p (insn, operands[1])" 1394 && dead_or_set_p (insn, operands[1])"
1390 [(set (match_dup 3) (match_dup 2)) 1395 [(set (match_dup 3) (match_dup 2))
1391 (set (match_dup 1) (lshiftrt:DI (match_dup 1) (const_int 32))) 1396 (set (match_dup 1) (lshiftrt:DI (match_dup 1) (const_int 32)))
1392 (set (match_dup 4) (match_dup 2))] 1397 (set (match_dup 4) (match_dup 2))]
1393 "operands[2] = gen_lowpart (SImode, operands[1]); 1398 "operands[2] = gen_lowpart (SImode, operands[1]);
1394 s390_split_access_reg (operands[0], &operands[3], &operands[4]);") 1399 s390_split_access_reg (operands[0], &operands[3], &operands[4]);")
1395 1400
1396 (define_split 1401 (define_split
1397 [(set (match_operand:DI 0 "register_operand" "") 1402 [(set (match_operand:DI 0 "register_operand" "")
1398 (match_operand:DI 1 "register_operand" ""))] 1403 (match_operand:DI 1 "register_operand" ""))]
1399 "TARGET_64BIT && ACCESS_REG_P (operands[0]) 1404 "TARGET_ZARCH && ACCESS_REG_P (operands[0])
1400 && !dead_or_set_p (insn, operands[1])" 1405 && !dead_or_set_p (insn, operands[1])"
1401 [(set (match_dup 3) (match_dup 2)) 1406 [(set (match_dup 3) (match_dup 2))
1402 (set (match_dup 1) (rotate:DI (match_dup 1) (const_int 32))) 1407 (set (match_dup 1) (rotate:DI (match_dup 1) (const_int 32)))
1403 (set (match_dup 4) (match_dup 2)) 1408 (set (match_dup 4) (match_dup 2))
1404 (set (match_dup 1) (rotate:DI (match_dup 1) (const_int 32)))] 1409 (set (match_dup 1) (rotate:DI (match_dup 1) (const_int 32)))]
1408 (define_insn "*movdi_31" 1413 (define_insn "*movdi_31"
1409 [(set (match_operand:DI 0 "nonimmediate_operand" 1414 [(set (match_operand:DI 0 "nonimmediate_operand"
1410 "=d,d,Q,S,d ,o,!*f,!*f,!*f,!R,!T,d") 1415 "=d,d,Q,S,d ,o,!*f,!*f,!*f,!R,!T,d")
1411 (match_operand:DI 1 "general_operand" 1416 (match_operand:DI 1 "general_operand"
1412 " Q,S,d,d,dPRT,d, *f, R, T,*f,*f,b"))] 1417 " Q,S,d,d,dPRT,d, *f, R, T,*f,*f,b"))]
1413 "!TARGET_64BIT" 1418 "!TARGET_ZARCH"
1414 "@ 1419 "@
1415 lm\t%0,%N0,%S1 1420 lm\t%0,%N0,%S1
1416 lmy\t%0,%N0,%S1 1421 lmy\t%0,%N0,%S1
1417 stm\t%1,%N1,%S0 1422 stm\t%1,%N1,%S0
1418 stmy\t%1,%N1,%S0 1423 stmy\t%1,%N1,%S0
1431 ; For a load from a symbol ref we can use one of the target registers 1436 ; For a load from a symbol ref we can use one of the target registers
1432 ; together with larl to load the address. 1437 ; together with larl to load the address.
1433 (define_split 1438 (define_split
1434 [(set (match_operand:DI 0 "register_operand" "") 1439 [(set (match_operand:DI 0 "register_operand" "")
1435 (match_operand:DI 1 "memory_operand" ""))] 1440 (match_operand:DI 1 "memory_operand" ""))]
1436 "!TARGET_64BIT && reload_completed && TARGET_Z10 1441 "!TARGET_ZARCH && reload_completed && TARGET_Z10
1437 && larl_operand (XEXP (operands[1], 0), SImode)" 1442 && larl_operand (XEXP (operands[1], 0), SImode)"
1438 [(set (match_dup 2) (match_dup 3)) 1443 [(set (match_dup 2) (match_dup 3))
1439 (set (match_dup 0) (match_dup 1))] 1444 (set (match_dup 0) (match_dup 1))]
1440 { 1445 {
1441 operands[2] = operand_subword (operands[0], 1, 0, DImode); 1446 operands[2] = operand_subword (operands[0], 1, 0, DImode);
1444 }) 1449 })
1445 1450
1446 (define_split 1451 (define_split
1447 [(set (match_operand:DI 0 "nonimmediate_operand" "") 1452 [(set (match_operand:DI 0 "nonimmediate_operand" "")
1448 (match_operand:DI 1 "general_operand" ""))] 1453 (match_operand:DI 1 "general_operand" ""))]
1449 "!TARGET_64BIT && reload_completed 1454 "!TARGET_ZARCH && reload_completed
1450 && s390_split_ok_p (operands[0], operands[1], DImode, 0)" 1455 && s390_split_ok_p (operands[0], operands[1], DImode, 0)"
1451 [(set (match_dup 2) (match_dup 4)) 1456 [(set (match_dup 2) (match_dup 4))
1452 (set (match_dup 3) (match_dup 5))] 1457 (set (match_dup 3) (match_dup 5))]
1453 { 1458 {
1454 operands[2] = operand_subword (operands[0], 0, 0, DImode); 1459 operands[2] = operand_subword (operands[0], 0, 0, DImode);
1458 }) 1463 })
1459 1464
1460 (define_split 1465 (define_split
1461 [(set (match_operand:DI 0 "nonimmediate_operand" "") 1466 [(set (match_operand:DI 0 "nonimmediate_operand" "")
1462 (match_operand:DI 1 "general_operand" ""))] 1467 (match_operand:DI 1 "general_operand" ""))]
1463 "!TARGET_64BIT && reload_completed 1468 "!TARGET_ZARCH && reload_completed
1464 && s390_split_ok_p (operands[0], operands[1], DImode, 1)" 1469 && s390_split_ok_p (operands[0], operands[1], DImode, 1)"
1465 [(set (match_dup 2) (match_dup 4)) 1470 [(set (match_dup 2) (match_dup 4))
1466 (set (match_dup 3) (match_dup 5))] 1471 (set (match_dup 3) (match_dup 5))]
1467 { 1472 {
1468 operands[2] = operand_subword (operands[0], 1, 0, DImode); 1473 operands[2] = operand_subword (operands[0], 1, 0, DImode);
1472 }) 1477 })
1473 1478
1474 (define_split 1479 (define_split
1475 [(set (match_operand:DI 0 "register_operand" "") 1480 [(set (match_operand:DI 0 "register_operand" "")
1476 (match_operand:DI 1 "memory_operand" ""))] 1481 (match_operand:DI 1 "memory_operand" ""))]
1477 "!TARGET_64BIT && reload_completed 1482 "!TARGET_ZARCH && reload_completed
1478 && !FP_REG_P (operands[0]) 1483 && !FP_REG_P (operands[0])
1479 && !s_operand (operands[1], VOIDmode)" 1484 && !s_operand (operands[1], VOIDmode)"
1480 [(set (match_dup 0) (match_dup 1))] 1485 [(set (match_dup 0) (match_dup 1))]
1481 { 1486 {
1482 rtx addr = operand_subword (operands[0], 1, 0, DImode); 1487 rtx addr = operand_subword (operands[0], 1, 0, DImode);
1485 }) 1490 })
1486 1491
1487 (define_peephole2 1492 (define_peephole2
1488 [(set (match_operand:DI 0 "register_operand" "") 1493 [(set (match_operand:DI 0 "register_operand" "")
1489 (mem:DI (match_operand 1 "address_operand" "")))] 1494 (mem:DI (match_operand 1 "address_operand" "")))]
1490 "TARGET_64BIT 1495 "TARGET_ZARCH
1491 && !FP_REG_P (operands[0]) 1496 && !FP_REG_P (operands[0])
1492 && GET_CODE (operands[1]) == SYMBOL_REF 1497 && GET_CODE (operands[1]) == SYMBOL_REF
1493 && CONSTANT_POOL_ADDRESS_P (operands[1]) 1498 && CONSTANT_POOL_ADDRESS_P (operands[1])
1494 && get_pool_mode (operands[1]) == DImode 1499 && get_pool_mode (operands[1]) == DImode
1495 && legitimate_reload_constant_p (get_pool_constant (operands[1]))" 1500 && legitimate_reload_constant_p (get_pool_constant (operands[1]))"
1824 is just as fast as a QImode load. */ 1829 is just as fast as a QImode load. */
1825 if (TARGET_ZARCH && optimize && can_create_pseudo_p () 1830 if (TARGET_ZARCH && optimize && can_create_pseudo_p ()
1826 && register_operand (operands[0], VOIDmode) 1831 && register_operand (operands[0], VOIDmode)
1827 && GET_CODE (operands[1]) == MEM) 1832 && GET_CODE (operands[1]) == MEM)
1828 { 1833 {
1829 rtx tmp = gen_reg_rtx (word_mode); 1834 rtx tmp = gen_reg_rtx (DImode);
1830 rtx ext = gen_rtx_ZERO_EXTEND (word_mode, operands[1]); 1835 rtx ext = gen_rtx_ZERO_EXTEND (DImode, operands[1]);
1831 emit_insn (gen_rtx_SET (VOIDmode, tmp, ext)); 1836 emit_insn (gen_rtx_SET (VOIDmode, tmp, ext));
1832 operands[1] = gen_lowpart (QImode, tmp); 1837 operands[1] = gen_lowpart (QImode, tmp);
1833 } 1838 }
1834 }) 1839 })
1835 1840
1836 (define_insn "*movqi" 1841 (define_insn "*movqi"
1837 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,d,d,R,T,Q,S") 1842 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,d,d,R,T,Q,S,?Q")
1838 (match_operand:QI 1 "general_operand" "d,n,R,T,d,d,n,n"))] 1843 (match_operand:QI 1 "general_operand" " d,n,R,T,d,d,n,n,?Q"))]
1839 "" 1844 ""
1840 "@ 1845 "@
1841 lr\t%0,%1 1846 lr\t%0,%1
1842 lhi\t%0,%b1 1847 lhi\t%0,%b1
1843 ic\t%0,%1 1848 ic\t%0,%1
1844 icy\t%0,%1 1849 icy\t%0,%1
1845 stc\t%1,%0 1850 stc\t%1,%0
1846 stcy\t%1,%0 1851 stcy\t%1,%0
1847 mvi\t%S0,%b1 1852 mvi\t%S0,%b1
1848 mviy\t%S0,%b1" 1853 mviy\t%S0,%b1
1849 [(set_attr "op_type" "RR,RI,RX,RXY,RX,RXY,SI,SIY") 1854 *"
1850 (set_attr "type" "lr,*,*,*,store,store,store,store") 1855 [(set_attr "op_type" "RR,RI,RX,RXY,RX,RXY,SI,SIY,SS")
1856 (set_attr "type" "lr,*,*,*,store,store,store,store,*")
1851 (set_attr "z10prop" "z10_fr_E1, 1857 (set_attr "z10prop" "z10_fr_E1,
1852 z10_fwd_A1, 1858 z10_fwd_A1,
1853 z10_super_E1, 1859 z10_super_E1,
1854 z10_super_E1, 1860 z10_super_E1,
1855 z10_rec, 1861 z10_rec,
1856 z10_rec, 1862 z10_rec,
1857 z10_super, 1863 z10_super,
1858 z10_super")]) 1864 z10_super,
1865 *")])
1859 1866
1860 (define_peephole2 1867 (define_peephole2
1861 [(set (match_operand:QI 0 "nonimmediate_operand" "") 1868 [(set (match_operand:QI 0 "nonimmediate_operand" "")
1862 (mem:QI (match_operand 1 "address_operand" "")))] 1869 (mem:QI (match_operand 1 "address_operand" "")))]
1863 "GET_CODE (operands[1]) == SYMBOL_REF 1870 "GET_CODE (operands[1]) == SYMBOL_REF
1901 ; 1908 ;
1902 1909
1903 (define_insn "movstrictsi" 1910 (define_insn "movstrictsi"
1904 [(set (strict_low_part (match_operand:SI 0 "register_operand" "+d,d,d,d")) 1911 [(set (strict_low_part (match_operand:SI 0 "register_operand" "+d,d,d,d"))
1905 (match_operand:SI 1 "general_operand" "d,R,T,t"))] 1912 (match_operand:SI 1 "general_operand" "d,R,T,t"))]
1906 "TARGET_64BIT" 1913 "TARGET_ZARCH"
1907 "@ 1914 "@
1908 lr\t%0,%1 1915 lr\t%0,%1
1909 l\t%0,%1 1916 l\t%0,%1
1910 ly\t%0,%1 1917 ly\t%0,%1
1911 ear\t%0,%1" 1918 ear\t%0,%1"
1924 "") 1931 "")
1925 1932
1926 (define_insn "*mov<mode>_64" 1933 (define_insn "*mov<mode>_64"
1927 [(set (match_operand:TD_TF 0 "nonimmediate_operand" "=f,f,f,o, d,QS, d,o") 1934 [(set (match_operand:TD_TF 0 "nonimmediate_operand" "=f,f,f,o, d,QS, d,o")
1928 (match_operand:TD_TF 1 "general_operand" " G,f,o,f,QS, d,dRT,d"))] 1935 (match_operand:TD_TF 1 "general_operand" " G,f,o,f,QS, d,dRT,d"))]
1929 "TARGET_64BIT" 1936 "TARGET_ZARCH"
1930 "@ 1937 "@
1931 lzxr\t%0 1938 lzxr\t%0
1932 lxr\t%0,%1 1939 lxr\t%0,%1
1933 # 1940 #
1934 # 1941 #
1940 (set_attr "type" "fhex,fsimptf,*,*,lm,stm,*,*")]) 1947 (set_attr "type" "fhex,fsimptf,*,*,lm,stm,*,*")])
1941 1948
1942 (define_insn "*mov<mode>_31" 1949 (define_insn "*mov<mode>_31"
1943 [(set (match_operand:TD_TF 0 "nonimmediate_operand" "=f,f,f,o") 1950 [(set (match_operand:TD_TF 0 "nonimmediate_operand" "=f,f,f,o")
1944 (match_operand:TD_TF 1 "general_operand" " G,f,o,f"))] 1951 (match_operand:TD_TF 1 "general_operand" " G,f,o,f"))]
1945 "!TARGET_64BIT" 1952 "!TARGET_ZARCH"
1946 "@ 1953 "@
1947 lzxr\t%0 1954 lzxr\t%0
1948 lxr\t%0,%1 1955 lxr\t%0,%1
1949 # 1956 #
1950 #" 1957 #"
1954 ; TFmode in GPRs splitters 1961 ; TFmode in GPRs splitters
1955 1962
1956 (define_split 1963 (define_split
1957 [(set (match_operand:TD_TF 0 "nonimmediate_operand" "") 1964 [(set (match_operand:TD_TF 0 "nonimmediate_operand" "")
1958 (match_operand:TD_TF 1 "general_operand" ""))] 1965 (match_operand:TD_TF 1 "general_operand" ""))]
1959 "TARGET_64BIT && reload_completed 1966 "TARGET_ZARCH && reload_completed
1960 && s390_split_ok_p (operands[0], operands[1], <MODE>mode, 0)" 1967 && s390_split_ok_p (operands[0], operands[1], <MODE>mode, 0)"
1961 [(set (match_dup 2) (match_dup 4)) 1968 [(set (match_dup 2) (match_dup 4))
1962 (set (match_dup 3) (match_dup 5))] 1969 (set (match_dup 3) (match_dup 5))]
1963 { 1970 {
1964 operands[2] = operand_subword (operands[0], 0, 0, <MODE>mode); 1971 operands[2] = operand_subword (operands[0], 0, 0, <MODE>mode);
1968 }) 1975 })
1969 1976
1970 (define_split 1977 (define_split
1971 [(set (match_operand:TD_TF 0 "nonimmediate_operand" "") 1978 [(set (match_operand:TD_TF 0 "nonimmediate_operand" "")
1972 (match_operand:TD_TF 1 "general_operand" ""))] 1979 (match_operand:TD_TF 1 "general_operand" ""))]
1973 "TARGET_64BIT && reload_completed 1980 "TARGET_ZARCH && reload_completed
1974 && s390_split_ok_p (operands[0], operands[1], <MODE>mode, 1)" 1981 && s390_split_ok_p (operands[0], operands[1], <MODE>mode, 1)"
1975 [(set (match_dup 2) (match_dup 4)) 1982 [(set (match_dup 2) (match_dup 4))
1976 (set (match_dup 3) (match_dup 5))] 1983 (set (match_dup 3) (match_dup 5))]
1977 { 1984 {
1978 operands[2] = operand_subword (operands[0], 1, 0, <MODE>mode); 1985 operands[2] = operand_subword (operands[0], 1, 0, <MODE>mode);
1982 }) 1989 })
1983 1990
1984 (define_split 1991 (define_split
1985 [(set (match_operand:TD_TF 0 "register_operand" "") 1992 [(set (match_operand:TD_TF 0 "register_operand" "")
1986 (match_operand:TD_TF 1 "memory_operand" ""))] 1993 (match_operand:TD_TF 1 "memory_operand" ""))]
1987 "TARGET_64BIT && reload_completed 1994 "TARGET_ZARCH && reload_completed
1988 && !FP_REG_P (operands[0]) 1995 && !FP_REG_P (operands[0])
1989 && !s_operand (operands[1], VOIDmode)" 1996 && !s_operand (operands[1], VOIDmode)"
1990 [(set (match_dup 0) (match_dup 1))] 1997 [(set (match_dup 0) (match_dup 1))]
1991 { 1998 {
1992 rtx addr = operand_subword (operands[0], 1, 0, <MODE>mode); 1999 rtx addr = operand_subword (operands[0], 1, 0, <MODE>mode);
2041 (define_insn "*mov<mode>_64dfp" 2048 (define_insn "*mov<mode>_64dfp"
2042 [(set (match_operand:DD_DF 0 "nonimmediate_operand" 2049 [(set (match_operand:DD_DF 0 "nonimmediate_operand"
2043 "=f,f,f,d,f,f,R,T,d, d,RT") 2050 "=f,f,f,d,f,f,R,T,d, d,RT")
2044 (match_operand:DD_DF 1 "general_operand" 2051 (match_operand:DD_DF 1 "general_operand"
2045 " G,f,d,f,R,T,f,f,d,RT, d"))] 2052 " G,f,d,f,R,T,f,f,d,RT, d"))]
2046 "TARGET_64BIT && TARGET_DFP" 2053 "TARGET_DFP"
2047 "@ 2054 "@
2048 lzdr\t%0 2055 lzdr\t%0
2049 ldr\t%0,%1 2056 ldr\t%0,%1
2050 ldgr\t%0,%1 2057 ldgr\t%0,%1
2051 lgdr\t%0,%1 2058 lgdr\t%0,%1
2073 ]) 2080 ])
2074 2081
2075 (define_insn "*mov<mode>_64" 2082 (define_insn "*mov<mode>_64"
2076 [(set (match_operand:DD_DF 0 "nonimmediate_operand" "=f,f,f,f,R,T,d, d,RT") 2083 [(set (match_operand:DD_DF 0 "nonimmediate_operand" "=f,f,f,f,R,T,d, d,RT")
2077 (match_operand:DD_DF 1 "general_operand" "G,f,R,T,f,f,d,RT, d"))] 2084 (match_operand:DD_DF 1 "general_operand" "G,f,R,T,f,f,d,RT, d"))]
2078 "TARGET_64BIT" 2085 "TARGET_ZARCH"
2079 "@ 2086 "@
2080 lzdr\t%0 2087 lzdr\t%0
2081 ldr\t%0,%1 2088 ldr\t%0,%1
2082 ld\t%0,%1 2089 ld\t%0,%1
2083 ldy\t%0,%1 2090 ldy\t%0,%1
2102 (define_insn "*mov<mode>_31" 2109 (define_insn "*mov<mode>_31"
2103 [(set (match_operand:DD_DF 0 "nonimmediate_operand" 2110 [(set (match_operand:DD_DF 0 "nonimmediate_operand"
2104 "=f,f,f,f,R,T,d,d,Q,S, d,o") 2111 "=f,f,f,f,R,T,d,d,Q,S, d,o")
2105 (match_operand:DD_DF 1 "general_operand" 2112 (match_operand:DD_DF 1 "general_operand"
2106 " G,f,R,T,f,f,Q,S,d,d,dPRT,d"))] 2113 " G,f,R,T,f,f,Q,S,d,d,dPRT,d"))]
2107 "!TARGET_64BIT" 2114 "!TARGET_ZARCH"
2108 "@ 2115 "@
2109 lzdr\t%0 2116 lzdr\t%0
2110 ldr\t%0,%1 2117 ldr\t%0,%1
2111 ld\t%0,%1 2118 ld\t%0,%1
2112 ldy\t%0,%1 2119 ldy\t%0,%1
2123 fstore<mode>,fstore<mode>,lm,lm,stm,stm,*,*")]) 2130 fstore<mode>,fstore<mode>,lm,lm,stm,stm,*,*")])
2124 2131
2125 (define_split 2132 (define_split
2126 [(set (match_operand:DD_DF 0 "nonimmediate_operand" "") 2133 [(set (match_operand:DD_DF 0 "nonimmediate_operand" "")
2127 (match_operand:DD_DF 1 "general_operand" ""))] 2134 (match_operand:DD_DF 1 "general_operand" ""))]
2128 "!TARGET_64BIT && reload_completed 2135 "!TARGET_ZARCH && reload_completed
2129 && s390_split_ok_p (operands[0], operands[1], <MODE>mode, 0)" 2136 && s390_split_ok_p (operands[0], operands[1], <MODE>mode, 0)"
2130 [(set (match_dup 2) (match_dup 4)) 2137 [(set (match_dup 2) (match_dup 4))
2131 (set (match_dup 3) (match_dup 5))] 2138 (set (match_dup 3) (match_dup 5))]
2132 { 2139 {
2133 operands[2] = operand_subword (operands[0], 0, 0, <MODE>mode); 2140 operands[2] = operand_subword (operands[0], 0, 0, <MODE>mode);
2137 }) 2144 })
2138 2145
2139 (define_split 2146 (define_split
2140 [(set (match_operand:DD_DF 0 "nonimmediate_operand" "") 2147 [(set (match_operand:DD_DF 0 "nonimmediate_operand" "")
2141 (match_operand:DD_DF 1 "general_operand" ""))] 2148 (match_operand:DD_DF 1 "general_operand" ""))]
2142 "!TARGET_64BIT && reload_completed 2149 "!TARGET_ZARCH && reload_completed
2143 && s390_split_ok_p (operands[0], operands[1], <MODE>mode, 1)" 2150 && s390_split_ok_p (operands[0], operands[1], <MODE>mode, 1)"
2144 [(set (match_dup 2) (match_dup 4)) 2151 [(set (match_dup 2) (match_dup 4))
2145 (set (match_dup 3) (match_dup 5))] 2152 (set (match_dup 3) (match_dup 5))]
2146 { 2153 {
2147 operands[2] = operand_subword (operands[0], 1, 0, <MODE>mode); 2154 operands[2] = operand_subword (operands[0], 1, 0, <MODE>mode);
2151 }) 2158 })
2152 2159
2153 (define_split 2160 (define_split
2154 [(set (match_operand:DD_DF 0 "register_operand" "") 2161 [(set (match_operand:DD_DF 0 "register_operand" "")
2155 (match_operand:DD_DF 1 "memory_operand" ""))] 2162 (match_operand:DD_DF 1 "memory_operand" ""))]
2156 "!TARGET_64BIT && reload_completed 2163 "!TARGET_ZARCH && reload_completed
2157 && !FP_REG_P (operands[0]) 2164 && !FP_REG_P (operands[0])
2158 && !s_operand (operands[1], VOIDmode)" 2165 && !s_operand (operands[1], VOIDmode)"
2159 [(set (match_dup 0) (match_dup 1))] 2166 [(set (match_dup 0) (match_dup 1))]
2160 { 2167 {
2161 rtx addr = operand_subword (operands[0], 1, 0, <MODE>mode); 2168 rtx addr = operand_subword (operands[0], 1, 0, <MODE>mode);
2230 (use (match_operand 2 "const_int_operand" "n"))] 2237 (use (match_operand 2 "const_int_operand" "n"))]
2231 "INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256" 2238 "INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256"
2232 "mvc\t%O0(%2,%R0),%S1" 2239 "mvc\t%O0(%2,%R0),%S1"
2233 [(set_attr "op_type" "SS")]) 2240 [(set_attr "op_type" "SS")])
2234 2241
2242 ; This splitter converts a QI to QI mode copy into a BLK mode copy in
2243 ; order to have it implemented with mvc.
2244
2245 (define_split
2246 [(set (match_operand:QI 0 "memory_operand" "")
2247 (match_operand:QI 1 "memory_operand" ""))]
2248 "reload_completed"
2249 [(parallel
2250 [(set (match_dup 0) (match_dup 1))
2251 (use (const_int 1))])]
2252 {
2253 operands[0] = adjust_address (operands[0], BLKmode, 0);
2254 operands[1] = adjust_address (operands[1], BLKmode, 0);
2255 })
2256
2257
2235 (define_peephole2 2258 (define_peephole2
2236 [(parallel 2259 [(parallel
2237 [(set (match_operand:BLK 0 "memory_operand" "") 2260 [(set (match_operand:BLK 0 "memory_operand" "")
2238 (match_operand:BLK 1 "memory_operand" "")) 2261 (match_operand:BLK 1 "memory_operand" ""))
2239 (use (match_operand 2 "const_int_operand" ""))]) 2262 (use (match_operand 2 "const_int_operand" ""))])
2284 FAIL; 2307 FAIL;
2285 2308
2286 count = INTVAL (operands[2]); 2309 count = INTVAL (operands[2]);
2287 regno = REGNO (operands[0]); 2310 regno = REGNO (operands[0]);
2288 mode = GET_MODE (operands[0]); 2311 mode = GET_MODE (operands[0]);
2289 if (mode != SImode && mode != word_mode) 2312 if (mode != SImode && (!TARGET_ZARCH || mode != DImode))
2290 FAIL; 2313 FAIL;
2291 2314
2292 operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count)); 2315 operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count));
2293 if (!can_create_pseudo_p ()) 2316 if (!can_create_pseudo_p ())
2294 { 2317 {
2322 2345
2323 (define_insn "*load_multiple_di" 2346 (define_insn "*load_multiple_di"
2324 [(match_parallel 0 "load_multiple_operation" 2347 [(match_parallel 0 "load_multiple_operation"
2325 [(set (match_operand:DI 1 "register_operand" "=r") 2348 [(set (match_operand:DI 1 "register_operand" "=r")
2326 (match_operand:DI 2 "s_operand" "QS"))])] 2349 (match_operand:DI 2 "s_operand" "QS"))])]
2327 "reload_completed && word_mode == DImode" 2350 "reload_completed && TARGET_ZARCH"
2328 { 2351 {
2329 int words = XVECLEN (operands[0], 0); 2352 int words = XVECLEN (operands[0], 0);
2330 operands[0] = gen_rtx_REG (DImode, REGNO (operands[1]) + words - 1); 2353 operands[0] = gen_rtx_REG (DImode, REGNO (operands[1]) + words - 1);
2331 return "lmg\t%1,%0,%S2"; 2354 return "lmg\t%1,%0,%S2";
2332 } 2355 }
2373 FAIL; 2396 FAIL;
2374 2397
2375 count = INTVAL (operands[2]); 2398 count = INTVAL (operands[2]);
2376 regno = REGNO (operands[1]); 2399 regno = REGNO (operands[1]);
2377 mode = GET_MODE (operands[1]); 2400 mode = GET_MODE (operands[1]);
2378 if (mode != SImode && mode != word_mode) 2401 if (mode != SImode && (!TARGET_ZARCH || mode != DImode))
2379 FAIL; 2402 FAIL;
2380 2403
2381 operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count)); 2404 operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count));
2382 2405
2383 if (!can_create_pseudo_p ()) 2406 if (!can_create_pseudo_p ())
2413 2436
2414 (define_insn "*store_multiple_di" 2437 (define_insn "*store_multiple_di"
2415 [(match_parallel 0 "store_multiple_operation" 2438 [(match_parallel 0 "store_multiple_operation"
2416 [(set (match_operand:DI 1 "s_operand" "=QS") 2439 [(set (match_operand:DI 1 "s_operand" "=QS")
2417 (match_operand:DI 2 "register_operand" "r"))])] 2440 (match_operand:DI 2 "register_operand" "r"))])]
2418 "reload_completed && word_mode == DImode" 2441 "reload_completed && TARGET_ZARCH"
2419 { 2442 {
2420 int words = XVECLEN (operands[0], 0); 2443 int words = XVECLEN (operands[0], 0);
2421 operands[0] = gen_rtx_REG (DImode, REGNO (operands[2]) + words - 1); 2444 operands[0] = gen_rtx_REG (DImode, REGNO (operands[2]) + words - 1);
2422 return "stmg\t%2,%0,%S1"; 2445 return "stmg\t%2,%0,%S1";
2423 } 2446 }
2695 (use (match_operand 2 "general_operand" "")) 2718 (use (match_operand 2 "general_operand" ""))
2696 (use (match_dup 3)) 2719 (use (match_dup 3))
2697 (clobber (reg:CC CC_REGNUM))])] 2720 (clobber (reg:CC CC_REGNUM))])]
2698 "" 2721 ""
2699 { 2722 {
2700 enum machine_mode dword_mode = word_mode == DImode ? TImode : DImode; 2723 enum machine_mode sreg_mode = TARGET_ZARCH ? DImode : SImode;
2701 rtx reg0 = gen_reg_rtx (dword_mode); 2724 enum machine_mode dreg_mode = TARGET_ZARCH ? TImode : DImode;
2702 rtx reg1 = gen_reg_rtx (dword_mode); 2725 rtx reg0 = gen_reg_rtx (dreg_mode);
2703 rtx addr0 = gen_lowpart (Pmode, gen_highpart (word_mode, reg0)); 2726 rtx reg1 = gen_reg_rtx (dreg_mode);
2704 rtx addr1 = gen_lowpart (Pmode, gen_highpart (word_mode, reg1)); 2727 rtx addr0 = gen_lowpart (Pmode, gen_highpart (sreg_mode, reg0));
2728 rtx addr1 = gen_lowpart (Pmode, gen_highpart (sreg_mode, reg1));
2705 rtx len0 = gen_lowpart (Pmode, reg0); 2729 rtx len0 = gen_lowpart (Pmode, reg0);
2706 rtx len1 = gen_lowpart (Pmode, reg1); 2730 rtx len1 = gen_lowpart (Pmode, reg1);
2707 2731
2708 emit_clobber (reg0); 2732 emit_clobber (reg0);
2709 emit_move_insn (addr0, force_operand (XEXP (operands[0], 0), NULL_RTX)); 2733 emit_move_insn (addr0, force_operand (XEXP (operands[0], 0), NULL_RTX));
2725 (set (mem:BLK (subreg:P (match_operand:<DBL> 2 "register_operand" "0") 0)) 2749 (set (mem:BLK (subreg:P (match_operand:<DBL> 2 "register_operand" "0") 0))
2726 (mem:BLK (subreg:P (match_operand:<DBL> 3 "register_operand" "1") 0))) 2750 (mem:BLK (subreg:P (match_operand:<DBL> 3 "register_operand" "1") 0)))
2727 (use (match_dup 2)) 2751 (use (match_dup 2))
2728 (use (match_dup 3)) 2752 (use (match_dup 3))
2729 (clobber (reg:CC CC_REGNUM))] 2753 (clobber (reg:CC CC_REGNUM))]
2730 "" 2754 "TARGET_64BIT || !TARGET_ZARCH"
2755 "mvcle\t%0,%1,0\;jo\t.-4"
2756 [(set_attr "length" "8")
2757 (set_attr "type" "vs")])
2758
2759 (define_insn "*movmem_long_31z"
2760 [(clobber (match_operand:TI 0 "register_operand" "=d"))
2761 (clobber (match_operand:TI 1 "register_operand" "=d"))
2762 (set (mem:BLK (subreg:SI (match_operand:TI 2 "register_operand" "0") 4))
2763 (mem:BLK (subreg:SI (match_operand:TI 3 "register_operand" "1") 4)))
2764 (use (match_dup 2))
2765 (use (match_dup 3))
2766 (clobber (reg:CC CC_REGNUM))]
2767 "!TARGET_64BIT && TARGET_ZARCH"
2731 "mvcle\t%0,%1,0\;jo\t.-4" 2768 "mvcle\t%0,%1,0\;jo\t.-4"
2732 [(set_attr "length" "8") 2769 [(set_attr "length" "8")
2733 (set_attr "type" "vs")]) 2770 (set_attr "type" "vs")])
2734 2771
2735 2772
2897 (use (match_operand 1 "general_operand" "")) 2934 (use (match_operand 1 "general_operand" ""))
2898 (use (match_dup 3)) 2935 (use (match_dup 3))
2899 (clobber (reg:CC CC_REGNUM))])] 2936 (clobber (reg:CC CC_REGNUM))])]
2900 "" 2937 ""
2901 { 2938 {
2902 enum machine_mode dword_mode = word_mode == DImode ? TImode : DImode; 2939 enum machine_mode sreg_mode = TARGET_ZARCH ? DImode : SImode;
2903 rtx reg0 = gen_reg_rtx (dword_mode); 2940 enum machine_mode dreg_mode = TARGET_ZARCH ? TImode : DImode;
2904 rtx reg1 = gen_reg_rtx (dword_mode); 2941 rtx reg0 = gen_reg_rtx (dreg_mode);
2905 rtx addr0 = gen_lowpart (Pmode, gen_highpart (word_mode, reg0)); 2942 rtx reg1 = gen_reg_rtx (dreg_mode);
2943 rtx addr0 = gen_lowpart (Pmode, gen_highpart (sreg_mode, reg0));
2906 rtx len0 = gen_lowpart (Pmode, reg0); 2944 rtx len0 = gen_lowpart (Pmode, reg0);
2907 2945
2908 emit_clobber (reg0); 2946 emit_clobber (reg0);
2909 emit_move_insn (addr0, force_operand (XEXP (operands[0], 0), NULL_RTX)); 2947 emit_move_insn (addr0, force_operand (XEXP (operands[0], 0), NULL_RTX));
2910 emit_move_insn (len0, operands[1]); 2948 emit_move_insn (len0, operands[1]);
2921 (set (mem:BLK (subreg:P (match_operand:<DBL> 3 "register_operand" "0") 0)) 2959 (set (mem:BLK (subreg:P (match_operand:<DBL> 3 "register_operand" "0") 0))
2922 (match_operand 2 "shift_count_or_setmem_operand" "Y")) 2960 (match_operand 2 "shift_count_or_setmem_operand" "Y"))
2923 (use (match_dup 3)) 2961 (use (match_dup 3))
2924 (use (match_operand:<DBL> 1 "register_operand" "d")) 2962 (use (match_operand:<DBL> 1 "register_operand" "d"))
2925 (clobber (reg:CC CC_REGNUM))] 2963 (clobber (reg:CC CC_REGNUM))]
2926 "" 2964 "TARGET_64BIT || !TARGET_ZARCH"
2927 "mvcle\t%0,%1,%Y2\;jo\t.-4" 2965 "mvcle\t%0,%1,%Y2\;jo\t.-4"
2928 [(set_attr "length" "8") 2966 [(set_attr "length" "8")
2929 (set_attr "type" "vs")]) 2967 (set_attr "type" "vs")])
2930 2968
2931 (define_insn "*setmem_long_and" 2969 (define_insn "*setmem_long_and"
2934 (and (match_operand 2 "shift_count_or_setmem_operand" "Y") 2972 (and (match_operand 2 "shift_count_or_setmem_operand" "Y")
2935 (match_operand 4 "const_int_operand" "n"))) 2973 (match_operand 4 "const_int_operand" "n")))
2936 (use (match_dup 3)) 2974 (use (match_dup 3))
2937 (use (match_operand:<DBL> 1 "register_operand" "d")) 2975 (use (match_operand:<DBL> 1 "register_operand" "d"))
2938 (clobber (reg:CC CC_REGNUM))] 2976 (clobber (reg:CC CC_REGNUM))]
2939 "(INTVAL (operands[4]) & 255) == 255" 2977 "(TARGET_64BIT || !TARGET_ZARCH) &&
2978 (INTVAL (operands[4]) & 255) == 255"
2940 "mvcle\t%0,%1,%Y2\;jo\t.-4" 2979 "mvcle\t%0,%1,%Y2\;jo\t.-4"
2941 [(set_attr "length" "8") 2980 [(set_attr "length" "8")
2942 (set_attr "type" "vs")]) 2981 (set_attr "type" "vs")])
2982
2983 (define_insn "*setmem_long_31z"
2984 [(clobber (match_operand:TI 0 "register_operand" "=d"))
2985 (set (mem:BLK (subreg:SI (match_operand:TI 3 "register_operand" "0") 4))
2986 (match_operand 2 "shift_count_or_setmem_operand" "Y"))
2987 (use (match_dup 3))
2988 (use (match_operand:TI 1 "register_operand" "d"))
2989 (clobber (reg:CC CC_REGNUM))]
2990 "!TARGET_64BIT && TARGET_ZARCH"
2991 "mvcle\t%0,%1,%Y2\;jo\t.-4"
2992 [(set_attr "length" "8")
2993 (set_attr "type" "vs")])
2994
2943 ; 2995 ;
2944 ; cmpmemM instruction pattern(s). 2996 ; cmpmemM instruction pattern(s).
2945 ; 2997 ;
2946 2998
2947 (define_expand "cmpmemsi" 2999 (define_expand "cmpmemsi"
3051 (match_operand:BLK 1 "memory_operand" ""))) 3103 (match_operand:BLK 1 "memory_operand" "")))
3052 (use (match_operand 2 "general_operand" "")) 3104 (use (match_operand 2 "general_operand" ""))
3053 (use (match_dup 3))])] 3105 (use (match_dup 3))])]
3054 "" 3106 ""
3055 { 3107 {
3056 enum machine_mode dword_mode = word_mode == DImode ? TImode : DImode; 3108 enum machine_mode sreg_mode = TARGET_ZARCH ? DImode : SImode;
3057 rtx reg0 = gen_reg_rtx (dword_mode); 3109 enum machine_mode dreg_mode = TARGET_ZARCH ? TImode : DImode;
3058 rtx reg1 = gen_reg_rtx (dword_mode); 3110 rtx reg0 = gen_reg_rtx (dreg_mode);
3059 rtx addr0 = gen_lowpart (Pmode, gen_highpart (word_mode, reg0)); 3111 rtx reg1 = gen_reg_rtx (dreg_mode);
3060 rtx addr1 = gen_lowpart (Pmode, gen_highpart (word_mode, reg1)); 3112 rtx addr0 = gen_lowpart (Pmode, gen_highpart (sreg_mode, reg0));
3113 rtx addr1 = gen_lowpart (Pmode, gen_highpart (sreg_mode, reg1));
3061 rtx len0 = gen_lowpart (Pmode, reg0); 3114 rtx len0 = gen_lowpart (Pmode, reg0);
3062 rtx len1 = gen_lowpart (Pmode, reg1); 3115 rtx len1 = gen_lowpart (Pmode, reg1);
3063 3116
3064 emit_clobber (reg0); 3117 emit_clobber (reg0);
3065 emit_move_insn (addr0, force_operand (XEXP (operands[0], 0), NULL_RTX)); 3118 emit_move_insn (addr0, force_operand (XEXP (operands[0], 0), NULL_RTX));
3081 (set (reg:CCU CC_REGNUM) 3134 (set (reg:CCU CC_REGNUM)
3082 (compare:CCU (mem:BLK (subreg:P (match_operand:<DBL> 2 "register_operand" "0") 0)) 3135 (compare:CCU (mem:BLK (subreg:P (match_operand:<DBL> 2 "register_operand" "0") 0))
3083 (mem:BLK (subreg:P (match_operand:<DBL> 3 "register_operand" "1") 0)))) 3136 (mem:BLK (subreg:P (match_operand:<DBL> 3 "register_operand" "1") 0))))
3084 (use (match_dup 2)) 3137 (use (match_dup 2))
3085 (use (match_dup 3))] 3138 (use (match_dup 3))]
3086 "" 3139 "TARGET_64BIT || !TARGET_ZARCH"
3087 "clcle\t%0,%1,0\;jo\t.-4" 3140 "clcle\t%0,%1,0\;jo\t.-4"
3088 [(set_attr "length" "8") 3141 [(set_attr "length" "8")
3089 (set_attr "type" "vs")]) 3142 (set_attr "type" "vs")])
3143
3144 (define_insn "*cmpmem_long_31z"
3145 [(clobber (match_operand:TI 0 "register_operand" "=d"))
3146 (clobber (match_operand:TI 1 "register_operand" "=d"))
3147 (set (reg:CCU CC_REGNUM)
3148 (compare:CCU (mem:BLK (subreg:SI (match_operand:TI 2 "register_operand" "0") 4))
3149 (mem:BLK (subreg:SI (match_operand:TI 3 "register_operand" "1") 4))))
3150 (use (match_dup 2))
3151 (use (match_dup 3))]
3152 "!TARGET_64BIT && TARGET_ZARCH"
3153 "clcle\t%0,%1,0\;jo\t.-4"
3154 [(set_attr "op_type" "NN")
3155 (set_attr "type" "vs")
3156 (set_attr "length" "8")])
3090 3157
3091 ; Convert CCUmode condition code to integer. 3158 ; Convert CCUmode condition code to integer.
3092 ; Result is zero if EQ, positive if LTU, negative if GTU. 3159 ; Result is zero if EQ, positive if LTU, negative if GTU.
3093 3160
3094 (define_insn_and_split "cmpint" 3161 (define_insn_and_split "cmpint"
3127 (define_insn_and_split "*cmpint_sign" 3194 (define_insn_and_split "*cmpint_sign"
3128 [(set (match_operand:DI 0 "register_operand" "=d") 3195 [(set (match_operand:DI 0 "register_operand" "=d")
3129 (sign_extend:DI (unspec:SI [(match_operand:CCU 1 "register_operand" "0")] 3196 (sign_extend:DI (unspec:SI [(match_operand:CCU 1 "register_operand" "0")]
3130 UNSPEC_CCU_TO_INT))) 3197 UNSPEC_CCU_TO_INT)))
3131 (clobber (reg:CC CC_REGNUM))] 3198 (clobber (reg:CC CC_REGNUM))]
3132 "TARGET_64BIT" 3199 "TARGET_ZARCH"
3133 "#" 3200 "#"
3134 "&& reload_completed" 3201 "&& reload_completed"
3135 [(set (match_dup 0) (ashift:DI (match_dup 0) (const_int 34))) 3202 [(set (match_dup 0) (ashift:DI (match_dup 0) (const_int 34)))
3136 (parallel 3203 (parallel
3137 [(set (match_dup 0) (ashiftrt:DI (match_dup 0) (const_int 62))) 3204 [(set (match_dup 0) (ashiftrt:DI (match_dup 0) (const_int 62)))
3144 UNSPEC_CCU_TO_INT) 0) 3211 UNSPEC_CCU_TO_INT) 0)
3145 (const_int 32)) (const_int 32)) 3212 (const_int 32)) (const_int 32))
3146 (const_int 0))) 3213 (const_int 0)))
3147 (set (match_operand:DI 0 "register_operand" "=d") 3214 (set (match_operand:DI 0 "register_operand" "=d")
3148 (sign_extend:DI (unspec:SI [(match_dup 1)] UNSPEC_CCU_TO_INT)))] 3215 (sign_extend:DI (unspec:SI [(match_dup 1)] UNSPEC_CCU_TO_INT)))]
3149 "s390_match_ccmode (insn, CCSmode) && TARGET_64BIT" 3216 "s390_match_ccmode (insn, CCSmode) && TARGET_ZARCH"
3150 "#" 3217 "#"
3151 "&& reload_completed" 3218 "&& reload_completed"
3152 [(set (match_dup 0) (ashift:DI (match_dup 0) (const_int 34))) 3219 [(set (match_dup 0) (ashift:DI (match_dup 0) (const_int 34)))
3153 (parallel 3220 (parallel
3154 [(set (match_dup 2) (match_dup 3)) 3221 [(set (match_dup 2) (match_dup 3))
3179 (define_insn "*sethighpartdi_64" 3246 (define_insn "*sethighpartdi_64"
3180 [(set (match_operand:DI 0 "register_operand" "=d") 3247 [(set (match_operand:DI 0 "register_operand" "=d")
3181 (unspec:DI [(match_operand:BLK 1 "s_operand" "QS") 3248 (unspec:DI [(match_operand:BLK 1 "s_operand" "QS")
3182 (match_operand 2 "const_int_operand" "n")] UNSPEC_ICM)) 3249 (match_operand 2 "const_int_operand" "n")] UNSPEC_ICM))
3183 (clobber (reg:CC CC_REGNUM))] 3250 (clobber (reg:CC CC_REGNUM))]
3184 "TARGET_64BIT" 3251 "TARGET_ZARCH"
3185 "icmh\t%0,%2,%S1" 3252 "icmh\t%0,%2,%S1"
3186 [(set_attr "op_type" "RSY") 3253 [(set_attr "op_type" "RSY")
3187 (set_attr "z10prop" "z10_super")]) 3254 (set_attr "z10prop" "z10_super")])
3188 3255
3189 (define_insn "*sethighpartdi_31" 3256 (define_insn "*sethighpartdi_31"
3190 [(set (match_operand:DI 0 "register_operand" "=d,d") 3257 [(set (match_operand:DI 0 "register_operand" "=d,d")
3191 (unspec:DI [(match_operand:BLK 1 "s_operand" "Q,S") 3258 (unspec:DI [(match_operand:BLK 1 "s_operand" "Q,S")
3192 (match_operand 2 "const_int_operand" "n,n")] UNSPEC_ICM)) 3259 (match_operand 2 "const_int_operand" "n,n")] UNSPEC_ICM))
3193 (clobber (reg:CC CC_REGNUM))] 3260 (clobber (reg:CC CC_REGNUM))]
3194 "!TARGET_64BIT" 3261 "!TARGET_ZARCH"
3195 "@ 3262 "@
3196 icm\t%0,%2,%S1 3263 icm\t%0,%2,%S1
3197 icmy\t%0,%2,%S1" 3264 icmy\t%0,%2,%S1"
3198 [(set_attr "op_type" "RS,RSY") 3265 [(set_attr "op_type" "RS,RSY")
3199 (set_attr "z10prop" "z10_super_E1,z10_super_E1")]) 3266 (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
3345 return "rosbg\t%0,%1,%b4,%b5,%b6"; 3412 return "rosbg\t%0,%1,%b4,%b5,%b6";
3346 } 3413 }
3347 [(set_attr "op_type" "RIE")]) 3414 [(set_attr "op_type" "RIE")])
3348 3415
3349 (define_insn "*insv<mode>_mem_reg" 3416 (define_insn "*insv<mode>_mem_reg"
3350 [(set (zero_extract:P (match_operand:QI 0 "memory_operand" "+Q,S") 3417 [(set (zero_extract:W (match_operand:QI 0 "memory_operand" "+Q,S")
3351 (match_operand 1 "const_int_operand" "n,n") 3418 (match_operand 1 "const_int_operand" "n,n")
3352 (const_int 0)) 3419 (const_int 0))
3353 (match_operand:P 2 "register_operand" "d,d"))] 3420 (match_operand:W 2 "register_operand" "d,d"))]
3354 "INTVAL (operands[1]) > 0 3421 "INTVAL (operands[1]) > 0
3355 && INTVAL (operands[1]) <= GET_MODE_BITSIZE (SImode) 3422 && INTVAL (operands[1]) <= GET_MODE_BITSIZE (SImode)
3356 && INTVAL (operands[1]) % BITS_PER_UNIT == 0" 3423 && INTVAL (operands[1]) % BITS_PER_UNIT == 0"
3357 { 3424 {
3358 int size = INTVAL (operands[1]) / BITS_PER_UNIT; 3425 int size = INTVAL (operands[1]) / BITS_PER_UNIT;
3368 [(set (zero_extract:DI (match_operand:QI 0 "memory_operand" "+QS") 3435 [(set (zero_extract:DI (match_operand:QI 0 "memory_operand" "+QS")
3369 (match_operand 1 "const_int_operand" "n") 3436 (match_operand 1 "const_int_operand" "n")
3370 (const_int 0)) 3437 (const_int 0))
3371 (lshiftrt:DI (match_operand:DI 2 "register_operand" "d") 3438 (lshiftrt:DI (match_operand:DI 2 "register_operand" "d")
3372 (const_int 32)))] 3439 (const_int 32)))]
3373 "TARGET_64BIT 3440 "TARGET_ZARCH
3374 && INTVAL (operands[1]) > 0 3441 && INTVAL (operands[1]) > 0
3375 && INTVAL (operands[1]) <= GET_MODE_BITSIZE (SImode) 3442 && INTVAL (operands[1]) <= GET_MODE_BITSIZE (SImode)
3376 && INTVAL (operands[1]) % BITS_PER_UNIT == 0" 3443 && INTVAL (operands[1]) % BITS_PER_UNIT == 0"
3377 { 3444 {
3378 int size = INTVAL (operands[1]) / BITS_PER_UNIT; 3445 int size = INTVAL (operands[1]) / BITS_PER_UNIT;
3381 return "stcmh\t%2,%1,%S0"; 3448 return "stcmh\t%2,%1,%S0";
3382 } 3449 }
3383 [(set_attr "op_type" "RSY") 3450 [(set_attr "op_type" "RSY")
3384 (set_attr "z10prop" "z10_super")]) 3451 (set_attr "z10prop" "z10_super")])
3385 3452
3386 (define_insn "*insv<mode>_reg_imm" 3453 (define_insn "*insvdi_reg_imm"
3387 [(set (zero_extract:P (match_operand:P 0 "register_operand" "+d") 3454 [(set (zero_extract:DI (match_operand:DI 0 "register_operand" "+d")
3388 (const_int 16) 3455 (const_int 16)
3389 (match_operand 1 "const_int_operand" "n")) 3456 (match_operand 1 "const_int_operand" "n"))
3390 (match_operand:P 2 "const_int_operand" "n"))] 3457 (match_operand:DI 2 "const_int_operand" "n"))]
3391 "TARGET_ZARCH 3458 "TARGET_ZARCH
3392 && INTVAL (operands[1]) >= 0 3459 && INTVAL (operands[1]) >= 0
3393 && INTVAL (operands[1]) < BITS_PER_WORD 3460 && INTVAL (operands[1]) < BITS_PER_WORD
3394 && INTVAL (operands[1]) % 16 == 0" 3461 && INTVAL (operands[1]) % 16 == 0"
3395 { 3462 {
3435 (define_expand "extendsidi2" 3502 (define_expand "extendsidi2"
3436 [(set (match_operand:DI 0 "register_operand" "") 3503 [(set (match_operand:DI 0 "register_operand" "")
3437 (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")))] 3504 (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")))]
3438 "" 3505 ""
3439 { 3506 {
3440 if (!TARGET_64BIT) 3507 if (!TARGET_ZARCH)
3441 { 3508 {
3442 emit_clobber (operands[0]); 3509 emit_clobber (operands[0]);
3443 emit_move_insn (gen_highpart (SImode, operands[0]), operands[1]); 3510 emit_move_insn (gen_highpart (SImode, operands[0]), operands[1]);
3444 emit_move_insn (gen_lowpart (SImode, operands[0]), const0_rtx); 3511 emit_move_insn (gen_lowpart (SImode, operands[0]), const0_rtx);
3445 emit_insn (gen_ashrdi3 (operands[0], operands[0], GEN_INT (32))); 3512 emit_insn (gen_ashrdi3 (operands[0], operands[0], GEN_INT (32)));
3448 }) 3515 })
3449 3516
3450 (define_insn "*extendsidi2" 3517 (define_insn "*extendsidi2"
3451 [(set (match_operand:DI 0 "register_operand" "=d,d,d") 3518 [(set (match_operand:DI 0 "register_operand" "=d,d,d")
3452 (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,RT,b")))] 3519 (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,RT,b")))]
3453 "TARGET_64BIT" 3520 "TARGET_ZARCH"
3454 "@ 3521 "@
3455 lgfr\t%0,%1 3522 lgfr\t%0,%1
3456 lgf\t%0,%1 3523 lgf\t%0,%1
3457 lgfrl\t%0,%1" 3524 lgfrl\t%0,%1"
3458 [(set_attr "op_type" "RRE,RXY,RIL") 3525 [(set_attr "op_type" "RRE,RXY,RIL")
3467 (define_expand "extend<HQI:mode><DSI:mode>2" 3534 (define_expand "extend<HQI:mode><DSI:mode>2"
3468 [(set (match_operand:DSI 0 "register_operand" "") 3535 [(set (match_operand:DSI 0 "register_operand" "")
3469 (sign_extend:DSI (match_operand:HQI 1 "nonimmediate_operand" "")))] 3536 (sign_extend:DSI (match_operand:HQI 1 "nonimmediate_operand" "")))]
3470 "" 3537 ""
3471 { 3538 {
3472 if (<DSI:MODE>mode == DImode && !TARGET_64BIT) 3539 if (<DSI:MODE>mode == DImode && !TARGET_ZARCH)
3473 { 3540 {
3474 rtx tmp = gen_reg_rtx (SImode); 3541 rtx tmp = gen_reg_rtx (SImode);
3475 emit_insn (gen_extend<HQI:mode>si2 (tmp, operands[1])); 3542 emit_insn (gen_extend<HQI:mode>si2 (tmp, operands[1]));
3476 emit_insn (gen_extendsidi2 (operands[0], tmp)); 3543 emit_insn (gen_extendsidi2 (operands[0], tmp));
3477 DONE; 3544 DONE;
3493 ; 3560 ;
3494 3561
3495 (define_insn "*extendhidi2_extimm" 3562 (define_insn "*extendhidi2_extimm"
3496 [(set (match_operand:DI 0 "register_operand" "=d,d,d") 3563 [(set (match_operand:DI 0 "register_operand" "=d,d,d")
3497 (sign_extend:DI (match_operand:HI 1 "general_operand" "d,RT,b")))] 3564 (sign_extend:DI (match_operand:HI 1 "general_operand" "d,RT,b")))]
3498 "TARGET_64BIT && TARGET_EXTIMM" 3565 "TARGET_ZARCH && TARGET_EXTIMM"
3499 "@ 3566 "@
3500 lghr\t%0,%1 3567 lghr\t%0,%1
3501 lgh\t%0,%1 3568 lgh\t%0,%1
3502 lghrl\t%0,%1" 3569 lghrl\t%0,%1"
3503 [(set_attr "op_type" "RRE,RXY,RIL") 3570 [(set_attr "op_type" "RRE,RXY,RIL")
3506 (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1")]) 3573 (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1")])
3507 3574
3508 (define_insn "*extendhidi2" 3575 (define_insn "*extendhidi2"
3509 [(set (match_operand:DI 0 "register_operand" "=d") 3576 [(set (match_operand:DI 0 "register_operand" "=d")
3510 (sign_extend:DI (match_operand:HI 1 "memory_operand" "RT")))] 3577 (sign_extend:DI (match_operand:HI 1 "memory_operand" "RT")))]
3511 "TARGET_64BIT" 3578 "TARGET_ZARCH"
3512 "lgh\t%0,%1" 3579 "lgh\t%0,%1"
3513 [(set_attr "op_type" "RXY") 3580 [(set_attr "op_type" "RXY")
3514 (set_attr "z10prop" "z10_super_E1")]) 3581 (set_attr "z10prop" "z10_super_E1")])
3515 3582
3516 ; 3583 ;
3592 (define_expand "zero_extendsidi2" 3659 (define_expand "zero_extendsidi2"
3593 [(set (match_operand:DI 0 "register_operand" "") 3660 [(set (match_operand:DI 0 "register_operand" "")
3594 (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")))] 3661 (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")))]
3595 "" 3662 ""
3596 { 3663 {
3597 if (!TARGET_64BIT) 3664 if (!TARGET_ZARCH)
3598 { 3665 {
3599 emit_clobber (operands[0]); 3666 emit_clobber (operands[0]);
3600 emit_move_insn (gen_lowpart (SImode, operands[0]), operands[1]); 3667 emit_move_insn (gen_lowpart (SImode, operands[0]), operands[1]);
3601 emit_move_insn (gen_highpart (SImode, operands[0]), const0_rtx); 3668 emit_move_insn (gen_highpart (SImode, operands[0]), const0_rtx);
3602 DONE; 3669 DONE;
3604 }) 3671 })
3605 3672
3606 (define_insn "*zero_extendsidi2" 3673 (define_insn "*zero_extendsidi2"
3607 [(set (match_operand:DI 0 "register_operand" "=d,d,d") 3674 [(set (match_operand:DI 0 "register_operand" "=d,d,d")
3608 (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,RT,b")))] 3675 (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,RT,b")))]
3609 "TARGET_64BIT" 3676 "TARGET_ZARCH"
3610 "@ 3677 "@
3611 llgfr\t%0,%1 3678 llgfr\t%0,%1
3612 llgf\t%0,%1 3679 llgf\t%0,%1
3613 llgfrl\t%0,%1" 3680 llgfrl\t%0,%1"
3614 [(set_attr "op_type" "RRE,RXY,RIL") 3681 [(set_attr "op_type" "RRE,RXY,RIL")
3622 3689
3623 (define_insn "*llgt_sidi" 3690 (define_insn "*llgt_sidi"
3624 [(set (match_operand:DI 0 "register_operand" "=d") 3691 [(set (match_operand:DI 0 "register_operand" "=d")
3625 (and:DI (subreg:DI (match_operand:SI 1 "memory_operand" "RT") 0) 3692 (and:DI (subreg:DI (match_operand:SI 1 "memory_operand" "RT") 0)
3626 (const_int 2147483647)))] 3693 (const_int 2147483647)))]
3627 "TARGET_64BIT" 3694 "TARGET_ZARCH"
3628 "llgt\t%0,%1" 3695 "llgt\t%0,%1"
3629 [(set_attr "op_type" "RXE") 3696 [(set_attr "op_type" "RXE")
3630 (set_attr "z10prop" "z10_super_E1")]) 3697 (set_attr "z10prop" "z10_super_E1")])
3631 3698
3632 (define_insn_and_split "*llgt_sidi_split" 3699 (define_insn_and_split "*llgt_sidi_split"
3633 [(set (match_operand:DI 0 "register_operand" "=d") 3700 [(set (match_operand:DI 0 "register_operand" "=d")
3634 (and:DI (subreg:DI (match_operand:SI 1 "memory_operand" "RT") 0) 3701 (and:DI (subreg:DI (match_operand:SI 1 "memory_operand" "RT") 0)
3635 (const_int 2147483647))) 3702 (const_int 2147483647)))
3636 (clobber (reg:CC CC_REGNUM))] 3703 (clobber (reg:CC CC_REGNUM))]
3637 "TARGET_64BIT" 3704 "TARGET_ZARCH"
3638 "#" 3705 "#"
3639 "&& reload_completed" 3706 "&& reload_completed"
3640 [(set (match_dup 0) 3707 [(set (match_dup 0)
3641 (and:DI (subreg:DI (match_dup 1) 0) 3708 (and:DI (subreg:DI (match_dup 1) 0)
3642 (const_int 2147483647)))] 3709 (const_int 2147483647)))]
3655 3722
3656 (define_insn "*llgt_didi" 3723 (define_insn "*llgt_didi"
3657 [(set (match_operand:DI 0 "register_operand" "=d,d") 3724 [(set (match_operand:DI 0 "register_operand" "=d,d")
3658 (and:DI (match_operand:DI 1 "nonimmediate_operand" "d,o") 3725 (and:DI (match_operand:DI 1 "nonimmediate_operand" "d,o")
3659 (const_int 2147483647)))] 3726 (const_int 2147483647)))]
3660 "TARGET_64BIT" 3727 "TARGET_ZARCH"
3661 "@ 3728 "@
3662 llgtr\t%0,%1 3729 llgtr\t%0,%1
3663 llgt\t%0,%N1" 3730 llgt\t%0,%N1"
3664 [(set_attr "op_type" "RRE,RXE") 3731 [(set_attr "op_type" "RRE,RXE")
3665 (set_attr "z10prop" "z10_super_E1,z10_super_E1")]) 3732 (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
3666 3733
3667 (define_split 3734 (define_split
3668 [(set (match_operand:GPR 0 "register_operand" "") 3735 [(set (match_operand:DSI 0 "register_operand" "")
3669 (and:GPR (match_operand:GPR 1 "nonimmediate_operand" "") 3736 (and:DSI (match_operand:DSI 1 "nonimmediate_operand" "")
3670 (const_int 2147483647))) 3737 (const_int 2147483647)))
3671 (clobber (reg:CC CC_REGNUM))] 3738 (clobber (reg:CC CC_REGNUM))]
3672 "TARGET_ZARCH && reload_completed" 3739 "TARGET_ZARCH && reload_completed"
3673 [(set (match_dup 0) 3740 [(set (match_dup 0)
3674 (and:GPR (match_dup 1) 3741 (and:DSI (match_dup 1)
3675 (const_int 2147483647)))] 3742 (const_int 2147483647)))]
3676 "") 3743 "")
3677 3744
3678 ; 3745 ;
3679 ; zero_extend(hi|qi)(si|di)2 instruction pattern(s). 3746 ; zero_extend(hi|qi)(si|di)2 instruction pattern(s).
3682 (define_expand "zero_extend<mode>di2" 3749 (define_expand "zero_extend<mode>di2"
3683 [(set (match_operand:DI 0 "register_operand" "") 3750 [(set (match_operand:DI 0 "register_operand" "")
3684 (zero_extend:DI (match_operand:HQI 1 "nonimmediate_operand" "")))] 3751 (zero_extend:DI (match_operand:HQI 1 "nonimmediate_operand" "")))]
3685 "" 3752 ""
3686 { 3753 {
3687 if (!TARGET_64BIT) 3754 if (!TARGET_ZARCH)
3688 { 3755 {
3689 rtx tmp = gen_reg_rtx (SImode); 3756 rtx tmp = gen_reg_rtx (SImode);
3690 emit_insn (gen_zero_extend<mode>si2 (tmp, operands[1])); 3757 emit_insn (gen_zero_extend<mode>si2 (tmp, operands[1]));
3691 emit_insn (gen_zero_extendsidi2 (operands[0], tmp)); 3758 emit_insn (gen_zero_extendsidi2 (operands[0], tmp));
3692 DONE; 3759 DONE;
3934 ; 4001 ;
3935 4002
3936 (define_expand "fix_trunc<mode>di2" 4003 (define_expand "fix_trunc<mode>di2"
3937 [(set (match_operand:DI 0 "register_operand" "") 4004 [(set (match_operand:DI 0 "register_operand" "")
3938 (fix:DI (match_operand:DFP 1 "nonimmediate_operand" "")))] 4005 (fix:DI (match_operand:DFP 1 "nonimmediate_operand" "")))]
3939 "TARGET_64BIT && TARGET_HARD_DFP" 4006 "TARGET_ZARCH && TARGET_HARD_DFP"
3940 { 4007 {
3941 operands[1] = force_reg (<MODE>mode, operands[1]); 4008 operands[1] = force_reg (<MODE>mode, operands[1]);
3942 emit_insn (gen_fix_trunc<mode>di2_dfp (operands[0], operands[1], 4009 emit_insn (gen_fix_trunc<mode>di2_dfp (operands[0], operands[1],
3943 GEN_INT (9))); 4010 GEN_INT (9)));
3944 DONE; 4011 DONE;
3948 (define_insn "fix_trunc<DFP:mode>di2_dfp" 4015 (define_insn "fix_trunc<DFP:mode>di2_dfp"
3949 [(set (match_operand:DI 0 "register_operand" "=d") 4016 [(set (match_operand:DI 0 "register_operand" "=d")
3950 (fix:DI (match_operand:DFP 1 "register_operand" "f"))) 4017 (fix:DI (match_operand:DFP 1 "register_operand" "f")))
3951 (unspec:DI [(match_operand:DI 2 "immediate_operand" "K")] UNSPEC_ROUND) 4018 (unspec:DI [(match_operand:DI 2 "immediate_operand" "K")] UNSPEC_ROUND)
3952 (clobber (reg:CC CC_REGNUM))] 4019 (clobber (reg:CC CC_REGNUM))]
3953 "TARGET_64BIT && TARGET_HARD_DFP" 4020 "TARGET_ZARCH && TARGET_HARD_DFP"
3954 "cg<DFP:xde>tr\t%0,%h2,%1" 4021 "cg<DFP:xde>tr\t%0,%h2,%1"
3955 [(set_attr "op_type" "RRF") 4022 [(set_attr "op_type" "RRF")
3956 (set_attr "type" "ftoidfp")]) 4023 (set_attr "type" "ftoidfp")])
3957 4024
3958 4025
3975 4042
3976 ; cxgbr, cdgbr, cegbr, cxgtr, cdgtr 4043 ; cxgbr, cdgbr, cegbr, cxgtr, cdgtr
3977 (define_insn "floatdi<mode>2" 4044 (define_insn "floatdi<mode>2"
3978 [(set (match_operand:FP 0 "register_operand" "=f") 4045 [(set (match_operand:FP 0 "register_operand" "=f")
3979 (float:FP (match_operand:DI 1 "register_operand" "d")))] 4046 (float:FP (match_operand:DI 1 "register_operand" "d")))]
3980 "TARGET_64BIT && TARGET_HARD_FLOAT" 4047 "TARGET_ZARCH && TARGET_HARD_FLOAT"
3981 "c<xde>g<bt>r\t%0,%1" 4048 "c<xde>g<bt>r\t%0,%1"
3982 [(set_attr "op_type" "RRE") 4049 [(set_attr "op_type" "RRE")
3983 (set_attr "type" "itof<mode>" )]) 4050 (set_attr "type" "itof<mode>" )])
3984 4051
3985 ; cxfbr, cdfbr, cefbr 4052 ; cxfbr, cdfbr, cefbr
4217 (define_insn_and_split "addti3" 4284 (define_insn_and_split "addti3"
4218 [(set (match_operand:TI 0 "register_operand" "=&d") 4285 [(set (match_operand:TI 0 "register_operand" "=&d")
4219 (plus:TI (match_operand:TI 1 "nonimmediate_operand" "%0") 4286 (plus:TI (match_operand:TI 1 "nonimmediate_operand" "%0")
4220 (match_operand:TI 2 "general_operand" "do") ) ) 4287 (match_operand:TI 2 "general_operand" "do") ) )
4221 (clobber (reg:CC CC_REGNUM))] 4288 (clobber (reg:CC CC_REGNUM))]
4222 "TARGET_64BIT" 4289 "TARGET_ZARCH"
4223 "#" 4290 "#"
4224 "&& reload_completed" 4291 "&& reload_completed"
4225 [(parallel 4292 [(parallel
4226 [(set (reg:CCL1 CC_REGNUM) 4293 [(set (reg:CCL1 CC_REGNUM)
4227 (compare:CCL1 (plus:DI (match_dup 7) (match_dup 8)) 4294 (compare:CCL1 (plus:DI (match_dup 7) (match_dup 8))
4255 (define_insn "*adddi3_sign" 4322 (define_insn "*adddi3_sign"
4256 [(set (match_operand:DI 0 "register_operand" "=d,d") 4323 [(set (match_operand:DI 0 "register_operand" "=d,d")
4257 (plus:DI (sign_extend:DI (match_operand:SI 2 "general_operand" "d,RT")) 4324 (plus:DI (sign_extend:DI (match_operand:SI 2 "general_operand" "d,RT"))
4258 (match_operand:DI 1 "register_operand" "0,0"))) 4325 (match_operand:DI 1 "register_operand" "0,0")))
4259 (clobber (reg:CC CC_REGNUM))] 4326 (clobber (reg:CC CC_REGNUM))]
4260 "TARGET_64BIT" 4327 "TARGET_ZARCH"
4261 "@ 4328 "@
4262 agfr\t%0,%2 4329 agfr\t%0,%2
4263 agf\t%0,%2" 4330 agf\t%0,%2"
4264 [(set_attr "op_type" "RRE,RXY")]) 4331 [(set_attr "op_type" "RRE,RXY")])
4265 4332
4268 (compare (plus:DI (zero_extend:DI (match_operand:SI 2 "general_operand" "d,RT")) 4335 (compare (plus:DI (zero_extend:DI (match_operand:SI 2 "general_operand" "d,RT"))
4269 (match_operand:DI 1 "register_operand" "0,0")) 4336 (match_operand:DI 1 "register_operand" "0,0"))
4270 (const_int 0))) 4337 (const_int 0)))
4271 (set (match_operand:DI 0 "register_operand" "=d,d") 4338 (set (match_operand:DI 0 "register_operand" "=d,d")
4272 (plus:DI (zero_extend:DI (match_dup 2)) (match_dup 1)))] 4339 (plus:DI (zero_extend:DI (match_dup 2)) (match_dup 1)))]
4273 "s390_match_ccmode (insn, CCLmode) && TARGET_64BIT" 4340 "s390_match_ccmode (insn, CCLmode) && TARGET_ZARCH"
4274 "@ 4341 "@
4275 algfr\t%0,%2 4342 algfr\t%0,%2
4276 algf\t%0,%2" 4343 algf\t%0,%2"
4277 [(set_attr "op_type" "RRE,RXY") 4344 [(set_attr "op_type" "RRE,RXY")
4278 (set_attr "z10prop" "z10_super_E1,z10_super_E1")]) 4345 (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
4281 [(set (reg CC_REGNUM) 4348 [(set (reg CC_REGNUM)
4282 (compare (plus:DI (zero_extend:DI (match_operand:SI 2 "general_operand" "d,RT")) 4349 (compare (plus:DI (zero_extend:DI (match_operand:SI 2 "general_operand" "d,RT"))
4283 (match_operand:DI 1 "register_operand" "0,0")) 4350 (match_operand:DI 1 "register_operand" "0,0"))
4284 (const_int 0))) 4351 (const_int 0)))
4285 (clobber (match_scratch:DI 0 "=d,d"))] 4352 (clobber (match_scratch:DI 0 "=d,d"))]
4286 "s390_match_ccmode (insn, CCLmode) && TARGET_64BIT" 4353 "s390_match_ccmode (insn, CCLmode) && TARGET_ZARCH"
4287 "@ 4354 "@
4288 algfr\t%0,%2 4355 algfr\t%0,%2
4289 algf\t%0,%2" 4356 algf\t%0,%2"
4290 [(set_attr "op_type" "RRE,RXY") 4357 [(set_attr "op_type" "RRE,RXY")
4291 (set_attr "z10prop" "z10_super_E1,z10_super_E1")]) 4358 (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
4293 (define_insn "*adddi3_zero" 4360 (define_insn "*adddi3_zero"
4294 [(set (match_operand:DI 0 "register_operand" "=d,d") 4361 [(set (match_operand:DI 0 "register_operand" "=d,d")
4295 (plus:DI (zero_extend:DI (match_operand:SI 2 "general_operand" "d,RT")) 4362 (plus:DI (zero_extend:DI (match_operand:SI 2 "general_operand" "d,RT"))
4296 (match_operand:DI 1 "register_operand" "0,0"))) 4363 (match_operand:DI 1 "register_operand" "0,0")))
4297 (clobber (reg:CC CC_REGNUM))] 4364 (clobber (reg:CC CC_REGNUM))]
4298 "TARGET_64BIT" 4365 "TARGET_ZARCH"
4299 "@ 4366 "@
4300 algfr\t%0,%2 4367 algfr\t%0,%2
4301 algf\t%0,%2" 4368 algf\t%0,%2"
4302 [(set_attr "op_type" "RRE,RXY") 4369 [(set_attr "op_type" "RRE,RXY")
4303 (set_attr "z10prop" "z10_super_E1,z10_super_E1")]) 4370 (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
4305 (define_insn_and_split "*adddi3_31z" 4372 (define_insn_and_split "*adddi3_31z"
4306 [(set (match_operand:DI 0 "nonimmediate_operand" "=&d") 4373 [(set (match_operand:DI 0 "nonimmediate_operand" "=&d")
4307 (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0") 4374 (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0")
4308 (match_operand:DI 2 "general_operand" "do") ) ) 4375 (match_operand:DI 2 "general_operand" "do") ) )
4309 (clobber (reg:CC CC_REGNUM))] 4376 (clobber (reg:CC CC_REGNUM))]
4310 "!TARGET_64BIT && TARGET_CPU_ZARCH" 4377 "!TARGET_ZARCH && TARGET_CPU_ZARCH"
4311 "#" 4378 "#"
4312 "&& reload_completed" 4379 "&& reload_completed"
4313 [(parallel 4380 [(parallel
4314 [(set (reg:CCL1 CC_REGNUM) 4381 [(set (reg:CCL1 CC_REGNUM)
4315 (compare:CCL1 (plus:SI (match_dup 7) (match_dup 8)) 4382 (compare:CCL1 (plus:SI (match_dup 7) (match_dup 8))
4625 (define_insn_and_split "subti3" 4692 (define_insn_and_split "subti3"
4626 [(set (match_operand:TI 0 "register_operand" "=&d") 4693 [(set (match_operand:TI 0 "register_operand" "=&d")
4627 (minus:TI (match_operand:TI 1 "register_operand" "0") 4694 (minus:TI (match_operand:TI 1 "register_operand" "0")
4628 (match_operand:TI 2 "general_operand" "do") ) ) 4695 (match_operand:TI 2 "general_operand" "do") ) )
4629 (clobber (reg:CC CC_REGNUM))] 4696 (clobber (reg:CC CC_REGNUM))]
4630 "TARGET_64BIT" 4697 "TARGET_ZARCH"
4631 "#" 4698 "#"
4632 "&& reload_completed" 4699 "&& reload_completed"
4633 [(parallel 4700 [(parallel
4634 [(set (reg:CCL2 CC_REGNUM) 4701 [(set (reg:CCL2 CC_REGNUM)
4635 (compare:CCL2 (minus:DI (match_dup 7) (match_dup 8)) 4702 (compare:CCL2 (minus:DI (match_dup 7) (match_dup 8))
4662 (define_insn "*subdi3_sign" 4729 (define_insn "*subdi3_sign"
4663 [(set (match_operand:DI 0 "register_operand" "=d,d") 4730 [(set (match_operand:DI 0 "register_operand" "=d,d")
4664 (minus:DI (match_operand:DI 1 "register_operand" "0,0") 4731 (minus:DI (match_operand:DI 1 "register_operand" "0,0")
4665 (sign_extend:DI (match_operand:SI 2 "general_operand" "d,RT")))) 4732 (sign_extend:DI (match_operand:SI 2 "general_operand" "d,RT"))))
4666 (clobber (reg:CC CC_REGNUM))] 4733 (clobber (reg:CC CC_REGNUM))]
4667 "TARGET_64BIT" 4734 "TARGET_ZARCH"
4668 "@ 4735 "@
4669 sgfr\t%0,%2 4736 sgfr\t%0,%2
4670 sgf\t%0,%2" 4737 sgf\t%0,%2"
4671 [(set_attr "op_type" "RRE,RXY") 4738 [(set_attr "op_type" "RRE,RXY")
4672 (set_attr "z10prop" "z10_c,*")]) 4739 (set_attr "z10prop" "z10_c,*")])
4676 (compare (minus:DI (match_operand:DI 1 "register_operand" "0,0") 4743 (compare (minus:DI (match_operand:DI 1 "register_operand" "0,0")
4677 (zero_extend:DI (match_operand:SI 2 "general_operand" "d,RT"))) 4744 (zero_extend:DI (match_operand:SI 2 "general_operand" "d,RT")))
4678 (const_int 0))) 4745 (const_int 0)))
4679 (set (match_operand:DI 0 "register_operand" "=d,d") 4746 (set (match_operand:DI 0 "register_operand" "=d,d")
4680 (minus:DI (match_dup 1) (zero_extend:DI (match_dup 2))))] 4747 (minus:DI (match_dup 1) (zero_extend:DI (match_dup 2))))]
4681 "s390_match_ccmode (insn, CCLmode) && TARGET_64BIT" 4748 "s390_match_ccmode (insn, CCLmode) && TARGET_ZARCH"
4682 "@ 4749 "@
4683 slgfr\t%0,%2 4750 slgfr\t%0,%2
4684 slgf\t%0,%2" 4751 slgf\t%0,%2"
4685 [(set_attr "op_type" "RRE,RXY") 4752 [(set_attr "op_type" "RRE,RXY")
4686 (set_attr "z10prop" "z10_super_c_E1,z10_super_E1")]) 4753 (set_attr "z10prop" "z10_super_c_E1,z10_super_E1")])
4689 [(set (reg CC_REGNUM) 4756 [(set (reg CC_REGNUM)
4690 (compare (minus:DI (match_operand:DI 1 "register_operand" "0,0") 4757 (compare (minus:DI (match_operand:DI 1 "register_operand" "0,0")
4691 (zero_extend:DI (match_operand:SI 2 "general_operand" "d,RT"))) 4758 (zero_extend:DI (match_operand:SI 2 "general_operand" "d,RT")))
4692 (const_int 0))) 4759 (const_int 0)))
4693 (clobber (match_scratch:DI 0 "=d,d"))] 4760 (clobber (match_scratch:DI 0 "=d,d"))]
4694 "s390_match_ccmode (insn, CCLmode) && TARGET_64BIT" 4761 "s390_match_ccmode (insn, CCLmode) && TARGET_ZARCH"
4695 "@ 4762 "@
4696 slgfr\t%0,%2 4763 slgfr\t%0,%2
4697 slgf\t%0,%2" 4764 slgf\t%0,%2"
4698 [(set_attr "op_type" "RRE,RXY") 4765 [(set_attr "op_type" "RRE,RXY")
4699 (set_attr "z10prop" "z10_super_c_E1,z10_super_E1")]) 4766 (set_attr "z10prop" "z10_super_c_E1,z10_super_E1")])
4701 (define_insn "*subdi3_zero" 4768 (define_insn "*subdi3_zero"
4702 [(set (match_operand:DI 0 "register_operand" "=d,d") 4769 [(set (match_operand:DI 0 "register_operand" "=d,d")
4703 (minus:DI (match_operand:DI 1 "register_operand" "0,0") 4770 (minus:DI (match_operand:DI 1 "register_operand" "0,0")
4704 (zero_extend:DI (match_operand:SI 2 "general_operand" "d,RT")))) 4771 (zero_extend:DI (match_operand:SI 2 "general_operand" "d,RT"))))
4705 (clobber (reg:CC CC_REGNUM))] 4772 (clobber (reg:CC CC_REGNUM))]
4706 "TARGET_64BIT" 4773 "TARGET_ZARCH"
4707 "@ 4774 "@
4708 slgfr\t%0,%2 4775 slgfr\t%0,%2
4709 slgf\t%0,%2" 4776 slgf\t%0,%2"
4710 [(set_attr "op_type" "RRE,RXY") 4777 [(set_attr "op_type" "RRE,RXY")
4711 (set_attr "z10prop" "z10_super_c_E1,z10_super_E1")]) 4778 (set_attr "z10prop" "z10_super_c_E1,z10_super_E1")])
4713 (define_insn_and_split "*subdi3_31z" 4780 (define_insn_and_split "*subdi3_31z"
4714 [(set (match_operand:DI 0 "register_operand" "=&d") 4781 [(set (match_operand:DI 0 "register_operand" "=&d")
4715 (minus:DI (match_operand:DI 1 "register_operand" "0") 4782 (minus:DI (match_operand:DI 1 "register_operand" "0")
4716 (match_operand:DI 2 "general_operand" "do") ) ) 4783 (match_operand:DI 2 "general_operand" "do") ) )
4717 (clobber (reg:CC CC_REGNUM))] 4784 (clobber (reg:CC CC_REGNUM))]
4718 "!TARGET_64BIT && TARGET_CPU_ZARCH" 4785 "!TARGET_ZARCH && TARGET_CPU_ZARCH"
4719 "#" 4786 "#"
4720 "&& reload_completed" 4787 "&& reload_completed"
4721 [(parallel 4788 [(parallel
4722 [(set (reg:CCL2 CC_REGNUM) 4789 [(set (reg:CCL2 CC_REGNUM)
4723 (compare:CCL2 (minus:SI (match_dup 7) (match_dup 8)) 4790 (compare:CCL2 (minus:SI (match_dup 7) (match_dup 8))
5177 5244
5178 (define_insn "*muldi3_sign" 5245 (define_insn "*muldi3_sign"
5179 [(set (match_operand:DI 0 "register_operand" "=d,d") 5246 [(set (match_operand:DI 0 "register_operand" "=d,d")
5180 (mult:DI (sign_extend:DI (match_operand:SI 2 "general_operand" "d,RT")) 5247 (mult:DI (sign_extend:DI (match_operand:SI 2 "general_operand" "d,RT"))
5181 (match_operand:DI 1 "register_operand" "0,0")))] 5248 (match_operand:DI 1 "register_operand" "0,0")))]
5182 "TARGET_64BIT" 5249 "TARGET_ZARCH"
5183 "@ 5250 "@
5184 msgfr\t%0,%2 5251 msgfr\t%0,%2
5185 msgf\t%0,%2" 5252 msgf\t%0,%2"
5186 [(set_attr "op_type" "RRE,RXY") 5253 [(set_attr "op_type" "RRE,RXY")
5187 (set_attr "type" "imuldi")]) 5254 (set_attr "type" "imuldi")])
5188 5255
5189 (define_insn "muldi3" 5256 (define_insn "muldi3"
5190 [(set (match_operand:DI 0 "register_operand" "=d,d,d,d") 5257 [(set (match_operand:DI 0 "register_operand" "=d,d,d,d")
5191 (mult:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0,0,0") 5258 (mult:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0,0,0")
5192 (match_operand:DI 2 "general_operand" "d,K,RT,Os")))] 5259 (match_operand:DI 2 "general_operand" "d,K,RT,Os")))]
5193 "TARGET_64BIT" 5260 "TARGET_ZARCH"
5194 "@ 5261 "@
5195 msgr\t%0,%2 5262 msgr\t%0,%2
5196 mghi\t%0,%h2 5263 mghi\t%0,%h2
5197 msg\t%0,%2 5264 msg\t%0,%2
5198 msgfi\t%0,%2" 5265 msgfi\t%0,%2"
5239 [(set (match_operand:DI 0 "register_operand" "=d,d,d") 5306 [(set (match_operand:DI 0 "register_operand" "=d,d,d")
5240 (mult:DI (sign_extend:DI 5307 (mult:DI (sign_extend:DI
5241 (match_operand:SI 1 "register_operand" "%0,0,0")) 5308 (match_operand:SI 1 "register_operand" "%0,0,0"))
5242 (sign_extend:DI 5309 (sign_extend:DI
5243 (match_operand:SI 2 "nonimmediate_operand" "d,R,T"))))] 5310 (match_operand:SI 2 "nonimmediate_operand" "d,R,T"))))]
5244 "!TARGET_64BIT" 5311 "!TARGET_ZARCH"
5245 "@ 5312 "@
5246 mr\t%0,%2 5313 mr\t%0,%2
5247 m\t%0,%2 5314 m\t%0,%2
5248 mfy\t%0,%2" 5315 mfy\t%0,%2"
5249 [(set_attr "op_type" "RR,RX,RXY") 5316 [(set_attr "op_type" "RR,RX,RXY")
5258 [(set (match_operand:DI 0 "register_operand" "=d,d") 5325 [(set (match_operand:DI 0 "register_operand" "=d,d")
5259 (mult:DI (zero_extend:DI 5326 (mult:DI (zero_extend:DI
5260 (match_operand:SI 1 "register_operand" "%0,0")) 5327 (match_operand:SI 1 "register_operand" "%0,0"))
5261 (zero_extend:DI 5328 (zero_extend:DI
5262 (match_operand:SI 2 "nonimmediate_operand" "d,RT"))))] 5329 (match_operand:SI 2 "nonimmediate_operand" "d,RT"))))]
5263 "!TARGET_64BIT && TARGET_CPU_ZARCH" 5330 "!TARGET_ZARCH && TARGET_CPU_ZARCH"
5264 "@ 5331 "@
5265 mlr\t%0,%2 5332 mlr\t%0,%2
5266 ml\t%0,%2" 5333 ml\t%0,%2"
5267 [(set_attr "op_type" "RRE,RXY") 5334 [(set_attr "op_type" "RRE,RXY")
5268 (set_attr "type" "imulsi")]) 5335 (set_attr "type" "imulsi")])
5322 (div:DI (match_operand:DI 1 "register_operand" "") 5389 (div:DI (match_operand:DI 1 "register_operand" "")
5323 (match_operand:DI 2 "general_operand" ""))) 5390 (match_operand:DI 2 "general_operand" "")))
5324 (set (match_operand:DI 3 "general_operand" "") 5391 (set (match_operand:DI 3 "general_operand" "")
5325 (mod:DI (match_dup 1) (match_dup 2)))]) 5392 (mod:DI (match_dup 1) (match_dup 2)))])
5326 (clobber (match_dup 4))] 5393 (clobber (match_dup 4))]
5327 "TARGET_64BIT" 5394 "TARGET_ZARCH"
5328 { 5395 {
5329 rtx insn, div_equal, mod_equal; 5396 rtx insn, div_equal, mod_equal;
5330 5397
5331 div_equal = gen_rtx_DIV (DImode, operands[1], operands[2]); 5398 div_equal = gen_rtx_DIV (DImode, operands[1], operands[2]);
5332 mod_equal = gen_rtx_MOD (DImode, operands[1], operands[2]); 5399 mod_equal = gen_rtx_MOD (DImode, operands[1], operands[2]);
5350 (zero_extend:TI 5417 (zero_extend:TI
5351 (mod:DI (match_operand:DI 1 "register_operand" "0,0") 5418 (mod:DI (match_operand:DI 1 "register_operand" "0,0")
5352 (match_operand:DI 2 "general_operand" "d,RT"))) 5419 (match_operand:DI 2 "general_operand" "d,RT")))
5353 (const_int 64)) 5420 (const_int 64))
5354 (zero_extend:TI (div:DI (match_dup 1) (match_dup 2)))))] 5421 (zero_extend:TI (div:DI (match_dup 1) (match_dup 2)))))]
5355 "TARGET_64BIT" 5422 "TARGET_ZARCH"
5356 "@ 5423 "@
5357 dsgr\t%0,%2 5424 dsgr\t%0,%2
5358 dsg\t%0,%2" 5425 dsg\t%0,%2"
5359 [(set_attr "op_type" "RRE,RXY") 5426 [(set_attr "op_type" "RRE,RXY")
5360 (set_attr "type" "idiv")]) 5427 (set_attr "type" "idiv")])
5368 (sign_extend:DI 5435 (sign_extend:DI
5369 (match_operand:SI 2 "nonimmediate_operand" "d,RT")))) 5436 (match_operand:SI 2 "nonimmediate_operand" "d,RT"))))
5370 (const_int 64)) 5437 (const_int 64))
5371 (zero_extend:TI 5438 (zero_extend:TI
5372 (div:DI (match_dup 1) (sign_extend:DI (match_dup 2))))))] 5439 (div:DI (match_dup 1) (sign_extend:DI (match_dup 2))))))]
5373 "TARGET_64BIT" 5440 "TARGET_ZARCH"
5374 "@ 5441 "@
5375 dsgfr\t%0,%2 5442 dsgfr\t%0,%2
5376 dsgf\t%0,%2" 5443 dsgf\t%0,%2"
5377 [(set_attr "op_type" "RRE,RXY") 5444 [(set_attr "op_type" "RRE,RXY")
5378 (set_attr "type" "idiv")]) 5445 (set_attr "type" "idiv")])
5386 (udiv:DI (match_operand:DI 1 "general_operand" "") 5453 (udiv:DI (match_operand:DI 1 "general_operand" "")
5387 (match_operand:DI 2 "nonimmediate_operand" ""))) 5454 (match_operand:DI 2 "nonimmediate_operand" "")))
5388 (set (match_operand:DI 3 "general_operand" "") 5455 (set (match_operand:DI 3 "general_operand" "")
5389 (umod:DI (match_dup 1) (match_dup 2)))]) 5456 (umod:DI (match_dup 1) (match_dup 2)))])
5390 (clobber (match_dup 4))] 5457 (clobber (match_dup 4))]
5391 "TARGET_64BIT" 5458 "TARGET_ZARCH"
5392 { 5459 {
5393 rtx insn, div_equal, mod_equal, equal; 5460 rtx insn, div_equal, mod_equal, equal;
5394 5461
5395 div_equal = gen_rtx_UDIV (DImode, operands[1], operands[2]); 5462 div_equal = gen_rtx_UDIV (DImode, operands[1], operands[2]);
5396 mod_equal = gen_rtx_UMOD (DImode, operands[1], operands[2]); 5463 mod_equal = gen_rtx_UMOD (DImode, operands[1], operands[2]);
5428 (match_operand:DI 2 "nonimmediate_operand" "d,RT"))))) 5495 (match_operand:DI 2 "nonimmediate_operand" "d,RT")))))
5429 (const_int 64)) 5496 (const_int 64))
5430 (zero_extend:TI 5497 (zero_extend:TI
5431 (truncate:DI 5498 (truncate:DI
5432 (udiv:TI (match_dup 1) (zero_extend:TI (match_dup 2)))))))] 5499 (udiv:TI (match_dup 1) (zero_extend:TI (match_dup 2)))))))]
5433 "TARGET_64BIT" 5500 "TARGET_ZARCH"
5434 "@ 5501 "@
5435 dlgr\t%0,%2 5502 dlgr\t%0,%2
5436 dlg\t%0,%2" 5503 dlg\t%0,%2"
5437 [(set_attr "op_type" "RRE,RXY") 5504 [(set_attr "op_type" "RRE,RXY")
5438 (set_attr "type" "idiv")]) 5505 (set_attr "type" "idiv")])
5446 (div:SI (match_operand:SI 1 "general_operand" "") 5513 (div:SI (match_operand:SI 1 "general_operand" "")
5447 (match_operand:SI 2 "nonimmediate_operand" ""))) 5514 (match_operand:SI 2 "nonimmediate_operand" "")))
5448 (set (match_operand:SI 3 "general_operand" "") 5515 (set (match_operand:SI 3 "general_operand" "")
5449 (mod:SI (match_dup 1) (match_dup 2)))]) 5516 (mod:SI (match_dup 1) (match_dup 2)))])
5450 (clobber (match_dup 4))] 5517 (clobber (match_dup 4))]
5451 "!TARGET_64BIT" 5518 "!TARGET_ZARCH"
5452 { 5519 {
5453 rtx insn, div_equal, mod_equal, equal; 5520 rtx insn, div_equal, mod_equal, equal;
5454 5521
5455 div_equal = gen_rtx_DIV (SImode, operands[1], operands[2]); 5522 div_equal = gen_rtx_DIV (SImode, operands[1], operands[2]);
5456 mod_equal = gen_rtx_MOD (SImode, operands[1], operands[2]); 5523 mod_equal = gen_rtx_MOD (SImode, operands[1], operands[2]);
5486 (match_operand:SI 2 "nonimmediate_operand" "d,R"))))) 5553 (match_operand:SI 2 "nonimmediate_operand" "d,R")))))
5487 (const_int 32)) 5554 (const_int 32))
5488 (zero_extend:DI 5555 (zero_extend:DI
5489 (truncate:SI 5556 (truncate:SI
5490 (div:DI (match_dup 1) (sign_extend:DI (match_dup 2)))))))] 5557 (div:DI (match_dup 1) (sign_extend:DI (match_dup 2)))))))]
5491 "!TARGET_64BIT" 5558 "!TARGET_ZARCH"
5492 "@ 5559 "@
5493 dr\t%0,%2 5560 dr\t%0,%2
5494 d\t%0,%2" 5561 d\t%0,%2"
5495 [(set_attr "op_type" "RR,RX") 5562 [(set_attr "op_type" "RR,RX")
5496 (set_attr "type" "idiv")]) 5563 (set_attr "type" "idiv")])
5504 (udiv:SI (match_operand:SI 1 "general_operand" "") 5571 (udiv:SI (match_operand:SI 1 "general_operand" "")
5505 (match_operand:SI 2 "nonimmediate_operand" ""))) 5572 (match_operand:SI 2 "nonimmediate_operand" "")))
5506 (set (match_operand:SI 3 "general_operand" "") 5573 (set (match_operand:SI 3 "general_operand" "")
5507 (umod:SI (match_dup 1) (match_dup 2)))]) 5574 (umod:SI (match_dup 1) (match_dup 2)))])
5508 (clobber (match_dup 4))] 5575 (clobber (match_dup 4))]
5509 "!TARGET_64BIT && TARGET_CPU_ZARCH" 5576 "!TARGET_ZARCH && TARGET_CPU_ZARCH"
5510 { 5577 {
5511 rtx insn, div_equal, mod_equal, equal; 5578 rtx insn, div_equal, mod_equal, equal;
5512 5579
5513 div_equal = gen_rtx_UDIV (SImode, operands[1], operands[2]); 5580 div_equal = gen_rtx_UDIV (SImode, operands[1], operands[2]);
5514 mod_equal = gen_rtx_UMOD (SImode, operands[1], operands[2]); 5581 mod_equal = gen_rtx_UMOD (SImode, operands[1], operands[2]);
5546 (match_operand:SI 2 "nonimmediate_operand" "d,RT"))))) 5613 (match_operand:SI 2 "nonimmediate_operand" "d,RT")))))
5547 (const_int 32)) 5614 (const_int 32))
5548 (zero_extend:DI 5615 (zero_extend:DI
5549 (truncate:SI 5616 (truncate:SI
5550 (udiv:DI (match_dup 1) (zero_extend:DI (match_dup 2)))))))] 5617 (udiv:DI (match_dup 1) (zero_extend:DI (match_dup 2)))))))]
5551 "!TARGET_64BIT && TARGET_CPU_ZARCH" 5618 "!TARGET_ZARCH && TARGET_CPU_ZARCH"
5552 "@ 5619 "@
5553 dlr\t%0,%2 5620 dlr\t%0,%2
5554 dl\t%0,%2" 5621 dl\t%0,%2"
5555 [(set_attr "op_type" "RRE,RXY") 5622 [(set_attr "op_type" "RRE,RXY")
5556 (set_attr "type" "idiv")]) 5623 (set_attr "type" "idiv")])
5558 (define_expand "udivsi3" 5625 (define_expand "udivsi3"
5559 [(set (match_operand:SI 0 "register_operand" "=d") 5626 [(set (match_operand:SI 0 "register_operand" "=d")
5560 (udiv:SI (match_operand:SI 1 "general_operand" "") 5627 (udiv:SI (match_operand:SI 1 "general_operand" "")
5561 (match_operand:SI 2 "general_operand" ""))) 5628 (match_operand:SI 2 "general_operand" "")))
5562 (clobber (match_dup 3))] 5629 (clobber (match_dup 3))]
5563 "!TARGET_64BIT && !TARGET_CPU_ZARCH" 5630 "!TARGET_ZARCH && !TARGET_CPU_ZARCH"
5564 { 5631 {
5565 rtx insn, udiv_equal, umod_equal, equal; 5632 rtx insn, udiv_equal, umod_equal, equal;
5566 5633
5567 udiv_equal = gen_rtx_UDIV (SImode, operands[1], operands[2]); 5634 udiv_equal = gen_rtx_UDIV (SImode, operands[1], operands[2]);
5568 umod_equal = gen_rtx_UMOD (SImode, operands[1], operands[2]); 5635 umod_equal = gen_rtx_UMOD (SImode, operands[1], operands[2]);
5644 (define_expand "umodsi3" 5711 (define_expand "umodsi3"
5645 [(set (match_operand:SI 0 "register_operand" "=d") 5712 [(set (match_operand:SI 0 "register_operand" "=d")
5646 (umod:SI (match_operand:SI 1 "nonimmediate_operand" "") 5713 (umod:SI (match_operand:SI 1 "nonimmediate_operand" "")
5647 (match_operand:SI 2 "nonimmediate_operand" ""))) 5714 (match_operand:SI 2 "nonimmediate_operand" "")))
5648 (clobber (match_dup 3))] 5715 (clobber (match_dup 3))]
5649 "!TARGET_64BIT && !TARGET_CPU_ZARCH" 5716 "!TARGET_ZARCH && !TARGET_CPU_ZARCH"
5650 { 5717 {
5651 rtx insn, udiv_equal, umod_equal, equal; 5718 rtx insn, udiv_equal, umod_equal, equal;
5652 5719
5653 udiv_equal = gen_rtx_UDIV (SImode, operands[1], operands[2]); 5720 udiv_equal = gen_rtx_UDIV (SImode, operands[1], operands[2]);
5654 umod_equal = gen_rtx_UMOD (SImode, operands[1], operands[2]); 5721 umod_equal = gen_rtx_UMOD (SImode, operands[1], operands[2]);
5765 (compare (and:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0") 5832 (compare (and:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
5766 (match_operand:DI 2 "general_operand" "d,RT")) 5833 (match_operand:DI 2 "general_operand" "d,RT"))
5767 (const_int 0))) 5834 (const_int 0)))
5768 (set (match_operand:DI 0 "register_operand" "=d,d") 5835 (set (match_operand:DI 0 "register_operand" "=d,d")
5769 (and:DI (match_dup 1) (match_dup 2)))] 5836 (and:DI (match_dup 1) (match_dup 2)))]
5770 "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT" 5837 "s390_match_ccmode(insn, CCTmode) && TARGET_ZARCH"
5771 "@ 5838 "@
5772 ngr\t%0,%2 5839 ngr\t%0,%2
5773 ng\t%0,%2" 5840 ng\t%0,%2"
5774 [(set_attr "op_type" "RRE,RXY") 5841 [(set_attr "op_type" "RRE,RXY")
5775 (set_attr "z10prop" "z10_super_E1,z10_super_E1")]) 5842 (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
5778 [(set (reg CC_REGNUM) 5845 [(set (reg CC_REGNUM)
5779 (compare (and:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0") 5846 (compare (and:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
5780 (match_operand:DI 2 "general_operand" "d,RT")) 5847 (match_operand:DI 2 "general_operand" "d,RT"))
5781 (const_int 0))) 5848 (const_int 0)))
5782 (clobber (match_scratch:DI 0 "=d,d"))] 5849 (clobber (match_scratch:DI 0 "=d,d"))]
5783 "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT 5850 "s390_match_ccmode(insn, CCTmode) && TARGET_ZARCH
5784 /* Do not steal TM patterns. */ 5851 /* Do not steal TM patterns. */
5785 && s390_single_part (operands[2], DImode, HImode, 0) < 0" 5852 && s390_single_part (operands[2], DImode, HImode, 0) < 0"
5786 "@ 5853 "@
5787 ngr\t%0,%2 5854 ngr\t%0,%2
5788 ng\t%0,%2" 5855 ng\t%0,%2"
5794 (and:DI (match_operand:DI 1 "nonimmediate_operand" 5861 (and:DI (match_operand:DI 1 "nonimmediate_operand"
5795 "%d,o,0,0,0,0,0,0,0,0,0,0") 5862 "%d,o,0,0,0,0,0,0,0,0,0,0")
5796 (match_operand:DI 2 "general_operand" 5863 (match_operand:DI 2 "general_operand"
5797 "M,M,N0HDF,N1HDF,N2HDF,N3HDF,N0SDF,N1SDF,d,RT,NxQDF,Q"))) 5864 "M,M,N0HDF,N1HDF,N2HDF,N3HDF,N0SDF,N1SDF,d,RT,NxQDF,Q")))
5798 (clobber (reg:CC CC_REGNUM))] 5865 (clobber (reg:CC CC_REGNUM))]
5799 "TARGET_64BIT && s390_logical_operator_ok_p (operands)" 5866 "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
5800 "@ 5867 "@
5801 # 5868 #
5802 # 5869 #
5803 nihh\t%0,%j2 5870 nihh\t%0,%j2
5804 nihl\t%0,%j2 5871 nihl\t%0,%j2
6084 (compare (ior:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0") 6151 (compare (ior:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
6085 (match_operand:DI 2 "general_operand" "d,RT")) 6152 (match_operand:DI 2 "general_operand" "d,RT"))
6086 (const_int 0))) 6153 (const_int 0)))
6087 (set (match_operand:DI 0 "register_operand" "=d,d") 6154 (set (match_operand:DI 0 "register_operand" "=d,d")
6088 (ior:DI (match_dup 1) (match_dup 2)))] 6155 (ior:DI (match_dup 1) (match_dup 2)))]
6089 "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT" 6156 "s390_match_ccmode(insn, CCTmode) && TARGET_ZARCH"
6090 "@ 6157 "@
6091 ogr\t%0,%2 6158 ogr\t%0,%2
6092 og\t%0,%2" 6159 og\t%0,%2"
6093 [(set_attr "op_type" "RRE,RXY") 6160 [(set_attr "op_type" "RRE,RXY")
6094 (set_attr "z10prop" "z10_super_E1,z10_super_E1")]) 6161 (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
6097 [(set (reg CC_REGNUM) 6164 [(set (reg CC_REGNUM)
6098 (compare (ior:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0") 6165 (compare (ior:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
6099 (match_operand:DI 2 "general_operand" "d,RT")) 6166 (match_operand:DI 2 "general_operand" "d,RT"))
6100 (const_int 0))) 6167 (const_int 0)))
6101 (clobber (match_scratch:DI 0 "=d,d"))] 6168 (clobber (match_scratch:DI 0 "=d,d"))]
6102 "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT" 6169 "s390_match_ccmode(insn, CCTmode) && TARGET_ZARCH"
6103 "@ 6170 "@
6104 ogr\t%0,%2 6171 ogr\t%0,%2
6105 og\t%0,%2" 6172 og\t%0,%2"
6106 [(set_attr "op_type" "RRE,RXY") 6173 [(set_attr "op_type" "RRE,RXY")
6107 (set_attr "z10prop" "z10_super_E1,z10_super_E1")]) 6174 (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
6110 [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,d,d,d,d,d,d,AQ,Q") 6177 [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,d,d,d,d,d,d,AQ,Q")
6111 (ior:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0,0,0,0,0,0,0,0,0") 6178 (ior:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0,0,0,0,0,0,0,0,0")
6112 (match_operand:DI 2 "general_operand" 6179 (match_operand:DI 2 "general_operand"
6113 "N0HD0,N1HD0,N2HD0,N3HD0,N0SD0,N1SD0,d,RT,NxQD0,Q"))) 6180 "N0HD0,N1HD0,N2HD0,N3HD0,N0SD0,N1SD0,d,RT,NxQD0,Q")))
6114 (clobber (reg:CC CC_REGNUM))] 6181 (clobber (reg:CC CC_REGNUM))]
6115 "TARGET_64BIT && s390_logical_operator_ok_p (operands)" 6182 "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
6116 "@ 6183 "@
6117 oihh\t%0,%i2 6184 oihh\t%0,%i2
6118 oihl\t%0,%i2 6185 oihl\t%0,%i2
6119 oilh\t%0,%i2 6186 oilh\t%0,%i2
6120 oill\t%0,%i2 6187 oill\t%0,%i2
6384 (compare (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0") 6451 (compare (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
6385 (match_operand:DI 2 "general_operand" "d,RT")) 6452 (match_operand:DI 2 "general_operand" "d,RT"))
6386 (const_int 0))) 6453 (const_int 0)))
6387 (set (match_operand:DI 0 "register_operand" "=d,d") 6454 (set (match_operand:DI 0 "register_operand" "=d,d")
6388 (xor:DI (match_dup 1) (match_dup 2)))] 6455 (xor:DI (match_dup 1) (match_dup 2)))]
6389 "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT" 6456 "s390_match_ccmode(insn, CCTmode) && TARGET_ZARCH"
6390 "@ 6457 "@
6391 xgr\t%0,%2 6458 xgr\t%0,%2
6392 xg\t%0,%2" 6459 xg\t%0,%2"
6393 [(set_attr "op_type" "RRE,RXY") 6460 [(set_attr "op_type" "RRE,RXY")
6394 (set_attr "z10prop" "z10_super_E1,z10_super_E1")]) 6461 (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
6397 [(set (reg CC_REGNUM) 6464 [(set (reg CC_REGNUM)
6398 (compare (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0") 6465 (compare (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
6399 (match_operand:DI 2 "general_operand" "d,RT")) 6466 (match_operand:DI 2 "general_operand" "d,RT"))
6400 (const_int 0))) 6467 (const_int 0)))
6401 (clobber (match_scratch:DI 0 "=d,d"))] 6468 (clobber (match_scratch:DI 0 "=d,d"))]
6402 "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT" 6469 "s390_match_ccmode(insn, CCTmode) && TARGET_ZARCH"
6403 "@ 6470 "@
6404 xgr\t%0,%2 6471 xgr\t%0,%2
6405 xg\t%0,%2" 6472 xg\t%0,%2"
6406 [(set_attr "op_type" "RRE,RXY") 6473 [(set_attr "op_type" "RRE,RXY")
6407 (set_attr "z10prop" "z10_super_E1,z10_super_E1")]) 6474 (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
6409 (define_insn "*xordi3" 6476 (define_insn "*xordi3"
6410 [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,d,d,AQ,Q") 6477 [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,d,d,AQ,Q")
6411 (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0,0,0,0,0") 6478 (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0,0,0,0,0")
6412 (match_operand:DI 2 "general_operand" "N0SD0,N1SD0,d,RT,NxQD0,Q"))) 6479 (match_operand:DI 2 "general_operand" "N0SD0,N1SD0,d,RT,NxQD0,Q")))
6413 (clobber (reg:CC CC_REGNUM))] 6480 (clobber (reg:CC CC_REGNUM))]
6414 "TARGET_64BIT && s390_logical_operator_ok_p (operands)" 6481 "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
6415 "@ 6482 "@
6416 xihf\t%0,%k2 6483 xihf\t%0,%k2
6417 xilf\t%0,%k2 6484 xilf\t%0,%k2
6418 xgr\t%0,%2 6485 xgr\t%0,%2
6419 xg\t%0,%2 6486 xg\t%0,%2
6656 (match_operand:SI 1 "register_operand" "d") 0) 6723 (match_operand:SI 1 "register_operand" "d") 0)
6657 (const_int 32)) (const_int 32))) 6724 (const_int 32)) (const_int 32)))
6658 (const_int 0))) 6725 (const_int 0)))
6659 (set (match_operand:DI 0 "register_operand" "=d") 6726 (set (match_operand:DI 0 "register_operand" "=d")
6660 (neg:DI (sign_extend:DI (match_dup 1))))] 6727 (neg:DI (sign_extend:DI (match_dup 1))))]
6661 "TARGET_64BIT && s390_match_ccmode (insn, CCAmode)" 6728 "TARGET_ZARCH && s390_match_ccmode (insn, CCAmode)"
6662 "lcgfr\t%0,%1" 6729 "lcgfr\t%0,%1"
6663 [(set_attr "op_type" "RRE") 6730 [(set_attr "op_type" "RRE")
6664 (set_attr "z10prop" "z10_c")]) 6731 (set_attr "z10prop" "z10_c")])
6665 6732
6666 (define_insn "*negdi2_sign" 6733 (define_insn "*negdi2_sign"
6667 [(set (match_operand:DI 0 "register_operand" "=d") 6734 [(set (match_operand:DI 0 "register_operand" "=d")
6668 (neg:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "d")))) 6735 (neg:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "d"))))
6669 (clobber (reg:CC CC_REGNUM))] 6736 (clobber (reg:CC CC_REGNUM))]
6670 "TARGET_64BIT" 6737 "TARGET_ZARCH"
6671 "lcgfr\t%0,%1" 6738 "lcgfr\t%0,%1"
6672 [(set_attr "op_type" "RRE") 6739 [(set_attr "op_type" "RRE")
6673 (set_attr "z10prop" "z10_c")]) 6740 (set_attr "z10prop" "z10_c")])
6674 6741
6675 ; lcr, lcgr 6742 ; lcr, lcgr
6707 6774
6708 (define_insn_and_split "*negdi2_31" 6775 (define_insn_and_split "*negdi2_31"
6709 [(set (match_operand:DI 0 "register_operand" "=d") 6776 [(set (match_operand:DI 0 "register_operand" "=d")
6710 (neg:DI (match_operand:DI 1 "register_operand" "d"))) 6777 (neg:DI (match_operand:DI 1 "register_operand" "d")))
6711 (clobber (reg:CC CC_REGNUM))] 6778 (clobber (reg:CC CC_REGNUM))]
6712 "!TARGET_64BIT" 6779 "!TARGET_ZARCH"
6713 "#" 6780 "#"
6714 "&& reload_completed" 6781 "&& reload_completed"
6715 [(parallel 6782 [(parallel
6716 [(set (match_dup 2) (neg:SI (match_dup 3))) 6783 [(set (match_dup 2) (neg:SI (match_dup 3)))
6717 (clobber (reg:CC CC_REGNUM))]) 6784 (clobber (reg:CC CC_REGNUM))])
6802 (match_operand:SI 1 "register_operand" "d") 0) 6869 (match_operand:SI 1 "register_operand" "d") 0)
6803 (const_int 32)) (const_int 32))) 6870 (const_int 32)) (const_int 32)))
6804 (const_int 0))) 6871 (const_int 0)))
6805 (set (match_operand:DI 0 "register_operand" "=d") 6872 (set (match_operand:DI 0 "register_operand" "=d")
6806 (abs:DI (sign_extend:DI (match_dup 1))))] 6873 (abs:DI (sign_extend:DI (match_dup 1))))]
6807 "TARGET_64BIT && s390_match_ccmode (insn, CCAmode)" 6874 "TARGET_ZARCH && s390_match_ccmode (insn, CCAmode)"
6808 "lpgfr\t%0,%1" 6875 "lpgfr\t%0,%1"
6809 [(set_attr "op_type" "RRE") 6876 [(set_attr "op_type" "RRE")
6810 (set_attr "z10prop" "z10_c")]) 6877 (set_attr "z10prop" "z10_c")])
6811 6878
6812 (define_insn "*absdi2_sign" 6879 (define_insn "*absdi2_sign"
6813 [(set (match_operand:DI 0 "register_operand" "=d") 6880 [(set (match_operand:DI 0 "register_operand" "=d")
6814 (abs:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "d")))) 6881 (abs:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "d"))))
6815 (clobber (reg:CC CC_REGNUM))] 6882 (clobber (reg:CC CC_REGNUM))]
6816 "TARGET_64BIT" 6883 "TARGET_ZARCH"
6817 "lpgfr\t%0,%1" 6884 "lpgfr\t%0,%1"
6818 [(set_attr "op_type" "RRE") 6885 [(set_attr "op_type" "RRE")
6819 (set_attr "z10prop" "z10_c")]) 6886 (set_attr "z10prop" "z10_c")])
6820 6887
6821 ; lpr, lpgr 6888 ; lpr, lpgr
6920 (match_operand:SI 1 "register_operand" "d") 0) 6987 (match_operand:SI 1 "register_operand" "d") 0)
6921 (const_int 32)) (const_int 32)))) 6988 (const_int 32)) (const_int 32))))
6922 (const_int 0))) 6989 (const_int 0)))
6923 (set (match_operand:DI 0 "register_operand" "=d") 6990 (set (match_operand:DI 0 "register_operand" "=d")
6924 (neg:DI (abs:DI (sign_extend:DI (match_dup 1)))))] 6991 (neg:DI (abs:DI (sign_extend:DI (match_dup 1)))))]
6925 "TARGET_64BIT && s390_match_ccmode (insn, CCAmode)" 6992 "TARGET_ZARCH && s390_match_ccmode (insn, CCAmode)"
6926 "lngfr\t%0,%1" 6993 "lngfr\t%0,%1"
6927 [(set_attr "op_type" "RRE") 6994 [(set_attr "op_type" "RRE")
6928 (set_attr "z10prop" "z10_c")]) 6995 (set_attr "z10prop" "z10_c")])
6929 6996
6930 (define_insn "*negabsdi2_sign" 6997 (define_insn "*negabsdi2_sign"
6931 [(set (match_operand:DI 0 "register_operand" "=d") 6998 [(set (match_operand:DI 0 "register_operand" "=d")
6932 (neg:DI (abs:DI (sign_extend:DI 6999 (neg:DI (abs:DI (sign_extend:DI
6933 (match_operand:SI 1 "register_operand" "d"))))) 7000 (match_operand:SI 1 "register_operand" "d")))))
6934 (clobber (reg:CC CC_REGNUM))] 7001 (clobber (reg:CC CC_REGNUM))]
6935 "TARGET_64BIT" 7002 "TARGET_ZARCH"
6936 "lngfr\t%0,%1" 7003 "lngfr\t%0,%1"
6937 [(set_attr "op_type" "RRE") 7004 [(set_attr "op_type" "RRE")
6938 (set_attr "z10prop" "z10_c")]) 7005 (set_attr "z10prop" "z10_c")])
6939 7006
6940 ; lnr, lngr 7007 ; lnr, lngr
7059 ;; 7126 ;;
7060 7127
7061 (define_expand "clzdi2" 7128 (define_expand "clzdi2"
7062 [(set (match_operand:DI 0 "register_operand" "=d") 7129 [(set (match_operand:DI 0 "register_operand" "=d")
7063 (clz:DI (match_operand:DI 1 "register_operand" "d")))] 7130 (clz:DI (match_operand:DI 1 "register_operand" "d")))]
7064 "TARGET_EXTIMM && TARGET_64BIT" 7131 "TARGET_EXTIMM && TARGET_ZARCH"
7065 { 7132 {
7066 rtx insn, clz_equal; 7133 rtx insn, clz_equal;
7067 rtx wide_reg = gen_reg_rtx (TImode); 7134 rtx wide_reg = gen_reg_rtx (TImode);
7068 rtx msb = gen_rtx_CONST_INT (DImode, (unsigned HOST_WIDE_INT) 1 << 63); 7135 rtx msb = gen_rtx_CONST_INT (DImode, (unsigned HOST_WIDE_INT) 1 << 63);
7069 7136
7089 (const_int 64)) 7156 (const_int 64))
7090 (zero_extend:TI (clz:DI (match_dup 1))))) 7157 (zero_extend:TI (clz:DI (match_dup 1)))))
7091 (clobber (reg:CC CC_REGNUM))] 7158 (clobber (reg:CC CC_REGNUM))]
7092 "(unsigned HOST_WIDE_INT) INTVAL (operands[2]) 7159 "(unsigned HOST_WIDE_INT) INTVAL (operands[2])
7093 == (unsigned HOST_WIDE_INT) 1 << 63 7160 == (unsigned HOST_WIDE_INT) 1 << 63
7094 && TARGET_EXTIMM && TARGET_64BIT" 7161 && TARGET_EXTIMM && TARGET_ZARCH"
7095 "flogr\t%0,%1" 7162 "flogr\t%0,%1"
7096 [(set_attr "op_type" "RRE")]) 7163 [(set_attr "op_type" "RRE")])
7097 7164
7098 7165
7099 ;; 7166 ;;
7146 ; sldl, srdl 7213 ; sldl, srdl
7147 (define_insn "*<shift>di3_31" 7214 (define_insn "*<shift>di3_31"
7148 [(set (match_operand:DI 0 "register_operand" "=d") 7215 [(set (match_operand:DI 0 "register_operand" "=d")
7149 (SHIFT:DI (match_operand:DI 1 "register_operand" "0") 7216 (SHIFT:DI (match_operand:DI 1 "register_operand" "0")
7150 (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")))] 7217 (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")))]
7151 "!TARGET_64BIT" 7218 "!TARGET_ZARCH"
7152 "s<lr>dl\t%0,%Y2" 7219 "s<lr>dl\t%0,%Y2"
7153 [(set_attr "op_type" "RS") 7220 [(set_attr "op_type" "RS")
7154 (set_attr "atype" "reg")]) 7221 (set_attr "atype" "reg")])
7155 7222
7156 ; sll, srl, sllg, srlg 7223 ; sll, srl, sllg, srlg
7168 (define_insn "*<shift>di3_31_and" 7235 (define_insn "*<shift>di3_31_and"
7169 [(set (match_operand:DI 0 "register_operand" "=d") 7236 [(set (match_operand:DI 0 "register_operand" "=d")
7170 (SHIFT:DI (match_operand:DI 1 "register_operand" "0") 7237 (SHIFT:DI (match_operand:DI 1 "register_operand" "0")
7171 (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y") 7238 (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")
7172 (match_operand:SI 3 "const_int_operand" "n"))))] 7239 (match_operand:SI 3 "const_int_operand" "n"))))]
7173 "!TARGET_64BIT && (INTVAL (operands[3]) & 63) == 63" 7240 "!TARGET_ZARCH && (INTVAL (operands[3]) & 63) == 63"
7174 "s<lr>dl\t%0,%Y2" 7241 "s<lr>dl\t%0,%Y2"
7175 [(set_attr "op_type" "RS") 7242 [(set_attr "op_type" "RS")
7176 (set_attr "atype" "reg")]) 7243 (set_attr "atype" "reg")])
7177 7244
7178 ; sll, srl, sllg, srlg 7245 ; sll, srl, sllg, srlg
7205 (compare (ashiftrt:DI (match_operand:DI 1 "register_operand" "0") 7272 (compare (ashiftrt:DI (match_operand:DI 1 "register_operand" "0")
7206 (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")) 7273 (match_operand:SI 2 "shift_count_or_setmem_operand" "Y"))
7207 (const_int 0))) 7274 (const_int 0)))
7208 (set (match_operand:DI 0 "register_operand" "=d") 7275 (set (match_operand:DI 0 "register_operand" "=d")
7209 (ashiftrt:DI (match_dup 1) (match_dup 2)))] 7276 (ashiftrt:DI (match_dup 1) (match_dup 2)))]
7210 "!TARGET_64BIT && s390_match_ccmode(insn, CCSmode)" 7277 "!TARGET_ZARCH && s390_match_ccmode(insn, CCSmode)"
7211 "srda\t%0,%Y2" 7278 "srda\t%0,%Y2"
7212 [(set_attr "op_type" "RS") 7279 [(set_attr "op_type" "RS")
7213 (set_attr "atype" "reg")]) 7280 (set_attr "atype" "reg")])
7214 7281
7215 (define_insn "*ashrdi3_cconly_31" 7282 (define_insn "*ashrdi3_cconly_31"
7216 [(set (reg CC_REGNUM) 7283 [(set (reg CC_REGNUM)
7217 (compare (ashiftrt:DI (match_operand:DI 1 "register_operand" "0") 7284 (compare (ashiftrt:DI (match_operand:DI 1 "register_operand" "0")
7218 (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")) 7285 (match_operand:SI 2 "shift_count_or_setmem_operand" "Y"))
7219 (const_int 0))) 7286 (const_int 0)))
7220 (clobber (match_scratch:DI 0 "=d"))] 7287 (clobber (match_scratch:DI 0 "=d"))]
7221 "!TARGET_64BIT && s390_match_ccmode(insn, CCSmode)" 7288 "!TARGET_ZARCH && s390_match_ccmode(insn, CCSmode)"
7222 "srda\t%0,%Y2" 7289 "srda\t%0,%Y2"
7223 [(set_attr "op_type" "RS") 7290 [(set_attr "op_type" "RS")
7224 (set_attr "atype" "reg")]) 7291 (set_attr "atype" "reg")])
7225 7292
7226 (define_insn "*ashrdi3_31" 7293 (define_insn "*ashrdi3_31"
7227 [(set (match_operand:DI 0 "register_operand" "=d") 7294 [(set (match_operand:DI 0 "register_operand" "=d")
7228 (ashiftrt:DI (match_operand:DI 1 "register_operand" "0") 7295 (ashiftrt:DI (match_operand:DI 1 "register_operand" "0")
7229 (match_operand:SI 2 "shift_count_or_setmem_operand" "Y"))) 7296 (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")))
7230 (clobber (reg:CC CC_REGNUM))] 7297 (clobber (reg:CC CC_REGNUM))]
7231 "!TARGET_64BIT" 7298 "!TARGET_ZARCH"
7232 "srda\t%0,%Y2" 7299 "srda\t%0,%Y2"
7233 [(set_attr "op_type" "RS") 7300 [(set_attr "op_type" "RS")
7234 (set_attr "atype" "reg")]) 7301 (set_attr "atype" "reg")])
7235 7302
7236 ; sra, srag 7303 ; sra, srag
7281 (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y") 7348 (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")
7282 (match_operand:SI 3 "const_int_operand" "n"))) 7349 (match_operand:SI 3 "const_int_operand" "n")))
7283 (const_int 0))) 7350 (const_int 0)))
7284 (set (match_operand:DI 0 "register_operand" "=d") 7351 (set (match_operand:DI 0 "register_operand" "=d")
7285 (ashiftrt:DI (match_dup 1) (and:SI (match_dup 2) (match_dup 3))))] 7352 (ashiftrt:DI (match_dup 1) (and:SI (match_dup 2) (match_dup 3))))]
7286 "!TARGET_64BIT && s390_match_ccmode(insn, CCSmode) 7353 "!TARGET_ZARCH && s390_match_ccmode(insn, CCSmode)
7287 && (INTVAL (operands[3]) & 63) == 63" 7354 && (INTVAL (operands[3]) & 63) == 63"
7288 "srda\t%0,%Y2" 7355 "srda\t%0,%Y2"
7289 [(set_attr "op_type" "RS") 7356 [(set_attr "op_type" "RS")
7290 (set_attr "atype" "reg")]) 7357 (set_attr "atype" "reg")])
7291 7358
7294 (compare (ashiftrt:DI (match_operand:DI 1 "register_operand" "0") 7361 (compare (ashiftrt:DI (match_operand:DI 1 "register_operand" "0")
7295 (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y") 7362 (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")
7296 (match_operand:SI 3 "const_int_operand" "n"))) 7363 (match_operand:SI 3 "const_int_operand" "n")))
7297 (const_int 0))) 7364 (const_int 0)))
7298 (clobber (match_scratch:DI 0 "=d"))] 7365 (clobber (match_scratch:DI 0 "=d"))]
7299 "!TARGET_64BIT && s390_match_ccmode(insn, CCSmode) 7366 "!TARGET_ZARCH && s390_match_ccmode(insn, CCSmode)
7300 && (INTVAL (operands[3]) & 63) == 63" 7367 && (INTVAL (operands[3]) & 63) == 63"
7301 "srda\t%0,%Y2" 7368 "srda\t%0,%Y2"
7302 [(set_attr "op_type" "RS") 7369 [(set_attr "op_type" "RS")
7303 (set_attr "atype" "reg")]) 7370 (set_attr "atype" "reg")])
7304 7371
7306 [(set (match_operand:DI 0 "register_operand" "=d") 7373 [(set (match_operand:DI 0 "register_operand" "=d")
7307 (ashiftrt:DI (match_operand:DI 1 "register_operand" "0") 7374 (ashiftrt:DI (match_operand:DI 1 "register_operand" "0")
7308 (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y") 7375 (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")
7309 (match_operand:SI 3 "const_int_operand" "n")))) 7376 (match_operand:SI 3 "const_int_operand" "n"))))
7310 (clobber (reg:CC CC_REGNUM))] 7377 (clobber (reg:CC CC_REGNUM))]
7311 "!TARGET_64BIT && (INTVAL (operands[3]) & 63) == 63" 7378 "!TARGET_ZARCH && (INTVAL (operands[3]) & 63) == 63"
7312 "srda\t%0,%Y2" 7379 "srda\t%0,%Y2"
7313 [(set_attr "op_type" "RS") 7380 [(set_attr "op_type" "RS")
7314 (set_attr "atype" "reg")]) 7381 (set_attr "atype" "reg")])
7315 7382
7316 ; sra, srag 7383 ; sra, srag
7660 (set (match_operand:DI 3 "nonimmediate_operand" "=1,?X,?X") 7727 (set (match_operand:DI 3 "nonimmediate_operand" "=1,?X,?X")
7661 (plus:DI (match_dup 1) 7728 (plus:DI (match_dup 1)
7662 (subreg:DI (match_dup 2) 0))) 7729 (subreg:DI (match_dup 2) 0)))
7663 (clobber (match_scratch:DI 4 "=X,&1,&?d")) 7730 (clobber (match_scratch:DI 4 "=X,&1,&?d"))
7664 (clobber (reg:CC CC_REGNUM))] 7731 (clobber (reg:CC CC_REGNUM))]
7665 "TARGET_64BIT" 7732 "TARGET_ZARCH"
7666 { 7733 {
7667 if (which_alternative != 0) 7734 if (which_alternative != 0)
7668 return "#"; 7735 return "#";
7669 else if (get_attr_length (insn) == 6) 7736 else if (get_attr_length (insn) == 6)
7670 return "brx%E5g\t%1,%2,%l0"; 7737 return "brx%E5g\t%1,%2,%l0";
7703 (set (match_operand:SI 3 "nonimmediate_operand" "=1,?X,?X") 7770 (set (match_operand:SI 3 "nonimmediate_operand" "=1,?X,?X")
7704 (plus:SI (match_dup 1) 7771 (plus:SI (match_dup 1)
7705 (subreg:SI (match_dup 2) 4))) 7772 (subreg:SI (match_dup 2) 4)))
7706 (clobber (match_scratch:SI 4 "=X,&1,&?d")) 7773 (clobber (match_scratch:SI 4 "=X,&1,&?d"))
7707 (clobber (reg:CC CC_REGNUM))] 7774 (clobber (reg:CC CC_REGNUM))]
7708 "TARGET_64BIT" 7775 "TARGET_ZARCH"
7709 { 7776 {
7710 if (which_alternative != 0) 7777 if (which_alternative != 0)
7711 return "#"; 7778 return "#";
7712 else if (get_attr_length (insn) == 6) 7779 else if (get_attr_length (insn) == 6)
7713 return "brx%C5\t%1,%2,%l0"; 7780 return "brx%C5\t%1,%2,%l0";
7746 (set (match_operand:SI 3 "nonimmediate_operand" "=1,?X,?X") 7813 (set (match_operand:SI 3 "nonimmediate_operand" "=1,?X,?X")
7747 (plus:SI (match_dup 1) 7814 (plus:SI (match_dup 1)
7748 (subreg:SI (match_dup 2) 0))) 7815 (subreg:SI (match_dup 2) 0)))
7749 (clobber (match_scratch:SI 4 "=X,&1,&?d")) 7816 (clobber (match_scratch:SI 4 "=X,&1,&?d"))
7750 (clobber (reg:CC CC_REGNUM))] 7817 (clobber (reg:CC CC_REGNUM))]
7751 "!TARGET_64BIT && TARGET_CPU_ZARCH" 7818 "!TARGET_ZARCH && TARGET_CPU_ZARCH"
7752 { 7819 {
7753 if (which_alternative != 0) 7820 if (which_alternative != 0)
7754 return "#"; 7821 return "#";
7755 else if (get_attr_length (insn) == 6) 7822 else if (get_attr_length (insn) == 6)
7756 return "brx%C5\t%1,%2,%l0"; 7823 return "brx%C5\t%1,%2,%l0";
7788 { 7855 {
7789 if (GET_MODE (operands[0]) == SImode && !TARGET_CPU_ZARCH) 7856 if (GET_MODE (operands[0]) == SImode && !TARGET_CPU_ZARCH)
7790 emit_jump_insn (gen_doloop_si31 (operands[4], operands[0], operands[0])); 7857 emit_jump_insn (gen_doloop_si31 (operands[4], operands[0], operands[0]));
7791 else if (GET_MODE (operands[0]) == SImode && TARGET_CPU_ZARCH) 7858 else if (GET_MODE (operands[0]) == SImode && TARGET_CPU_ZARCH)
7792 emit_jump_insn (gen_doloop_si64 (operands[4], operands[0], operands[0])); 7859 emit_jump_insn (gen_doloop_si64 (operands[4], operands[0], operands[0]));
7793 else if (GET_MODE (operands[0]) == DImode && TARGET_64BIT) 7860 else if (GET_MODE (operands[0]) == DImode && TARGET_ZARCH)
7794 emit_jump_insn (gen_doloop_di (operands[4], operands[0], operands[0])); 7861 emit_jump_insn (gen_doloop_di (operands[4], operands[0], operands[0]));
7795 else 7862 else
7796 FAIL; 7863 FAIL;
7797 7864
7798 DONE; 7865 DONE;
7919 (pc))) 7986 (pc)))
7920 (set (match_operand:DI 2 "nonimmediate_operand" "=1,?X,?X") 7987 (set (match_operand:DI 2 "nonimmediate_operand" "=1,?X,?X")
7921 (plus:DI (match_dup 1) (const_int -1))) 7988 (plus:DI (match_dup 1) (const_int -1)))
7922 (clobber (match_scratch:DI 3 "=X,&1,&?d")) 7989 (clobber (match_scratch:DI 3 "=X,&1,&?d"))
7923 (clobber (reg:CC CC_REGNUM))] 7990 (clobber (reg:CC CC_REGNUM))]
7924 "TARGET_64BIT" 7991 "TARGET_ZARCH"
7925 { 7992 {
7926 if (which_alternative != 0) 7993 if (which_alternative != 0)
7927 return "#"; 7994 return "#";
7928 else if (get_attr_length (insn) == 4) 7995 else if (get_attr_length (insn) == 4)
7929 return "brctg\t%1,%l0"; 7996 return "brctg\t%1,%l0";
8477 "s390_expand_cs_hqi (<MODE>mode, operands[0], operands[1], 8544 "s390_expand_cs_hqi (<MODE>mode, operands[0], operands[1],
8478 operands[2], operands[3]); DONE;") 8545 operands[2], operands[3]); DONE;")
8479 8546
8480 ; cds, cdsg 8547 ; cds, cdsg
8481 (define_insn "*sync_compare_and_swap<mode>" 8548 (define_insn "*sync_compare_and_swap<mode>"
8482 [(set (match_operand:DP 0 "register_operand" "=r") 8549 [(set (match_operand:DW 0 "register_operand" "=r")
8483 (match_operand:DP 1 "memory_operand" "+Q")) 8550 (match_operand:DW 1 "memory_operand" "+Q"))
8484 (set (match_dup 1) 8551 (set (match_dup 1)
8485 (unspec_volatile:DP 8552 (unspec_volatile:DW
8486 [(match_dup 1) 8553 [(match_dup 1)
8487 (match_operand:DP 2 "register_operand" "0") 8554 (match_operand:DW 2 "register_operand" "0")
8488 (match_operand:DP 3 "register_operand" "r")] 8555 (match_operand:DW 3 "register_operand" "r")]
8489 UNSPECV_CAS)) 8556 UNSPECV_CAS))
8490 (set (reg:CCZ1 CC_REGNUM) 8557 (set (reg:CCZ1 CC_REGNUM)
8491 (compare:CCZ1 (match_dup 1) (match_dup 2)))] 8558 (compare:CCZ1 (match_dup 1) (match_dup 2)))]
8492 "" 8559 ""
8493 "cds<tg>\t%0,%3,%S1" 8560 "cds<tg>\t%0,%3,%S1"
8626 (define_expand "save_stack_nonlocal" 8693 (define_expand "save_stack_nonlocal"
8627 [(match_operand 0 "memory_operand" "") 8694 [(match_operand 0 "memory_operand" "")
8628 (match_operand 1 "register_operand" "")] 8695 (match_operand 1 "register_operand" "")]
8629 "" 8696 ""
8630 { 8697 {
8631 enum machine_mode mode = TARGET_64BIT ? OImode : TImode;
8632 rtx base = gen_rtx_REG (Pmode, BASE_REGNUM); 8698 rtx base = gen_rtx_REG (Pmode, BASE_REGNUM);
8633 8699
8634 /* Copy the backchain to the first word, sp to the second and the 8700 /* Copy the backchain to the first word, sp to the second and the
8635 literal pool base to the third. */ 8701 literal pool base to the third. */
8636 8702
8703 rtx save_bc = adjust_address (operands[0], Pmode, 0);
8704 rtx save_sp = adjust_address (operands[0], Pmode, GET_MODE_SIZE (Pmode));
8705 rtx save_bp = adjust_address (operands[0], Pmode, 2 * GET_MODE_SIZE (Pmode));
8706
8637 if (TARGET_BACKCHAIN) 8707 if (TARGET_BACKCHAIN)
8638 { 8708 emit_move_insn (save_bc, force_reg (Pmode, s390_back_chain_rtx ()));
8639 rtx temp = force_reg (Pmode, s390_back_chain_rtx ()); 8709
8640 emit_move_insn (operand_subword (operands[0], 0, 0, mode), temp); 8710 emit_move_insn (save_sp, operands[1]);
8641 } 8711 emit_move_insn (save_bp, base);
8642
8643 emit_move_insn (operand_subword (operands[0], 1, 0, mode), operands[1]);
8644 emit_move_insn (operand_subword (operands[0], 2, 0, mode), base);
8645 8712
8646 DONE; 8713 DONE;
8647 }) 8714 })
8648 8715
8649 (define_expand "restore_stack_nonlocal" 8716 (define_expand "restore_stack_nonlocal"
8650 [(match_operand 0 "register_operand" "") 8717 [(match_operand 0 "register_operand" "")
8651 (match_operand 1 "memory_operand" "")] 8718 (match_operand 1 "memory_operand" "")]
8652 "" 8719 ""
8653 { 8720 {
8654 enum machine_mode mode = TARGET_64BIT ? OImode : TImode;
8655 rtx base = gen_rtx_REG (Pmode, BASE_REGNUM); 8721 rtx base = gen_rtx_REG (Pmode, BASE_REGNUM);
8656 rtx temp = NULL_RTX; 8722 rtx temp = NULL_RTX;
8657 8723
8658 /* Restore the backchain from the first word, sp from the second and the 8724 /* Restore the backchain from the first word, sp from the second and the
8659 literal pool base from the third. */ 8725 literal pool base from the third. */
8660 8726
8727 rtx save_bc = adjust_address (operands[1], Pmode, 0);
8728 rtx save_sp = adjust_address (operands[1], Pmode, GET_MODE_SIZE (Pmode));
8729 rtx save_bp = adjust_address (operands[1], Pmode, 2 * GET_MODE_SIZE (Pmode));
8730
8661 if (TARGET_BACKCHAIN) 8731 if (TARGET_BACKCHAIN)
8662 temp = force_reg (Pmode, operand_subword (operands[1], 0, 0, mode)); 8732 temp = force_reg (Pmode, save_bc);
8663 8733
8664 emit_move_insn (base, operand_subword (operands[1], 2, 0, mode)); 8734 emit_move_insn (base, save_bp);
8665 emit_move_insn (operands[0], operand_subword (operands[1], 1, 0, mode)); 8735 emit_move_insn (operands[0], save_sp);
8666 8736
8667 if (temp) 8737 if (temp)
8668 emit_move_insn (s390_back_chain_rtx (), temp); 8738 emit_move_insn (s390_back_chain_rtx (), temp);
8669 8739
8670 emit_use (base); 8740 emit_use (base);