Mercurial > hg > CbC > CbC_gcc
diff gcc/config/s390/s390.md @ 63:b7f97abdc517 gcc-4.6-20100522
update gcc from gcc-4.5.0 to gcc-4.6
| author | ryoma <e075725@ie.u-ryukyu.ac.jp> |
|---|---|
| date | Mon, 24 May 2010 12:47:05 +0900 |
| parents | 77e2b8dfacca |
| children | f6334be47118 |
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--- a/gcc/config/s390/s390.md Fri Feb 12 23:41:23 2010 +0900 +++ b/gcc/config/s390/s390.md Mon May 24 12:47:05 2010 +0900 @@ -1,6 +1,6 @@ ;;- Machine description for GNU compiler -- S/390 / zSeries version. ;; Copyright (C) 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, -;; 2009 Free Software Foundation, Inc. +;; 2009, 2010 Free Software Foundation, Inc. ;; Contributed by Hartmut Penner (hpenner@de.ibm.com) and ;; Ulrich Weigand (uweigand@de.ibm.com) and ;; Andreas Krebbel (Andreas.Krebbel@de.ibm.com) @@ -337,21 +337,25 @@ ;; These mode iterators allow 31-bit and 64-bit GPR patterns to be generated ;; from the same template. -(define_mode_iterator GPR [(DI "TARGET_64BIT") SI]) +(define_mode_iterator GPR [(DI "TARGET_ZARCH") SI]) (define_mode_iterator DSI [DI SI]) ;; These mode iterators allow :P to be used for patterns that operate on ;; pointer-sized quantities. Exactly one of the two alternatives will match. -(define_mode_iterator DP [(TI "TARGET_64BIT") (DI "!TARGET_64BIT")]) (define_mode_iterator P [(DI "TARGET_64BIT") (SI "!TARGET_64BIT")]) +;; These macros refer to the actual word_mode of the configuration. This is equal +;; to Pmode except on 31-bit machines in zarch mode. +(define_mode_iterator DW [(TI "TARGET_ZARCH") (DI "!TARGET_ZARCH")]) +(define_mode_iterator W [(DI "TARGET_ZARCH") (SI "!TARGET_ZARCH")]) + ;; This mode iterator allows the QI and HI patterns to be defined from ;; the same template. (define_mode_iterator HQI [HI QI]) ;; This mode iterator allows the integer patterns to be defined from the ;; same template. -(define_mode_iterator INT [(DI "TARGET_64BIT") SI HI QI]) +(define_mode_iterator INT [(DI "TARGET_ZARCH") SI HI QI]) (define_mode_iterator INTALL [TI DI SI HI QI]) ;; This iterator allows some 'ashift' and 'lshiftrt' pattern to be defined from @@ -455,7 +459,7 @@ ;; variant for long displacements. (define_mode_attr y [(DI "g") (SI "y")]) -;; In DP templates, a string like "cds<g>" will expand to "cdsg" in TImode +;; In DW templates, a string like "cds<g>" will expand to "cdsg" in TImode ;; and "cds" in DImode. (define_mode_attr tg [(TI "g") (DI "")]) @@ -506,7 +510,7 @@ (match_operand:DI 1 "immediate_operand" "N0HD0,N1HD0,N2HD0,N3HD0")) (match_operand:DI 2 "immediate_operand" "n,n,n,n")))] - "TARGET_64BIT + "TARGET_ZARCH && s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], true)) && s390_single_part (operands[1], DImode, HImode, 0) >= 0" "@ @@ -556,7 +560,7 @@ (match_operand:DI 1 "const0_operand" ""))) (set (match_operand:DI 2 "register_operand" "=d,d") (sign_extend:DI (match_dup 0)))] - "s390_match_ccmode(insn, CCSmode) && TARGET_64BIT" + "s390_match_ccmode(insn, CCSmode) && TARGET_ZARCH" "ltgfr\t%2,%0 ltgf\t%2,%0" [(set_attr "op_type" "RRE,RXY") @@ -596,7 +600,7 @@ (match_operand:DI 1 "const0_operand" ""))) (set (match_operand:DI 2 "register_operand" "=d") (match_dup 0))] - "s390_match_ccmode(insn, CCSmode) && TARGET_64BIT && !TARGET_EXTIMM" + "s390_match_ccmode(insn, CCSmode) && TARGET_ZARCH && !TARGET_EXTIMM" "ltgr\t%2,%0" [(set_attr "op_type" "RRE") (set_attr "z10prop" "z10_fr_E1")]) @@ -632,7 +636,7 @@ [(set (reg CC_REGNUM) (compare (match_operand:DI 0 "register_operand" "d") (match_operand:DI 1 "const0_operand" "")))] - "s390_match_ccmode(insn, CCSmode) && !TARGET_64BIT" + "s390_match_ccmode(insn, CCSmode) && !TARGET_ZARCH" "srda\t%0,0" [(set_attr "op_type" "RS") (set_attr "atype" "reg")]) @@ -720,7 +724,7 @@ [(set (reg CC_REGNUM) (compare (match_operand:DI 0 "nonimmediate_operand" "%d,d,d,d,Q") (match_operand:DI 1 "general_operand" "d,K,Os,RT,BQ")))] - "s390_match_ccmode (insn, CCTmode) && TARGET_64BIT" + "s390_match_ccmode (insn, CCTmode) && TARGET_ZARCH" "@ cgr\t%0,%1 cghi\t%0,%h1 @@ -752,7 +756,7 @@ (compare (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,RT,b")) (match_operand:DI 0 "register_operand" "d, d,d")))] - "s390_match_ccmode(insn, CCSRmode) && TARGET_64BIT" + "s390_match_ccmode(insn, CCSRmode) && TARGET_ZARCH" "@ cgfr\t%0,%1 cgf\t%0,%1 @@ -847,7 +851,7 @@ (compare (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,RT,b")) (match_operand:DI 0 "register_operand" "d, d,d")))] - "s390_match_ccmode (insn, CCURmode) && TARGET_64BIT" + "s390_match_ccmode (insn, CCURmode) && TARGET_ZARCH" "@ clgfr\t%0,%1 clgf\t%0,%1 @@ -863,7 +867,7 @@ "d, d,d,Q, d, Q,BQ") (match_operand:DI 1 "general_operand" "d,Op,b,D,RT,BQ,Q")))] - "s390_match_ccmode (insn, CCUmode) && TARGET_64BIT" + "s390_match_ccmode (insn, CCUmode) && TARGET_ZARCH" "@ clgr\t%0,%1 clgfi\t%0,%1 @@ -1115,7 +1119,7 @@ (define_insn "movti" [(set (match_operand:TI 0 "nonimmediate_operand" "=d,QS,d,o") (match_operand:TI 1 "general_operand" "QS,d,dPRT,d"))] - "TARGET_64BIT" + "TARGET_ZARCH" "@ lmg\t%0,%N0,%S1 stmg\t%1,%N1,%S0 @@ -1127,7 +1131,7 @@ (define_split [(set (match_operand:TI 0 "nonimmediate_operand" "") (match_operand:TI 1 "general_operand" ""))] - "TARGET_64BIT && reload_completed + "TARGET_ZARCH && reload_completed && s390_split_ok_p (operands[0], operands[1], TImode, 0)" [(set (match_dup 2) (match_dup 4)) (set (match_dup 3) (match_dup 5))] @@ -1141,7 +1145,7 @@ (define_split [(set (match_operand:TI 0 "nonimmediate_operand" "") (match_operand:TI 1 "general_operand" ""))] - "TARGET_64BIT && reload_completed + "TARGET_ZARCH && reload_completed && s390_split_ok_p (operands[0], operands[1], TImode, 1)" [(set (match_dup 2) (match_dup 4)) (set (match_dup 3) (match_dup 5))] @@ -1155,11 +1159,12 @@ (define_split [(set (match_operand:TI 0 "register_operand" "") (match_operand:TI 1 "memory_operand" ""))] - "TARGET_64BIT && reload_completed + "TARGET_ZARCH && reload_completed && !s_operand (operands[1], VOIDmode)" [(set (match_dup 0) (match_dup 1))] { rtx addr = operand_subword (operands[0], 1, 0, TImode); + addr = gen_lowpart (Pmode, addr); s390_load_address (addr, XEXP (operands[1], 0)); operands[1] = replace_equiv_address (operands[1], addr); }) @@ -1308,7 +1313,7 @@ (match_operand:DI 1 "general_operand" "K,N0HD0,N1HD0,N2HD0,N3HD0,Os,N0SD0,N1SD0,d,f,L,b,d,RT, d,*f,R,T,*f,*f,d,K,t,d,t,Q"))] - "TARGET_64BIT" + "TARGET_ZARCH" "@ lghi\t%0,%h1 llihh\t%0,%i1 @@ -1375,7 +1380,7 @@ (define_split [(set (match_operand:DI 0 "register_operand" "") (match_operand:DI 1 "register_operand" ""))] - "TARGET_64BIT && ACCESS_REG_P (operands[1])" + "TARGET_ZARCH && ACCESS_REG_P (operands[1])" [(set (match_dup 2) (match_dup 3)) (set (match_dup 0) (ashift:DI (match_dup 0) (const_int 32))) (set (strict_low_part (match_dup 2)) (match_dup 4))] @@ -1385,7 +1390,7 @@ (define_split [(set (match_operand:DI 0 "register_operand" "") (match_operand:DI 1 "register_operand" ""))] - "TARGET_64BIT && ACCESS_REG_P (operands[0]) + "TARGET_ZARCH && ACCESS_REG_P (operands[0]) && dead_or_set_p (insn, operands[1])" [(set (match_dup 3) (match_dup 2)) (set (match_dup 1) (lshiftrt:DI (match_dup 1) (const_int 32))) @@ -1396,7 +1401,7 @@ (define_split [(set (match_operand:DI 0 "register_operand" "") (match_operand:DI 1 "register_operand" ""))] - "TARGET_64BIT && ACCESS_REG_P (operands[0]) + "TARGET_ZARCH && ACCESS_REG_P (operands[0]) && !dead_or_set_p (insn, operands[1])" [(set (match_dup 3) (match_dup 2)) (set (match_dup 1) (rotate:DI (match_dup 1) (const_int 32))) @@ -1410,7 +1415,7 @@ "=d,d,Q,S,d ,o,!*f,!*f,!*f,!R,!T,d") (match_operand:DI 1 "general_operand" " Q,S,d,d,dPRT,d, *f, R, T,*f,*f,b"))] - "!TARGET_64BIT" + "!TARGET_ZARCH" "@ lm\t%0,%N0,%S1 lmy\t%0,%N0,%S1 @@ -1433,7 +1438,7 @@ (define_split [(set (match_operand:DI 0 "register_operand" "") (match_operand:DI 1 "memory_operand" ""))] - "!TARGET_64BIT && reload_completed && TARGET_Z10 + "!TARGET_ZARCH && reload_completed && TARGET_Z10 && larl_operand (XEXP (operands[1], 0), SImode)" [(set (match_dup 2) (match_dup 3)) (set (match_dup 0) (match_dup 1))] @@ -1446,7 +1451,7 @@ (define_split [(set (match_operand:DI 0 "nonimmediate_operand" "") (match_operand:DI 1 "general_operand" ""))] - "!TARGET_64BIT && reload_completed + "!TARGET_ZARCH && reload_completed && s390_split_ok_p (operands[0], operands[1], DImode, 0)" [(set (match_dup 2) (match_dup 4)) (set (match_dup 3) (match_dup 5))] @@ -1460,7 +1465,7 @@ (define_split [(set (match_operand:DI 0 "nonimmediate_operand" "") (match_operand:DI 1 "general_operand" ""))] - "!TARGET_64BIT && reload_completed + "!TARGET_ZARCH && reload_completed && s390_split_ok_p (operands[0], operands[1], DImode, 1)" [(set (match_dup 2) (match_dup 4)) (set (match_dup 3) (match_dup 5))] @@ -1474,7 +1479,7 @@ (define_split [(set (match_operand:DI 0 "register_operand" "") (match_operand:DI 1 "memory_operand" ""))] - "!TARGET_64BIT && reload_completed + "!TARGET_ZARCH && reload_completed && !FP_REG_P (operands[0]) && !s_operand (operands[1], VOIDmode)" [(set (match_dup 0) (match_dup 1))] @@ -1487,7 +1492,7 @@ (define_peephole2 [(set (match_operand:DI 0 "register_operand" "") (mem:DI (match_operand 1 "address_operand" "")))] - "TARGET_64BIT + "TARGET_ZARCH && !FP_REG_P (operands[0]) && GET_CODE (operands[1]) == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P (operands[1]) @@ -1826,16 +1831,16 @@ && register_operand (operands[0], VOIDmode) && GET_CODE (operands[1]) == MEM) { - rtx tmp = gen_reg_rtx (word_mode); - rtx ext = gen_rtx_ZERO_EXTEND (word_mode, operands[1]); + rtx tmp = gen_reg_rtx (DImode); + rtx ext = gen_rtx_ZERO_EXTEND (DImode, operands[1]); emit_insn (gen_rtx_SET (VOIDmode, tmp, ext)); operands[1] = gen_lowpart (QImode, tmp); } }) (define_insn "*movqi" - [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,d,d,R,T,Q,S") - (match_operand:QI 1 "general_operand" "d,n,R,T,d,d,n,n"))] + [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,d,d,R,T,Q,S,?Q") + (match_operand:QI 1 "general_operand" " d,n,R,T,d,d,n,n,?Q"))] "" "@ lr\t%0,%1 @@ -1845,9 +1850,10 @@ stc\t%1,%0 stcy\t%1,%0 mvi\t%S0,%b1 - mviy\t%S0,%b1" - [(set_attr "op_type" "RR,RI,RX,RXY,RX,RXY,SI,SIY") - (set_attr "type" "lr,*,*,*,store,store,store,store") + mviy\t%S0,%b1 + *" + [(set_attr "op_type" "RR,RI,RX,RXY,RX,RXY,SI,SIY,SS") + (set_attr "type" "lr,*,*,*,store,store,store,store,*") (set_attr "z10prop" "z10_fr_E1, z10_fwd_A1, z10_super_E1, @@ -1855,7 +1861,8 @@ z10_rec, z10_rec, z10_super, - z10_super")]) + z10_super, + *")]) (define_peephole2 [(set (match_operand:QI 0 "nonimmediate_operand" "") @@ -1903,7 +1910,7 @@ (define_insn "movstrictsi" [(set (strict_low_part (match_operand:SI 0 "register_operand" "+d,d,d,d")) (match_operand:SI 1 "general_operand" "d,R,T,t"))] - "TARGET_64BIT" + "TARGET_ZARCH" "@ lr\t%0,%1 l\t%0,%1 @@ -1926,7 +1933,7 @@ (define_insn "*mov<mode>_64" [(set (match_operand:TD_TF 0 "nonimmediate_operand" "=f,f,f,o, d,QS, d,o") (match_operand:TD_TF 1 "general_operand" " G,f,o,f,QS, d,dRT,d"))] - "TARGET_64BIT" + "TARGET_ZARCH" "@ lzxr\t%0 lxr\t%0,%1 @@ -1942,7 +1949,7 @@ (define_insn "*mov<mode>_31" [(set (match_operand:TD_TF 0 "nonimmediate_operand" "=f,f,f,o") (match_operand:TD_TF 1 "general_operand" " G,f,o,f"))] - "!TARGET_64BIT" + "!TARGET_ZARCH" "@ lzxr\t%0 lxr\t%0,%1 @@ -1956,7 +1963,7 @@ (define_split [(set (match_operand:TD_TF 0 "nonimmediate_operand" "") (match_operand:TD_TF 1 "general_operand" ""))] - "TARGET_64BIT && reload_completed + "TARGET_ZARCH && reload_completed && s390_split_ok_p (operands[0], operands[1], <MODE>mode, 0)" [(set (match_dup 2) (match_dup 4)) (set (match_dup 3) (match_dup 5))] @@ -1970,7 +1977,7 @@ (define_split [(set (match_operand:TD_TF 0 "nonimmediate_operand" "") (match_operand:TD_TF 1 "general_operand" ""))] - "TARGET_64BIT && reload_completed + "TARGET_ZARCH && reload_completed && s390_split_ok_p (operands[0], operands[1], <MODE>mode, 1)" [(set (match_dup 2) (match_dup 4)) (set (match_dup 3) (match_dup 5))] @@ -1984,7 +1991,7 @@ (define_split [(set (match_operand:TD_TF 0 "register_operand" "") (match_operand:TD_TF 1 "memory_operand" ""))] - "TARGET_64BIT && reload_completed + "TARGET_ZARCH && reload_completed && !FP_REG_P (operands[0]) && !s_operand (operands[1], VOIDmode)" [(set (match_dup 0) (match_dup 1))] @@ -2043,7 +2050,7 @@ "=f,f,f,d,f,f,R,T,d, d,RT") (match_operand:DD_DF 1 "general_operand" " G,f,d,f,R,T,f,f,d,RT, d"))] - "TARGET_64BIT && TARGET_DFP" + "TARGET_DFP" "@ lzdr\t%0 ldr\t%0,%1 @@ -2075,7 +2082,7 @@ (define_insn "*mov<mode>_64" [(set (match_operand:DD_DF 0 "nonimmediate_operand" "=f,f,f,f,R,T,d, d,RT") (match_operand:DD_DF 1 "general_operand" "G,f,R,T,f,f,d,RT, d"))] - "TARGET_64BIT" + "TARGET_ZARCH" "@ lzdr\t%0 ldr\t%0,%1 @@ -2104,7 +2111,7 @@ "=f,f,f,f,R,T,d,d,Q,S, d,o") (match_operand:DD_DF 1 "general_operand" " G,f,R,T,f,f,Q,S,d,d,dPRT,d"))] - "!TARGET_64BIT" + "!TARGET_ZARCH" "@ lzdr\t%0 ldr\t%0,%1 @@ -2125,7 +2132,7 @@ (define_split [(set (match_operand:DD_DF 0 "nonimmediate_operand" "") (match_operand:DD_DF 1 "general_operand" ""))] - "!TARGET_64BIT && reload_completed + "!TARGET_ZARCH && reload_completed && s390_split_ok_p (operands[0], operands[1], <MODE>mode, 0)" [(set (match_dup 2) (match_dup 4)) (set (match_dup 3) (match_dup 5))] @@ -2139,7 +2146,7 @@ (define_split [(set (match_operand:DD_DF 0 "nonimmediate_operand" "") (match_operand:DD_DF 1 "general_operand" ""))] - "!TARGET_64BIT && reload_completed + "!TARGET_ZARCH && reload_completed && s390_split_ok_p (operands[0], operands[1], <MODE>mode, 1)" [(set (match_dup 2) (match_dup 4)) (set (match_dup 3) (match_dup 5))] @@ -2153,7 +2160,7 @@ (define_split [(set (match_operand:DD_DF 0 "register_operand" "") (match_operand:DD_DF 1 "memory_operand" ""))] - "!TARGET_64BIT && reload_completed + "!TARGET_ZARCH && reload_completed && !FP_REG_P (operands[0]) && !s_operand (operands[1], VOIDmode)" [(set (match_dup 0) (match_dup 1))] @@ -2232,6 +2239,22 @@ "mvc\t%O0(%2,%R0),%S1" [(set_attr "op_type" "SS")]) +; This splitter converts a QI to QI mode copy into a BLK mode copy in +; order to have it implemented with mvc. + +(define_split + [(set (match_operand:QI 0 "memory_operand" "") + (match_operand:QI 1 "memory_operand" ""))] + "reload_completed" + [(parallel + [(set (match_dup 0) (match_dup 1)) + (use (const_int 1))])] +{ + operands[0] = adjust_address (operands[0], BLKmode, 0); + operands[1] = adjust_address (operands[1], BLKmode, 0); +}) + + (define_peephole2 [(parallel [(set (match_operand:BLK 0 "memory_operand" "") @@ -2286,7 +2309,7 @@ count = INTVAL (operands[2]); regno = REGNO (operands[0]); mode = GET_MODE (operands[0]); - if (mode != SImode && mode != word_mode) + if (mode != SImode && (!TARGET_ZARCH || mode != DImode)) FAIL; operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count)); @@ -2324,7 +2347,7 @@ [(match_parallel 0 "load_multiple_operation" [(set (match_operand:DI 1 "register_operand" "=r") (match_operand:DI 2 "s_operand" "QS"))])] - "reload_completed && word_mode == DImode" + "reload_completed && TARGET_ZARCH" { int words = XVECLEN (operands[0], 0); operands[0] = gen_rtx_REG (DImode, REGNO (operands[1]) + words - 1); @@ -2375,7 +2398,7 @@ count = INTVAL (operands[2]); regno = REGNO (operands[1]); mode = GET_MODE (operands[1]); - if (mode != SImode && mode != word_mode) + if (mode != SImode && (!TARGET_ZARCH || mode != DImode)) FAIL; operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count)); @@ -2415,7 +2438,7 @@ [(match_parallel 0 "store_multiple_operation" [(set (match_operand:DI 1 "s_operand" "=QS") (match_operand:DI 2 "register_operand" "r"))])] - "reload_completed && word_mode == DImode" + "reload_completed && TARGET_ZARCH" { int words = XVECLEN (operands[0], 0); operands[0] = gen_rtx_REG (DImode, REGNO (operands[2]) + words - 1); @@ -2697,11 +2720,12 @@ (clobber (reg:CC CC_REGNUM))])] "" { - enum machine_mode dword_mode = word_mode == DImode ? TImode : DImode; - rtx reg0 = gen_reg_rtx (dword_mode); - rtx reg1 = gen_reg_rtx (dword_mode); - rtx addr0 = gen_lowpart (Pmode, gen_highpart (word_mode, reg0)); - rtx addr1 = gen_lowpart (Pmode, gen_highpart (word_mode, reg1)); + enum machine_mode sreg_mode = TARGET_ZARCH ? DImode : SImode; + enum machine_mode dreg_mode = TARGET_ZARCH ? TImode : DImode; + rtx reg0 = gen_reg_rtx (dreg_mode); + rtx reg1 = gen_reg_rtx (dreg_mode); + rtx addr0 = gen_lowpart (Pmode, gen_highpart (sreg_mode, reg0)); + rtx addr1 = gen_lowpart (Pmode, gen_highpart (sreg_mode, reg1)); rtx len0 = gen_lowpart (Pmode, reg0); rtx len1 = gen_lowpart (Pmode, reg1); @@ -2727,7 +2751,20 @@ (use (match_dup 2)) (use (match_dup 3)) (clobber (reg:CC CC_REGNUM))] - "" + "TARGET_64BIT || !TARGET_ZARCH" + "mvcle\t%0,%1,0\;jo\t.-4" + [(set_attr "length" "8") + (set_attr "type" "vs")]) + +(define_insn "*movmem_long_31z" + [(clobber (match_operand:TI 0 "register_operand" "=d")) + (clobber (match_operand:TI 1 "register_operand" "=d")) + (set (mem:BLK (subreg:SI (match_operand:TI 2 "register_operand" "0") 4)) + (mem:BLK (subreg:SI (match_operand:TI 3 "register_operand" "1") 4))) + (use (match_dup 2)) + (use (match_dup 3)) + (clobber (reg:CC CC_REGNUM))] + "!TARGET_64BIT && TARGET_ZARCH" "mvcle\t%0,%1,0\;jo\t.-4" [(set_attr "length" "8") (set_attr "type" "vs")]) @@ -2899,10 +2936,11 @@ (clobber (reg:CC CC_REGNUM))])] "" { - enum machine_mode dword_mode = word_mode == DImode ? TImode : DImode; - rtx reg0 = gen_reg_rtx (dword_mode); - rtx reg1 = gen_reg_rtx (dword_mode); - rtx addr0 = gen_lowpart (Pmode, gen_highpart (word_mode, reg0)); + enum machine_mode sreg_mode = TARGET_ZARCH ? DImode : SImode; + enum machine_mode dreg_mode = TARGET_ZARCH ? TImode : DImode; + rtx reg0 = gen_reg_rtx (dreg_mode); + rtx reg1 = gen_reg_rtx (dreg_mode); + rtx addr0 = gen_lowpart (Pmode, gen_highpart (sreg_mode, reg0)); rtx len0 = gen_lowpart (Pmode, reg0); emit_clobber (reg0); @@ -2923,7 +2961,7 @@ (use (match_dup 3)) (use (match_operand:<DBL> 1 "register_operand" "d")) (clobber (reg:CC CC_REGNUM))] - "" + "TARGET_64BIT || !TARGET_ZARCH" "mvcle\t%0,%1,%Y2\;jo\t.-4" [(set_attr "length" "8") (set_attr "type" "vs")]) @@ -2936,10 +2974,24 @@ (use (match_dup 3)) (use (match_operand:<DBL> 1 "register_operand" "d")) (clobber (reg:CC CC_REGNUM))] - "(INTVAL (operands[4]) & 255) == 255" + "(TARGET_64BIT || !TARGET_ZARCH) && + (INTVAL (operands[4]) & 255) == 255" "mvcle\t%0,%1,%Y2\;jo\t.-4" [(set_attr "length" "8") (set_attr "type" "vs")]) + +(define_insn "*setmem_long_31z" + [(clobber (match_operand:TI 0 "register_operand" "=d")) + (set (mem:BLK (subreg:SI (match_operand:TI 3 "register_operand" "0") 4)) + (match_operand 2 "shift_count_or_setmem_operand" "Y")) + (use (match_dup 3)) + (use (match_operand:TI 1 "register_operand" "d")) + (clobber (reg:CC CC_REGNUM))] + "!TARGET_64BIT && TARGET_ZARCH" + "mvcle\t%0,%1,%Y2\;jo\t.-4" + [(set_attr "length" "8") + (set_attr "type" "vs")]) + ; ; cmpmemM instruction pattern(s). ; @@ -3053,11 +3105,12 @@ (use (match_dup 3))])] "" { - enum machine_mode dword_mode = word_mode == DImode ? TImode : DImode; - rtx reg0 = gen_reg_rtx (dword_mode); - rtx reg1 = gen_reg_rtx (dword_mode); - rtx addr0 = gen_lowpart (Pmode, gen_highpart (word_mode, reg0)); - rtx addr1 = gen_lowpart (Pmode, gen_highpart (word_mode, reg1)); + enum machine_mode sreg_mode = TARGET_ZARCH ? DImode : SImode; + enum machine_mode dreg_mode = TARGET_ZARCH ? TImode : DImode; + rtx reg0 = gen_reg_rtx (dreg_mode); + rtx reg1 = gen_reg_rtx (dreg_mode); + rtx addr0 = gen_lowpart (Pmode, gen_highpart (sreg_mode, reg0)); + rtx addr1 = gen_lowpart (Pmode, gen_highpart (sreg_mode, reg1)); rtx len0 = gen_lowpart (Pmode, reg0); rtx len1 = gen_lowpart (Pmode, reg1); @@ -3083,11 +3136,25 @@ (mem:BLK (subreg:P (match_operand:<DBL> 3 "register_operand" "1") 0)))) (use (match_dup 2)) (use (match_dup 3))] - "" + "TARGET_64BIT || !TARGET_ZARCH" "clcle\t%0,%1,0\;jo\t.-4" [(set_attr "length" "8") (set_attr "type" "vs")]) +(define_insn "*cmpmem_long_31z" + [(clobber (match_operand:TI 0 "register_operand" "=d")) + (clobber (match_operand:TI 1 "register_operand" "=d")) + (set (reg:CCU CC_REGNUM) + (compare:CCU (mem:BLK (subreg:SI (match_operand:TI 2 "register_operand" "0") 4)) + (mem:BLK (subreg:SI (match_operand:TI 3 "register_operand" "1") 4)))) + (use (match_dup 2)) + (use (match_dup 3))] + "!TARGET_64BIT && TARGET_ZARCH" + "clcle\t%0,%1,0\;jo\t.-4" + [(set_attr "op_type" "NN") + (set_attr "type" "vs") + (set_attr "length" "8")]) + ; Convert CCUmode condition code to integer. ; Result is zero if EQ, positive if LTU, negative if GTU. @@ -3129,7 +3196,7 @@ (sign_extend:DI (unspec:SI [(match_operand:CCU 1 "register_operand" "0")] UNSPEC_CCU_TO_INT))) (clobber (reg:CC CC_REGNUM))] - "TARGET_64BIT" + "TARGET_ZARCH" "#" "&& reload_completed" [(set (match_dup 0) (ashift:DI (match_dup 0) (const_int 34))) @@ -3146,7 +3213,7 @@ (const_int 0))) (set (match_operand:DI 0 "register_operand" "=d") (sign_extend:DI (unspec:SI [(match_dup 1)] UNSPEC_CCU_TO_INT)))] - "s390_match_ccmode (insn, CCSmode) && TARGET_64BIT" + "s390_match_ccmode (insn, CCSmode) && TARGET_ZARCH" "#" "&& reload_completed" [(set (match_dup 0) (ashift:DI (match_dup 0) (const_int 34))) @@ -3181,7 +3248,7 @@ (unspec:DI [(match_operand:BLK 1 "s_operand" "QS") (match_operand 2 "const_int_operand" "n")] UNSPEC_ICM)) (clobber (reg:CC CC_REGNUM))] - "TARGET_64BIT" + "TARGET_ZARCH" "icmh\t%0,%2,%S1" [(set_attr "op_type" "RSY") (set_attr "z10prop" "z10_super")]) @@ -3191,7 +3258,7 @@ (unspec:DI [(match_operand:BLK 1 "s_operand" "Q,S") (match_operand 2 "const_int_operand" "n,n")] UNSPEC_ICM)) (clobber (reg:CC CC_REGNUM))] - "!TARGET_64BIT" + "!TARGET_ZARCH" "@ icm\t%0,%2,%S1 icmy\t%0,%2,%S1" @@ -3347,10 +3414,10 @@ [(set_attr "op_type" "RIE")]) (define_insn "*insv<mode>_mem_reg" - [(set (zero_extract:P (match_operand:QI 0 "memory_operand" "+Q,S") + [(set (zero_extract:W (match_operand:QI 0 "memory_operand" "+Q,S") (match_operand 1 "const_int_operand" "n,n") (const_int 0)) - (match_operand:P 2 "register_operand" "d,d"))] + (match_operand:W 2 "register_operand" "d,d"))] "INTVAL (operands[1]) > 0 && INTVAL (operands[1]) <= GET_MODE_BITSIZE (SImode) && INTVAL (operands[1]) % BITS_PER_UNIT == 0" @@ -3370,7 +3437,7 @@ (const_int 0)) (lshiftrt:DI (match_operand:DI 2 "register_operand" "d") (const_int 32)))] - "TARGET_64BIT + "TARGET_ZARCH && INTVAL (operands[1]) > 0 && INTVAL (operands[1]) <= GET_MODE_BITSIZE (SImode) && INTVAL (operands[1]) % BITS_PER_UNIT == 0" @@ -3383,11 +3450,11 @@ [(set_attr "op_type" "RSY") (set_attr "z10prop" "z10_super")]) -(define_insn "*insv<mode>_reg_imm" - [(set (zero_extract:P (match_operand:P 0 "register_operand" "+d") - (const_int 16) - (match_operand 1 "const_int_operand" "n")) - (match_operand:P 2 "const_int_operand" "n"))] +(define_insn "*insvdi_reg_imm" + [(set (zero_extract:DI (match_operand:DI 0 "register_operand" "+d") + (const_int 16) + (match_operand 1 "const_int_operand" "n")) + (match_operand:DI 2 "const_int_operand" "n"))] "TARGET_ZARCH && INTVAL (operands[1]) >= 0 && INTVAL (operands[1]) < BITS_PER_WORD @@ -3437,7 +3504,7 @@ (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")))] "" { - if (!TARGET_64BIT) + if (!TARGET_ZARCH) { emit_clobber (operands[0]); emit_move_insn (gen_highpart (SImode, operands[0]), operands[1]); @@ -3450,7 +3517,7 @@ (define_insn "*extendsidi2" [(set (match_operand:DI 0 "register_operand" "=d,d,d") (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,RT,b")))] - "TARGET_64BIT" + "TARGET_ZARCH" "@ lgfr\t%0,%1 lgf\t%0,%1 @@ -3469,7 +3536,7 @@ (sign_extend:DSI (match_operand:HQI 1 "nonimmediate_operand" "")))] "" { - if (<DSI:MODE>mode == DImode && !TARGET_64BIT) + if (<DSI:MODE>mode == DImode && !TARGET_ZARCH) { rtx tmp = gen_reg_rtx (SImode); emit_insn (gen_extend<HQI:mode>si2 (tmp, operands[1])); @@ -3495,7 +3562,7 @@ (define_insn "*extendhidi2_extimm" [(set (match_operand:DI 0 "register_operand" "=d,d,d") (sign_extend:DI (match_operand:HI 1 "general_operand" "d,RT,b")))] - "TARGET_64BIT && TARGET_EXTIMM" + "TARGET_ZARCH && TARGET_EXTIMM" "@ lghr\t%0,%1 lgh\t%0,%1 @@ -3508,7 +3575,7 @@ (define_insn "*extendhidi2" [(set (match_operand:DI 0 "register_operand" "=d") (sign_extend:DI (match_operand:HI 1 "memory_operand" "RT")))] - "TARGET_64BIT" + "TARGET_ZARCH" "lgh\t%0,%1" [(set_attr "op_type" "RXY") (set_attr "z10prop" "z10_super_E1")]) @@ -3594,7 +3661,7 @@ (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")))] "" { - if (!TARGET_64BIT) + if (!TARGET_ZARCH) { emit_clobber (operands[0]); emit_move_insn (gen_lowpart (SImode, operands[0]), operands[1]); @@ -3606,7 +3673,7 @@ (define_insn "*zero_extendsidi2" [(set (match_operand:DI 0 "register_operand" "=d,d,d") (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,RT,b")))] - "TARGET_64BIT" + "TARGET_ZARCH" "@ llgfr\t%0,%1 llgf\t%0,%1 @@ -3624,7 +3691,7 @@ [(set (match_operand:DI 0 "register_operand" "=d") (and:DI (subreg:DI (match_operand:SI 1 "memory_operand" "RT") 0) (const_int 2147483647)))] - "TARGET_64BIT" + "TARGET_ZARCH" "llgt\t%0,%1" [(set_attr "op_type" "RXE") (set_attr "z10prop" "z10_super_E1")]) @@ -3634,7 +3701,7 @@ (and:DI (subreg:DI (match_operand:SI 1 "memory_operand" "RT") 0) (const_int 2147483647))) (clobber (reg:CC CC_REGNUM))] - "TARGET_64BIT" + "TARGET_ZARCH" "#" "&& reload_completed" [(set (match_dup 0) @@ -3657,7 +3724,7 @@ [(set (match_operand:DI 0 "register_operand" "=d,d") (and:DI (match_operand:DI 1 "nonimmediate_operand" "d,o") (const_int 2147483647)))] - "TARGET_64BIT" + "TARGET_ZARCH" "@ llgtr\t%0,%1 llgt\t%0,%N1" @@ -3665,13 +3732,13 @@ (set_attr "z10prop" "z10_super_E1,z10_super_E1")]) (define_split - [(set (match_operand:GPR 0 "register_operand" "") - (and:GPR (match_operand:GPR 1 "nonimmediate_operand" "") + [(set (match_operand:DSI 0 "register_operand" "") + (and:DSI (match_operand:DSI 1 "nonimmediate_operand" "") (const_int 2147483647))) (clobber (reg:CC CC_REGNUM))] "TARGET_ZARCH && reload_completed" [(set (match_dup 0) - (and:GPR (match_dup 1) + (and:DSI (match_dup 1) (const_int 2147483647)))] "") @@ -3684,7 +3751,7 @@ (zero_extend:DI (match_operand:HQI 1 "nonimmediate_operand" "")))] "" { - if (!TARGET_64BIT) + if (!TARGET_ZARCH) { rtx tmp = gen_reg_rtx (SImode); emit_insn (gen_zero_extend<mode>si2 (tmp, operands[1])); @@ -3936,7 +4003,7 @@ (define_expand "fix_trunc<mode>di2" [(set (match_operand:DI 0 "register_operand" "") (fix:DI (match_operand:DFP 1 "nonimmediate_operand" "")))] - "TARGET_64BIT && TARGET_HARD_DFP" + "TARGET_ZARCH && TARGET_HARD_DFP" { operands[1] = force_reg (<MODE>mode, operands[1]); emit_insn (gen_fix_trunc<mode>di2_dfp (operands[0], operands[1], @@ -3950,7 +4017,7 @@ (fix:DI (match_operand:DFP 1 "register_operand" "f"))) (unspec:DI [(match_operand:DI 2 "immediate_operand" "K")] UNSPEC_ROUND) (clobber (reg:CC CC_REGNUM))] - "TARGET_64BIT && TARGET_HARD_DFP" + "TARGET_ZARCH && TARGET_HARD_DFP" "cg<DFP:xde>tr\t%0,%h2,%1" [(set_attr "op_type" "RRF") (set_attr "type" "ftoidfp")]) @@ -3977,7 +4044,7 @@ (define_insn "floatdi<mode>2" [(set (match_operand:FP 0 "register_operand" "=f") (float:FP (match_operand:DI 1 "register_operand" "d")))] - "TARGET_64BIT && TARGET_HARD_FLOAT" + "TARGET_ZARCH && TARGET_HARD_FLOAT" "c<xde>g<bt>r\t%0,%1" [(set_attr "op_type" "RRE") (set_attr "type" "itof<mode>" )]) @@ -4219,7 +4286,7 @@ (plus:TI (match_operand:TI 1 "nonimmediate_operand" "%0") (match_operand:TI 2 "general_operand" "do") ) ) (clobber (reg:CC CC_REGNUM))] - "TARGET_64BIT" + "TARGET_ZARCH" "#" "&& reload_completed" [(parallel @@ -4257,7 +4324,7 @@ (plus:DI (sign_extend:DI (match_operand:SI 2 "general_operand" "d,RT")) (match_operand:DI 1 "register_operand" "0,0"))) (clobber (reg:CC CC_REGNUM))] - "TARGET_64BIT" + "TARGET_ZARCH" "@ agfr\t%0,%2 agf\t%0,%2" @@ -4270,7 +4337,7 @@ (const_int 0))) (set (match_operand:DI 0 "register_operand" "=d,d") (plus:DI (zero_extend:DI (match_dup 2)) (match_dup 1)))] - "s390_match_ccmode (insn, CCLmode) && TARGET_64BIT" + "s390_match_ccmode (insn, CCLmode) && TARGET_ZARCH" "@ algfr\t%0,%2 algf\t%0,%2" @@ -4283,7 +4350,7 @@ (match_operand:DI 1 "register_operand" "0,0")) (const_int 0))) (clobber (match_scratch:DI 0 "=d,d"))] - "s390_match_ccmode (insn, CCLmode) && TARGET_64BIT" + "s390_match_ccmode (insn, CCLmode) && TARGET_ZARCH" "@ algfr\t%0,%2 algf\t%0,%2" @@ -4295,7 +4362,7 @@ (plus:DI (zero_extend:DI (match_operand:SI 2 "general_operand" "d,RT")) (match_operand:DI 1 "register_operand" "0,0"))) (clobber (reg:CC CC_REGNUM))] - "TARGET_64BIT" + "TARGET_ZARCH" "@ algfr\t%0,%2 algf\t%0,%2" @@ -4307,7 +4374,7 @@ (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0") (match_operand:DI 2 "general_operand" "do") ) ) (clobber (reg:CC CC_REGNUM))] - "!TARGET_64BIT && TARGET_CPU_ZARCH" + "!TARGET_ZARCH && TARGET_CPU_ZARCH" "#" "&& reload_completed" [(parallel @@ -4627,7 +4694,7 @@ (minus:TI (match_operand:TI 1 "register_operand" "0") (match_operand:TI 2 "general_operand" "do") ) ) (clobber (reg:CC CC_REGNUM))] - "TARGET_64BIT" + "TARGET_ZARCH" "#" "&& reload_completed" [(parallel @@ -4664,7 +4731,7 @@ (minus:DI (match_operand:DI 1 "register_operand" "0,0") (sign_extend:DI (match_operand:SI 2 "general_operand" "d,RT")))) (clobber (reg:CC CC_REGNUM))] - "TARGET_64BIT" + "TARGET_ZARCH" "@ sgfr\t%0,%2 sgf\t%0,%2" @@ -4678,7 +4745,7 @@ (const_int 0))) (set (match_operand:DI 0 "register_operand" "=d,d") (minus:DI (match_dup 1) (zero_extend:DI (match_dup 2))))] - "s390_match_ccmode (insn, CCLmode) && TARGET_64BIT" + "s390_match_ccmode (insn, CCLmode) && TARGET_ZARCH" "@ slgfr\t%0,%2 slgf\t%0,%2" @@ -4691,7 +4758,7 @@ (zero_extend:DI (match_operand:SI 2 "general_operand" "d,RT"))) (const_int 0))) (clobber (match_scratch:DI 0 "=d,d"))] - "s390_match_ccmode (insn, CCLmode) && TARGET_64BIT" + "s390_match_ccmode (insn, CCLmode) && TARGET_ZARCH" "@ slgfr\t%0,%2 slgf\t%0,%2" @@ -4703,7 +4770,7 @@ (minus:DI (match_operand:DI 1 "register_operand" "0,0") (zero_extend:DI (match_operand:SI 2 "general_operand" "d,RT")))) (clobber (reg:CC CC_REGNUM))] - "TARGET_64BIT" + "TARGET_ZARCH" "@ slgfr\t%0,%2 slgf\t%0,%2" @@ -4715,7 +4782,7 @@ (minus:DI (match_operand:DI 1 "register_operand" "0") (match_operand:DI 2 "general_operand" "do") ) ) (clobber (reg:CC CC_REGNUM))] - "!TARGET_64BIT && TARGET_CPU_ZARCH" + "!TARGET_ZARCH && TARGET_CPU_ZARCH" "#" "&& reload_completed" [(parallel @@ -5179,7 +5246,7 @@ [(set (match_operand:DI 0 "register_operand" "=d,d") (mult:DI (sign_extend:DI (match_operand:SI 2 "general_operand" "d,RT")) (match_operand:DI 1 "register_operand" "0,0")))] - "TARGET_64BIT" + "TARGET_ZARCH" "@ msgfr\t%0,%2 msgf\t%0,%2" @@ -5190,7 +5257,7 @@ [(set (match_operand:DI 0 "register_operand" "=d,d,d,d") (mult:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0,0,0") (match_operand:DI 2 "general_operand" "d,K,RT,Os")))] - "TARGET_64BIT" + "TARGET_ZARCH" "@ msgr\t%0,%2 mghi\t%0,%h2 @@ -5241,7 +5308,7 @@ (match_operand:SI 1 "register_operand" "%0,0,0")) (sign_extend:DI (match_operand:SI 2 "nonimmediate_operand" "d,R,T"))))] - "!TARGET_64BIT" + "!TARGET_ZARCH" "@ mr\t%0,%2 m\t%0,%2 @@ -5260,7 +5327,7 @@ (match_operand:SI 1 "register_operand" "%0,0")) (zero_extend:DI (match_operand:SI 2 "nonimmediate_operand" "d,RT"))))] - "!TARGET_64BIT && TARGET_CPU_ZARCH" + "!TARGET_ZARCH && TARGET_CPU_ZARCH" "@ mlr\t%0,%2 ml\t%0,%2" @@ -5324,7 +5391,7 @@ (set (match_operand:DI 3 "general_operand" "") (mod:DI (match_dup 1) (match_dup 2)))]) (clobber (match_dup 4))] - "TARGET_64BIT" + "TARGET_ZARCH" { rtx insn, div_equal, mod_equal; @@ -5352,7 +5419,7 @@ (match_operand:DI 2 "general_operand" "d,RT"))) (const_int 64)) (zero_extend:TI (div:DI (match_dup 1) (match_dup 2)))))] - "TARGET_64BIT" + "TARGET_ZARCH" "@ dsgr\t%0,%2 dsg\t%0,%2" @@ -5370,7 +5437,7 @@ (const_int 64)) (zero_extend:TI (div:DI (match_dup 1) (sign_extend:DI (match_dup 2))))))] - "TARGET_64BIT" + "TARGET_ZARCH" "@ dsgfr\t%0,%2 dsgf\t%0,%2" @@ -5388,7 +5455,7 @@ (set (match_operand:DI 3 "general_operand" "") (umod:DI (match_dup 1) (match_dup 2)))]) (clobber (match_dup 4))] - "TARGET_64BIT" + "TARGET_ZARCH" { rtx insn, div_equal, mod_equal, equal; @@ -5430,7 +5497,7 @@ (zero_extend:TI (truncate:DI (udiv:TI (match_dup 1) (zero_extend:TI (match_dup 2)))))))] - "TARGET_64BIT" + "TARGET_ZARCH" "@ dlgr\t%0,%2 dlg\t%0,%2" @@ -5448,7 +5515,7 @@ (set (match_operand:SI 3 "general_operand" "") (mod:SI (match_dup 1) (match_dup 2)))]) (clobber (match_dup 4))] - "!TARGET_64BIT" + "!TARGET_ZARCH" { rtx insn, div_equal, mod_equal, equal; @@ -5488,7 +5555,7 @@ (zero_extend:DI (truncate:SI (div:DI (match_dup 1) (sign_extend:DI (match_dup 2)))))))] - "!TARGET_64BIT" + "!TARGET_ZARCH" "@ dr\t%0,%2 d\t%0,%2" @@ -5506,7 +5573,7 @@ (set (match_operand:SI 3 "general_operand" "") (umod:SI (match_dup 1) (match_dup 2)))]) (clobber (match_dup 4))] - "!TARGET_64BIT && TARGET_CPU_ZARCH" + "!TARGET_ZARCH && TARGET_CPU_ZARCH" { rtx insn, div_equal, mod_equal, equal; @@ -5548,7 +5615,7 @@ (zero_extend:DI (truncate:SI (udiv:DI (match_dup 1) (zero_extend:DI (match_dup 2)))))))] - "!TARGET_64BIT && TARGET_CPU_ZARCH" + "!TARGET_ZARCH && TARGET_CPU_ZARCH" "@ dlr\t%0,%2 dl\t%0,%2" @@ -5560,7 +5627,7 @@ (udiv:SI (match_operand:SI 1 "general_operand" "") (match_operand:SI 2 "general_operand" ""))) (clobber (match_dup 3))] - "!TARGET_64BIT && !TARGET_CPU_ZARCH" + "!TARGET_ZARCH && !TARGET_CPU_ZARCH" { rtx insn, udiv_equal, umod_equal, equal; @@ -5646,7 +5713,7 @@ (umod:SI (match_operand:SI 1 "nonimmediate_operand" "") (match_operand:SI 2 "nonimmediate_operand" ""))) (clobber (match_dup 3))] - "!TARGET_64BIT && !TARGET_CPU_ZARCH" + "!TARGET_ZARCH && !TARGET_CPU_ZARCH" { rtx insn, udiv_equal, umod_equal, equal; @@ -5767,7 +5834,7 @@ (const_int 0))) (set (match_operand:DI 0 "register_operand" "=d,d") (and:DI (match_dup 1) (match_dup 2)))] - "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT" + "s390_match_ccmode(insn, CCTmode) && TARGET_ZARCH" "@ ngr\t%0,%2 ng\t%0,%2" @@ -5780,7 +5847,7 @@ (match_operand:DI 2 "general_operand" "d,RT")) (const_int 0))) (clobber (match_scratch:DI 0 "=d,d"))] - "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT + "s390_match_ccmode(insn, CCTmode) && TARGET_ZARCH /* Do not steal TM patterns. */ && s390_single_part (operands[2], DImode, HImode, 0) < 0" "@ @@ -5796,7 +5863,7 @@ (match_operand:DI 2 "general_operand" "M,M,N0HDF,N1HDF,N2HDF,N3HDF,N0SDF,N1SDF,d,RT,NxQDF,Q"))) (clobber (reg:CC CC_REGNUM))] - "TARGET_64BIT && s390_logical_operator_ok_p (operands)" + "TARGET_ZARCH && s390_logical_operator_ok_p (operands)" "@ # # @@ -6086,7 +6153,7 @@ (const_int 0))) (set (match_operand:DI 0 "register_operand" "=d,d") (ior:DI (match_dup 1) (match_dup 2)))] - "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT" + "s390_match_ccmode(insn, CCTmode) && TARGET_ZARCH" "@ ogr\t%0,%2 og\t%0,%2" @@ -6099,7 +6166,7 @@ (match_operand:DI 2 "general_operand" "d,RT")) (const_int 0))) (clobber (match_scratch:DI 0 "=d,d"))] - "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT" + "s390_match_ccmode(insn, CCTmode) && TARGET_ZARCH" "@ ogr\t%0,%2 og\t%0,%2" @@ -6112,7 +6179,7 @@ (match_operand:DI 2 "general_operand" "N0HD0,N1HD0,N2HD0,N3HD0,N0SD0,N1SD0,d,RT,NxQD0,Q"))) (clobber (reg:CC CC_REGNUM))] - "TARGET_64BIT && s390_logical_operator_ok_p (operands)" + "TARGET_ZARCH && s390_logical_operator_ok_p (operands)" "@ oihh\t%0,%i2 oihl\t%0,%i2 @@ -6386,7 +6453,7 @@ (const_int 0))) (set (match_operand:DI 0 "register_operand" "=d,d") (xor:DI (match_dup 1) (match_dup 2)))] - "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT" + "s390_match_ccmode(insn, CCTmode) && TARGET_ZARCH" "@ xgr\t%0,%2 xg\t%0,%2" @@ -6399,7 +6466,7 @@ (match_operand:DI 2 "general_operand" "d,RT")) (const_int 0))) (clobber (match_scratch:DI 0 "=d,d"))] - "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT" + "s390_match_ccmode(insn, CCTmode) && TARGET_ZARCH" "@ xgr\t%0,%2 xg\t%0,%2" @@ -6411,7 +6478,7 @@ (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0,0,0,0,0") (match_operand:DI 2 "general_operand" "N0SD0,N1SD0,d,RT,NxQD0,Q"))) (clobber (reg:CC CC_REGNUM))] - "TARGET_64BIT && s390_logical_operator_ok_p (operands)" + "TARGET_ZARCH && s390_logical_operator_ok_p (operands)" "@ xihf\t%0,%k2 xilf\t%0,%k2 @@ -6658,7 +6725,7 @@ (const_int 0))) (set (match_operand:DI 0 "register_operand" "=d") (neg:DI (sign_extend:DI (match_dup 1))))] - "TARGET_64BIT && s390_match_ccmode (insn, CCAmode)" + "TARGET_ZARCH && s390_match_ccmode (insn, CCAmode)" "lcgfr\t%0,%1" [(set_attr "op_type" "RRE") (set_attr "z10prop" "z10_c")]) @@ -6667,7 +6734,7 @@ [(set (match_operand:DI 0 "register_operand" "=d") (neg:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "d")))) (clobber (reg:CC CC_REGNUM))] - "TARGET_64BIT" + "TARGET_ZARCH" "lcgfr\t%0,%1" [(set_attr "op_type" "RRE") (set_attr "z10prop" "z10_c")]) @@ -6709,7 +6776,7 @@ [(set (match_operand:DI 0 "register_operand" "=d") (neg:DI (match_operand:DI 1 "register_operand" "d"))) (clobber (reg:CC CC_REGNUM))] - "!TARGET_64BIT" + "!TARGET_ZARCH" "#" "&& reload_completed" [(parallel @@ -6804,7 +6871,7 @@ (const_int 0))) (set (match_operand:DI 0 "register_operand" "=d") (abs:DI (sign_extend:DI (match_dup 1))))] - "TARGET_64BIT && s390_match_ccmode (insn, CCAmode)" + "TARGET_ZARCH && s390_match_ccmode (insn, CCAmode)" "lpgfr\t%0,%1" [(set_attr "op_type" "RRE") (set_attr "z10prop" "z10_c")]) @@ -6813,7 +6880,7 @@ [(set (match_operand:DI 0 "register_operand" "=d") (abs:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "d")))) (clobber (reg:CC CC_REGNUM))] - "TARGET_64BIT" + "TARGET_ZARCH" "lpgfr\t%0,%1" [(set_attr "op_type" "RRE") (set_attr "z10prop" "z10_c")]) @@ -6922,7 +6989,7 @@ (const_int 0))) (set (match_operand:DI 0 "register_operand" "=d") (neg:DI (abs:DI (sign_extend:DI (match_dup 1)))))] - "TARGET_64BIT && s390_match_ccmode (insn, CCAmode)" + "TARGET_ZARCH && s390_match_ccmode (insn, CCAmode)" "lngfr\t%0,%1" [(set_attr "op_type" "RRE") (set_attr "z10prop" "z10_c")]) @@ -6932,7 +6999,7 @@ (neg:DI (abs:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "d"))))) (clobber (reg:CC CC_REGNUM))] - "TARGET_64BIT" + "TARGET_ZARCH" "lngfr\t%0,%1" [(set_attr "op_type" "RRE") (set_attr "z10prop" "z10_c")]) @@ -7061,7 +7128,7 @@ (define_expand "clzdi2" [(set (match_operand:DI 0 "register_operand" "=d") (clz:DI (match_operand:DI 1 "register_operand" "d")))] - "TARGET_EXTIMM && TARGET_64BIT" + "TARGET_EXTIMM && TARGET_ZARCH" { rtx insn, clz_equal; rtx wide_reg = gen_reg_rtx (TImode); @@ -7091,7 +7158,7 @@ (clobber (reg:CC CC_REGNUM))] "(unsigned HOST_WIDE_INT) INTVAL (operands[2]) == (unsigned HOST_WIDE_INT) 1 << 63 - && TARGET_EXTIMM && TARGET_64BIT" + && TARGET_EXTIMM && TARGET_ZARCH" "flogr\t%0,%1" [(set_attr "op_type" "RRE")]) @@ -7148,7 +7215,7 @@ [(set (match_operand:DI 0 "register_operand" "=d") (SHIFT:DI (match_operand:DI 1 "register_operand" "0") (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")))] - "!TARGET_64BIT" + "!TARGET_ZARCH" "s<lr>dl\t%0,%Y2" [(set_attr "op_type" "RS") (set_attr "atype" "reg")]) @@ -7170,7 +7237,7 @@ (SHIFT:DI (match_operand:DI 1 "register_operand" "0") (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y") (match_operand:SI 3 "const_int_operand" "n"))))] - "!TARGET_64BIT && (INTVAL (operands[3]) & 63) == 63" + "!TARGET_ZARCH && (INTVAL (operands[3]) & 63) == 63" "s<lr>dl\t%0,%Y2" [(set_attr "op_type" "RS") (set_attr "atype" "reg")]) @@ -7207,7 +7274,7 @@ (const_int 0))) (set (match_operand:DI 0 "register_operand" "=d") (ashiftrt:DI (match_dup 1) (match_dup 2)))] - "!TARGET_64BIT && s390_match_ccmode(insn, CCSmode)" + "!TARGET_ZARCH && s390_match_ccmode(insn, CCSmode)" "srda\t%0,%Y2" [(set_attr "op_type" "RS") (set_attr "atype" "reg")]) @@ -7218,7 +7285,7 @@ (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")) (const_int 0))) (clobber (match_scratch:DI 0 "=d"))] - "!TARGET_64BIT && s390_match_ccmode(insn, CCSmode)" + "!TARGET_ZARCH && s390_match_ccmode(insn, CCSmode)" "srda\t%0,%Y2" [(set_attr "op_type" "RS") (set_attr "atype" "reg")]) @@ -7228,7 +7295,7 @@ (ashiftrt:DI (match_operand:DI 1 "register_operand" "0") (match_operand:SI 2 "shift_count_or_setmem_operand" "Y"))) (clobber (reg:CC CC_REGNUM))] - "!TARGET_64BIT" + "!TARGET_ZARCH" "srda\t%0,%Y2" [(set_attr "op_type" "RS") (set_attr "atype" "reg")]) @@ -7283,7 +7350,7 @@ (const_int 0))) (set (match_operand:DI 0 "register_operand" "=d") (ashiftrt:DI (match_dup 1) (and:SI (match_dup 2) (match_dup 3))))] - "!TARGET_64BIT && s390_match_ccmode(insn, CCSmode) + "!TARGET_ZARCH && s390_match_ccmode(insn, CCSmode) && (INTVAL (operands[3]) & 63) == 63" "srda\t%0,%Y2" [(set_attr "op_type" "RS") @@ -7296,7 +7363,7 @@ (match_operand:SI 3 "const_int_operand" "n"))) (const_int 0))) (clobber (match_scratch:DI 0 "=d"))] - "!TARGET_64BIT && s390_match_ccmode(insn, CCSmode) + "!TARGET_ZARCH && s390_match_ccmode(insn, CCSmode) && (INTVAL (operands[3]) & 63) == 63" "srda\t%0,%Y2" [(set_attr "op_type" "RS") @@ -7308,7 +7375,7 @@ (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y") (match_operand:SI 3 "const_int_operand" "n")))) (clobber (reg:CC CC_REGNUM))] - "!TARGET_64BIT && (INTVAL (operands[3]) & 63) == 63" + "!TARGET_ZARCH && (INTVAL (operands[3]) & 63) == 63" "srda\t%0,%Y2" [(set_attr "op_type" "RS") (set_attr "atype" "reg")]) @@ -7662,7 +7729,7 @@ (subreg:DI (match_dup 2) 0))) (clobber (match_scratch:DI 4 "=X,&1,&?d")) (clobber (reg:CC CC_REGNUM))] - "TARGET_64BIT" + "TARGET_ZARCH" { if (which_alternative != 0) return "#"; @@ -7705,7 +7772,7 @@ (subreg:SI (match_dup 2) 4))) (clobber (match_scratch:SI 4 "=X,&1,&?d")) (clobber (reg:CC CC_REGNUM))] - "TARGET_64BIT" + "TARGET_ZARCH" { if (which_alternative != 0) return "#"; @@ -7748,7 +7815,7 @@ (subreg:SI (match_dup 2) 0))) (clobber (match_scratch:SI 4 "=X,&1,&?d")) (clobber (reg:CC CC_REGNUM))] - "!TARGET_64BIT && TARGET_CPU_ZARCH" + "!TARGET_ZARCH && TARGET_CPU_ZARCH" { if (which_alternative != 0) return "#"; @@ -7790,7 +7857,7 @@ emit_jump_insn (gen_doloop_si31 (operands[4], operands[0], operands[0])); else if (GET_MODE (operands[0]) == SImode && TARGET_CPU_ZARCH) emit_jump_insn (gen_doloop_si64 (operands[4], operands[0], operands[0])); - else if (GET_MODE (operands[0]) == DImode && TARGET_64BIT) + else if (GET_MODE (operands[0]) == DImode && TARGET_ZARCH) emit_jump_insn (gen_doloop_di (operands[4], operands[0], operands[0])); else FAIL; @@ -7921,7 +7988,7 @@ (plus:DI (match_dup 1) (const_int -1))) (clobber (match_scratch:DI 3 "=X,&1,&?d")) (clobber (reg:CC CC_REGNUM))] - "TARGET_64BIT" + "TARGET_ZARCH" { if (which_alternative != 0) return "#"; @@ -8479,13 +8546,13 @@ ; cds, cdsg (define_insn "*sync_compare_and_swap<mode>" - [(set (match_operand:DP 0 "register_operand" "=r") - (match_operand:DP 1 "memory_operand" "+Q")) + [(set (match_operand:DW 0 "register_operand" "=r") + (match_operand:DW 1 "memory_operand" "+Q")) (set (match_dup 1) - (unspec_volatile:DP + (unspec_volatile:DW [(match_dup 1) - (match_operand:DP 2 "register_operand" "0") - (match_operand:DP 3 "register_operand" "r")] + (match_operand:DW 2 "register_operand" "0") + (match_operand:DW 3 "register_operand" "r")] UNSPECV_CAS)) (set (reg:CCZ1 CC_REGNUM) (compare:CCZ1 (match_dup 1) (match_dup 2)))] @@ -8628,20 +8695,20 @@ (match_operand 1 "register_operand" "")] "" { - enum machine_mode mode = TARGET_64BIT ? OImode : TImode; rtx base = gen_rtx_REG (Pmode, BASE_REGNUM); /* Copy the backchain to the first word, sp to the second and the literal pool base to the third. */ + rtx save_bc = adjust_address (operands[0], Pmode, 0); + rtx save_sp = adjust_address (operands[0], Pmode, GET_MODE_SIZE (Pmode)); + rtx save_bp = adjust_address (operands[0], Pmode, 2 * GET_MODE_SIZE (Pmode)); + if (TARGET_BACKCHAIN) - { - rtx temp = force_reg (Pmode, s390_back_chain_rtx ()); - emit_move_insn (operand_subword (operands[0], 0, 0, mode), temp); - } - - emit_move_insn (operand_subword (operands[0], 1, 0, mode), operands[1]); - emit_move_insn (operand_subword (operands[0], 2, 0, mode), base); + emit_move_insn (save_bc, force_reg (Pmode, s390_back_chain_rtx ())); + + emit_move_insn (save_sp, operands[1]); + emit_move_insn (save_bp, base); DONE; }) @@ -8651,18 +8718,21 @@ (match_operand 1 "memory_operand" "")] "" { - enum machine_mode mode = TARGET_64BIT ? OImode : TImode; rtx base = gen_rtx_REG (Pmode, BASE_REGNUM); rtx temp = NULL_RTX; /* Restore the backchain from the first word, sp from the second and the literal pool base from the third. */ + rtx save_bc = adjust_address (operands[1], Pmode, 0); + rtx save_sp = adjust_address (operands[1], Pmode, GET_MODE_SIZE (Pmode)); + rtx save_bp = adjust_address (operands[1], Pmode, 2 * GET_MODE_SIZE (Pmode)); + if (TARGET_BACKCHAIN) - temp = force_reg (Pmode, operand_subword (operands[1], 0, 0, mode)); - - emit_move_insn (base, operand_subword (operands[1], 2, 0, mode)); - emit_move_insn (operands[0], operand_subword (operands[1], 1, 0, mode)); + temp = force_reg (Pmode, save_bc); + + emit_move_insn (base, save_bp); + emit_move_insn (operands[0], save_sp); if (temp) emit_move_insn (s390_back_chain_rtx (), temp);