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comparison gcc/config/arm/vec-common.md @ 67:f6334be47118

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update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
author nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
date Tue, 22 Mar 2011 17:18:12 +0900
parents 77e2b8dfacca
children 04ced10e8804
comparison
equal deleted inserted replaced
65:65488c3d617d 67:f6334be47118
1 ;; Machine Description for shared bits common to IWMMXT and Neon. 1 ;; Machine Description for shared bits common to IWMMXT and Neon.
2 ;; Copyright (C) 2006, 2007 Free Software Foundation, Inc. 2 ;; Copyright (C) 2006, 2007, 2010 Free Software Foundation, Inc.
3 ;; Written by CodeSourcery. 3 ;; Written by CodeSourcery.
4 ;; 4 ;;
5 ;; This file is part of GCC. 5 ;; This file is part of GCC.
6 ;; 6 ;;
7 ;; GCC is free software; you can redistribute it and/or modify it 7 ;; GCC is free software; you can redistribute it and/or modify it
17 ;; You should have received a copy of the GNU General Public License 17 ;; You should have received a copy of the GNU General Public License
18 ;; along with GCC; see the file COPYING3. If not see 18 ;; along with GCC; see the file COPYING3. If not see
19 ;; <http://www.gnu.org/licenses/>. 19 ;; <http://www.gnu.org/licenses/>.
20 20
21 ;; Vector Moves 21 ;; Vector Moves
22
23 ;; All integer and float modes supported by Neon and IWMMXT.
24 (define_mode_iterator VALL [V2DI V2SI V4HI V8QI V2SF V4SI V8HI V16QI V4SF])
25
26 ;; All integer and float modes supported by Neon and IWMMXT, except V2DI.
27 (define_mode_iterator VALLW [V2SI V4HI V8QI V2SF V4SI V8HI V16QI V4SF])
28
29 ;; All integer modes supported by Neon and IWMMXT
30 (define_mode_iterator VINT [V2DI V2SI V4HI V8QI V4SI V8HI V16QI])
31
32 ;; All integer modes supported by Neon and IWMMXT, except V2DI
33 (define_mode_iterator VINTW [V2SI V4HI V8QI V4SI V8HI V16QI])
34 22
35 (define_expand "mov<mode>" 23 (define_expand "mov<mode>"
36 [(set (match_operand:VALL 0 "nonimmediate_operand" "") 24 [(set (match_operand:VALL 0 "nonimmediate_operand" "")
37 (match_operand:VALL 1 "general_operand" ""))] 25 (match_operand:VALL 1 "general_operand" ""))]
38 "TARGET_NEON 26 "TARGET_NEON
55 43
56 (define_expand "add<mode>3" 44 (define_expand "add<mode>3"
57 [(set (match_operand:VALL 0 "s_register_operand" "") 45 [(set (match_operand:VALL 0 "s_register_operand" "")
58 (plus:VALL (match_operand:VALL 1 "s_register_operand" "") 46 (plus:VALL (match_operand:VALL 1 "s_register_operand" "")
59 (match_operand:VALL 2 "s_register_operand" "")))] 47 (match_operand:VALL 2 "s_register_operand" "")))]
60 "TARGET_NEON 48 "(TARGET_NEON && ((<MODE>mode != V2SFmode && <MODE>mode != V4SFmode)
49 || flag_unsafe_math_optimizations))
61 || (TARGET_REALLY_IWMMXT && VALID_IWMMXT_REG_MODE (<MODE>mode))" 50 || (TARGET_REALLY_IWMMXT && VALID_IWMMXT_REG_MODE (<MODE>mode))"
62 { 51 {
63 }) 52 })
64 53
65 (define_expand "sub<mode>3" 54 (define_expand "sub<mode>3"
66 [(set (match_operand:VALL 0 "s_register_operand" "") 55 [(set (match_operand:VALL 0 "s_register_operand" "")
67 (minus:VALL (match_operand:VALL 1 "s_register_operand" "") 56 (minus:VALL (match_operand:VALL 1 "s_register_operand" "")
68 (match_operand:VALL 2 "s_register_operand" "")))] 57 (match_operand:VALL 2 "s_register_operand" "")))]
69 "TARGET_NEON 58 "(TARGET_NEON && ((<MODE>mode != V2SFmode && <MODE>mode != V4SFmode)
59 || flag_unsafe_math_optimizations))
70 || (TARGET_REALLY_IWMMXT && VALID_IWMMXT_REG_MODE (<MODE>mode))" 60 || (TARGET_REALLY_IWMMXT && VALID_IWMMXT_REG_MODE (<MODE>mode))"
71 { 61 {
72 }) 62 })
73 63
74 (define_expand "mul<mode>3" 64 (define_expand "mul<mode>3"
75 [(set (match_operand:VALLW 0 "s_register_operand" "") 65 [(set (match_operand:VALLW 0 "s_register_operand" "")
76 (mult:VALLW (match_operand:VALLW 1 "s_register_operand" "") 66 (mult:VALLW (match_operand:VALLW 1 "s_register_operand" "")
77 (match_operand:VALLW 2 "s_register_operand" "")))] 67 (match_operand:VALLW 2 "s_register_operand" "")))]
78 "TARGET_NEON || (<MODE>mode == V4HImode && TARGET_REALLY_IWMMXT)" 68 "(TARGET_NEON && ((<MODE>mode != V2SFmode && <MODE>mode != V4SFmode)
69 || flag_unsafe_math_optimizations))
70 || (<MODE>mode == V4HImode && TARGET_REALLY_IWMMXT)"
79 { 71 {
80 }) 72 })
81 73
82 (define_expand "smin<mode>3" 74 (define_expand "smin<mode>3"
83 [(set (match_operand:VALLW 0 "s_register_operand" "") 75 [(set (match_operand:VALLW 0 "s_register_operand" "")
84 (smin:VALLW (match_operand:VALLW 1 "s_register_operand" "") 76 (smin:VALLW (match_operand:VALLW 1 "s_register_operand" "")
85 (match_operand:VALLW 2 "s_register_operand" "")))] 77 (match_operand:VALLW 2 "s_register_operand" "")))]
86 "TARGET_NEON 78 "(TARGET_NEON && ((<MODE>mode != V2SFmode && <MODE>mode != V4SFmode)
79 || flag_unsafe_math_optimizations))
87 || (TARGET_REALLY_IWMMXT && VALID_IWMMXT_REG_MODE (<MODE>mode))" 80 || (TARGET_REALLY_IWMMXT && VALID_IWMMXT_REG_MODE (<MODE>mode))"
88 { 81 {
89 }) 82 })
90 83
91 (define_expand "umin<mode>3" 84 (define_expand "umin<mode>3"
99 92
100 (define_expand "smax<mode>3" 93 (define_expand "smax<mode>3"
101 [(set (match_operand:VALLW 0 "s_register_operand" "") 94 [(set (match_operand:VALLW 0 "s_register_operand" "")
102 (smax:VALLW (match_operand:VALLW 1 "s_register_operand" "") 95 (smax:VALLW (match_operand:VALLW 1 "s_register_operand" "")
103 (match_operand:VALLW 2 "s_register_operand" "")))] 96 (match_operand:VALLW 2 "s_register_operand" "")))]
104 "TARGET_NEON 97 "(TARGET_NEON && ((<MODE>mode != V2SFmode && <MODE>mode != V4SFmode)
98 || flag_unsafe_math_optimizations))
105 || (TARGET_REALLY_IWMMXT && VALID_IWMMXT_REG_MODE (<MODE>mode))" 99 || (TARGET_REALLY_IWMMXT && VALID_IWMMXT_REG_MODE (<MODE>mode))"
106 { 100 {
107 }) 101 })
108 102
109 (define_expand "umax<mode>3" 103 (define_expand "umax<mode>3"