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comparison gcc/config/frv/frv.md @ 67:f6334be47118

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update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
author nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
date Tue, 22 Mar 2011 17:18:12 +0900
parents 77e2b8dfacca
children 04ced10e8804
comparison
equal deleted inserted replaced
65:65488c3d617d 67:f6334be47118
1 ;; Frv Machine Description 1 ;; Frv Machine Description
2 ;; Copyright (C) 1999, 2000, 2001, 2003, 2004, 2005, 2007, 2008 2 ;; Copyright (C) 1999, 2000, 2001, 2003, 2004, 2005, 2007, 2008, 2010
3 ;; Free Software Foundation, Inc. 3 ;; Free Software Foundation, Inc.
4 ;; Contributed by Red Hat, Inc. 4 ;; Contributed by Red Hat, Inc.
5 5
6 ;; This file is part of GCC. 6 ;; This file is part of GCC.
7 7
343 343
344 ;; Processor type -- this attribute must exactly match the processor_type 344 ;; Processor type -- this attribute must exactly match the processor_type
345 ;; enumeration in frv-protos.h. 345 ;; enumeration in frv-protos.h.
346 346
347 (define_attr "cpu" "generic,fr550,fr500,fr450,fr405,fr400,fr300,simple,tomcat" 347 (define_attr "cpu" "generic,fr550,fr500,fr450,fr405,fr400,fr300,simple,tomcat"
348 (const (symbol_ref "frv_cpu_type"))) 348 (const (symbol_ref "(enum attr_cpu) frv_cpu_type")))
349 349
350 ;; Attribute is "yes" for branches and jumps that span too great a distance 350 ;; Attribute is "yes" for branches and jumps that span too great a distance
351 ;; to be implemented in the most natural way. Such instructions will use 351 ;; to be implemented in the most natural way. Such instructions will use
352 ;; a call instruction in some way. 352 ;; a call instruction in some way.
353 353
358 (define_attr "type" 358 (define_attr "type"
359 "int,sethi,setlo,mul,div,gload,gstore,fload,fstore,movfg,movgf,macc,scan,cut,branch,jump,jumpl,call,spr,trap,fnop,fsconv,fsadd,fscmp,fsmul,fsmadd,fsdiv,sqrt_single,fdconv,fdadd,fdcmp,fdmul,fdmadd,fddiv,sqrt_double,mnop,mlogic,maveh,msath,maddh,mqaddh,mpackh,munpackh,mdpackh,mbhconv,mrot,mshift,mexpdhw,mexpdhd,mwcut,mmulh,mmulxh,mmach,mmrdh,mqmulh,mqmulxh,mqmach,mcpx,mqcpx,mcut,mclracc,mclracca,mdunpackh,mbhconve,mrdacc,mwtacc,maddacc,mdaddacc,mabsh,mdrot,mcpl,mdcut,mqsath,mqlimh,mqshift,mset,ccr,multi,load_or_call,unknown" 359 "int,sethi,setlo,mul,div,gload,gstore,fload,fstore,movfg,movgf,macc,scan,cut,branch,jump,jumpl,call,spr,trap,fnop,fsconv,fsadd,fscmp,fsmul,fsmadd,fsdiv,sqrt_single,fdconv,fdadd,fdcmp,fdmul,fdmadd,fddiv,sqrt_double,mnop,mlogic,maveh,msath,maddh,mqaddh,mpackh,munpackh,mdpackh,mbhconv,mrot,mshift,mexpdhw,mexpdhd,mwcut,mmulh,mmulxh,mmach,mmrdh,mqmulh,mqmulxh,mqmach,mcpx,mqcpx,mcut,mclracc,mclracca,mdunpackh,mbhconve,mrdacc,mwtacc,maddacc,mdaddacc,mabsh,mdrot,mcpl,mdcut,mqsath,mqlimh,mqshift,mset,ccr,multi,load_or_call,unknown"
360 (const_string "unknown")) 360 (const_string "unknown"))
361 361
362 (define_attr "acc_group" "none,even,odd" 362 (define_attr "acc_group" "none,even,odd"
363 (symbol_ref "frv_acc_group (insn)")) 363 (symbol_ref "(enum attr_acc_group) frv_acc_group (insn)"))
364 364
365 ;; Scheduling and Packing Overview 365 ;; Scheduling and Packing Overview
366 ;; ------------------------------- 366 ;; -------------------------------
367 ;; 367 ;;
368 ;; FR-V instructions are divided into five groups: integer, floating-point, 368 ;; FR-V instructions are divided into five groups: integer, floating-point,
1517 ;; }" 1517 ;; }"
1518 ;; ) 1518 ;; )
1519 ;; 1519 ;;
1520 1520
1521 (include "predicates.md") 1521 (include "predicates.md")
1522 (include "constraints.md")
1522 1523
1523 ;; :::::::::::::::::::: 1524 ;; ::::::::::::::::::::
1524 ;; :: 1525 ;; ::
1525 ;; :: Moves 1526 ;; :: Moves
1526 ;; :: 1527 ;; ::
1893 operands[4] = GEN_INT ((INTVAL (op1) < 0) ? -1 : 0); 1894 operands[4] = GEN_INT ((INTVAL (op1) < 0) ? -1 : 0);
1894 operands[5] = op1; 1895 operands[5] = op1;
1895 } 1896 }
1896 else 1897 else
1897 { 1898 {
1898 operands[4] = GEN_INT ((((unsigned HOST_WIDE_INT)INTVAL (op1) >> 16) 1899 operands[4] = gen_int_mode ((INTVAL (op1) >> 16) >> 16, SImode);
1899 >> 16) ^ ((unsigned HOST_WIDE_INT)1 << 31) 1900 operands[5] = gen_int_mode (INTVAL (op1), SImode);
1900 - ((unsigned HOST_WIDE_INT)1 << 31));
1901 operands[5] = GEN_INT (trunc_int_for_mode (INTVAL (op1), SImode));
1902 } 1901 }
1903 }") 1902 }")
1904 1903
1905 (define_split 1904 (define_split
1906 [(set (match_operand:DI 0 "register_operand" "") 1905 [(set (match_operand:DI 0 "register_operand" "")
3274 "fmuls %1,%2,%0" 3273 "fmuls %1,%2,%0"
3275 [(set_attr "length" "4") 3274 [(set_attr "length" "4")
3276 (set_attr "type" "fsmul")]) 3275 (set_attr "type" "fsmul")])
3277 3276
3278 ;; Multiplication with addition/subtraction 3277 ;; Multiplication with addition/subtraction
3279 (define_insn "*muladdsf4" 3278 (define_insn "fmasf4"
3280 [(set (match_operand:SF 0 "fpr_operand" "=f") 3279 [(set (match_operand:SF 0 "fpr_operand" "=f")
3281 (plus:SF (mult:SF (match_operand:SF 1 "fpr_operand" "%f") 3280 (fma:SF (match_operand:SF 1 "fpr_operand" "f")
3282 (match_operand:SF 2 "fpr_operand" "f")) 3281 (match_operand:SF 2 "fpr_operand" "f")
3283 (match_operand:SF 3 "fpr_operand" "0")))] 3282 (match_operand:SF 3 "fpr_operand" "0")))]
3284 "TARGET_HARD_FLOAT && TARGET_MULADD" 3283 "TARGET_HARD_FLOAT && TARGET_MULADD"
3285 "fmadds %1,%2,%0" 3284 "fmadds %1,%2,%0"
3286 [(set_attr "length" "4") 3285 [(set_attr "length" "4")
3287 (set_attr "type" "fsmadd")]) 3286 (set_attr "type" "fsmadd")])
3288 3287
3289 (define_insn "*mulsubsf4" 3288 (define_insn "fmssf4"
3290 [(set (match_operand:SF 0 "fpr_operand" "=f") 3289 [(set (match_operand:SF 0 "fpr_operand" "=f")
3291 (minus:SF (mult:SF (match_operand:SF 1 "fpr_operand" "%f") 3290 (fma:SF (match_operand:SF 1 "fpr_operand" "f")
3292 (match_operand:SF 2 "fpr_operand" "f")) 3291 (match_operand:SF 2 "fpr_operand" "f")
3293 (match_operand:SF 3 "fpr_operand" "0")))] 3292 (neg:SF (match_operand:SF 3 "fpr_operand" "0"))))]
3294 "TARGET_HARD_FLOAT && TARGET_MULADD" 3293 "TARGET_HARD_FLOAT && TARGET_MULADD"
3295 "fmsubs %1,%2,%0" 3294 "fmsubs %1,%2,%0"
3296 [(set_attr "length" "4") 3295 [(set_attr "length" "4")
3297 (set_attr "type" "fsmadd")]) 3296 (set_attr "type" "fsmadd")])
3298 3297
4628 (match_operand:QI 3 "const_int_operand" "O,O,L,n,n") 4627 (match_operand:QI 3 "const_int_operand" "O,O,L,n,n")
4629 (match_operand:QI 4 "const_int_operand" "L,n,O,O,n"))) 4628 (match_operand:QI 4 "const_int_operand" "L,n,O,O,n")))
4630 (clobber (match_operand:CC_CCR 5 "icr_operand" "=v,v,v,v,v"))] 4629 (clobber (match_operand:CC_CCR 5 "icr_operand" "=v,v,v,v,v"))]
4631 "(INTVAL (operands[3]) == 0 4630 "(INTVAL (operands[3]) == 0
4632 || INTVAL (operands[4]) == 0 4631 || INTVAL (operands[4]) == 0
4633 || (IN_RANGE_P (INTVAL (operands[3]), -2048, 2047) 4632 || (IN_RANGE (INTVAL (operands[3]), -2048, 2047)
4634 && IN_RANGE_P (INTVAL (operands[4]) - INTVAL (operands[3]), -2048, 2047)))" 4633 && IN_RANGE (INTVAL (operands[4]) - INTVAL (operands[3]), -2048, 2047)))"
4635 "#" 4634 "#"
4636 [(set_attr "length" "8,12,8,12,12") 4635 [(set_attr "length" "8,12,8,12,12")
4637 (set_attr "type" "multi")]) 4636 (set_attr "type" "multi")])
4638 4637
4639 (define_insn "*movqicc_internal2_float" 4638 (define_insn "*movqicc_internal2_float"
4645 (match_operand:QI 4 "const_int_operand" "L,n,O,O,n"))) 4644 (match_operand:QI 4 "const_int_operand" "L,n,O,O,n")))
4646 (clobber (match_operand:CC_CCR 5 "fcr_operand" "=w,w,w,w,w"))] 4645 (clobber (match_operand:CC_CCR 5 "fcr_operand" "=w,w,w,w,w"))]
4647 "TARGET_HARD_FLOAT 4646 "TARGET_HARD_FLOAT
4648 && (INTVAL (operands[3]) == 0 4647 && (INTVAL (operands[3]) == 0
4649 || INTVAL (operands[4]) == 0 4648 || INTVAL (operands[4]) == 0
4650 || (IN_RANGE_P (INTVAL (operands[3]), -2048, 2047) 4649 || (IN_RANGE (INTVAL (operands[3]), -2048, 2047)
4651 && IN_RANGE_P (INTVAL (operands[4]) - INTVAL (operands[3]), -2048, 2047)))" 4650 && IN_RANGE (INTVAL (operands[4]) - INTVAL (operands[3]), -2048, 2047)))"
4652 "#" 4651 "#"
4653 [(set_attr "length" "8,12,8,12,12") 4652 [(set_attr "length" "8,12,8,12,12")
4654 (set_attr "type" "multi")]) 4653 (set_attr "type" "multi")])
4655 4654
4656 (define_split 4655 (define_split
4713 (match_operand:HI 3 "const_int_operand" "O,O,L,n,n") 4712 (match_operand:HI 3 "const_int_operand" "O,O,L,n,n")
4714 (match_operand:HI 4 "const_int_operand" "L,n,O,O,n"))) 4713 (match_operand:HI 4 "const_int_operand" "L,n,O,O,n")))
4715 (clobber (match_operand:CC_CCR 5 "icr_operand" "=v,v,v,v,v"))] 4714 (clobber (match_operand:CC_CCR 5 "icr_operand" "=v,v,v,v,v"))]
4716 "(INTVAL (operands[3]) == 0 4715 "(INTVAL (operands[3]) == 0
4717 || INTVAL (operands[4]) == 0 4716 || INTVAL (operands[4]) == 0
4718 || (IN_RANGE_P (INTVAL (operands[3]), -2048, 2047) 4717 || (IN_RANGE (INTVAL (operands[3]), -2048, 2047)
4719 && IN_RANGE_P (INTVAL (operands[4]) - INTVAL (operands[3]), -2048, 2047)))" 4718 && IN_RANGE (INTVAL (operands[4]) - INTVAL (operands[3]), -2048, 2047)))"
4720 "#" 4719 "#"
4721 [(set_attr "length" "8,12,8,12,12") 4720 [(set_attr "length" "8,12,8,12,12")
4722 (set_attr "type" "multi")]) 4721 (set_attr "type" "multi")])
4723 4722
4724 (define_insn "*movhicc_internal2_float" 4723 (define_insn "*movhicc_internal2_float"
4730 (match_operand:HI 4 "const_int_operand" "L,n,O,O,n"))) 4729 (match_operand:HI 4 "const_int_operand" "L,n,O,O,n")))
4731 (clobber (match_operand:CC_CCR 5 "fcr_operand" "=w,w,w,w,w"))] 4730 (clobber (match_operand:CC_CCR 5 "fcr_operand" "=w,w,w,w,w"))]
4732 "TARGET_HARD_FLOAT 4731 "TARGET_HARD_FLOAT
4733 && (INTVAL (operands[3]) == 0 4732 && (INTVAL (operands[3]) == 0
4734 || INTVAL (operands[4]) == 0 4733 || INTVAL (operands[4]) == 0
4735 || (IN_RANGE_P (INTVAL (operands[3]), -2048, 2047) 4734 || (IN_RANGE (INTVAL (operands[3]), -2048, 2047)
4736 && IN_RANGE_P (INTVAL (operands[4]) - INTVAL (operands[3]), -2048, 2047)))" 4735 && IN_RANGE (INTVAL (operands[4]) - INTVAL (operands[3]), -2048, 2047)))"
4737 "#" 4736 "#"
4738 [(set_attr "length" "8,12,8,12,12") 4737 [(set_attr "length" "8,12,8,12,12")
4739 (set_attr "type" "multi")]) 4738 (set_attr "type" "multi")])
4740 4739
4741 (define_split 4740 (define_split
4798 (match_operand:SI 3 "const_int_operand" "O,O,L,n,n") 4797 (match_operand:SI 3 "const_int_operand" "O,O,L,n,n")
4799 (match_operand:SI 4 "const_int_operand" "L,n,O,O,n"))) 4798 (match_operand:SI 4 "const_int_operand" "L,n,O,O,n")))
4800 (clobber (match_operand:CC_CCR 5 "icr_operand" "=v,v,v,v,v"))] 4799 (clobber (match_operand:CC_CCR 5 "icr_operand" "=v,v,v,v,v"))]
4801 "(INTVAL (operands[3]) == 0 4800 "(INTVAL (operands[3]) == 0
4802 || INTVAL (operands[4]) == 0 4801 || INTVAL (operands[4]) == 0
4803 || (IN_RANGE_P (INTVAL (operands[3]), -2048, 2047) 4802 || (IN_RANGE (INTVAL (operands[3]), -2048, 2047)
4804 && IN_RANGE_P (INTVAL (operands[4]) - INTVAL (operands[3]), -2048, 2047)))" 4803 && IN_RANGE (INTVAL (operands[4]) - INTVAL (operands[3]), -2048, 2047)))"
4805 "#" 4804 "#"
4806 [(set_attr "length" "8,12,8,12,12") 4805 [(set_attr "length" "8,12,8,12,12")
4807 (set_attr "type" "multi")]) 4806 (set_attr "type" "multi")])
4808 4807
4809 (define_insn "*movsicc_internal2_float" 4808 (define_insn "*movsicc_internal2_float"
4815 (match_operand:SI 4 "const_int_operand" "L,n,O,O,n"))) 4814 (match_operand:SI 4 "const_int_operand" "L,n,O,O,n")))
4816 (clobber (match_operand:CC_CCR 5 "fcr_operand" "=w,w,w,w,w"))] 4815 (clobber (match_operand:CC_CCR 5 "fcr_operand" "=w,w,w,w,w"))]
4817 "TARGET_HARD_FLOAT 4816 "TARGET_HARD_FLOAT
4818 && (INTVAL (operands[3]) == 0 4817 && (INTVAL (operands[3]) == 0
4819 || INTVAL (operands[4]) == 0 4818 || INTVAL (operands[4]) == 0
4820 || (IN_RANGE_P (INTVAL (operands[3]), -2048, 2047) 4819 || (IN_RANGE (INTVAL (operands[3]), -2048, 2047)
4821 && IN_RANGE_P (INTVAL (operands[4]) - INTVAL (operands[3]), -2048, 2047)))" 4820 && IN_RANGE (INTVAL (operands[4]) - INTVAL (operands[3]), -2048, 2047)))"
4822 "#" 4821 "#"
4823 [(set_attr "length" "8,12,8,12,12") 4822 [(set_attr "length" "8,12,8,12,12")
4824 (set_attr "type" "multi")]) 4823 (set_attr "type" "multi")])
4825 4824
4826 (define_split 4825 (define_split
5564 gcc_assert (GET_CODE (operands[1]) == CONST_INT); 5563 gcc_assert (GET_CODE (operands[1]) == CONST_INT);
5565 5564
5566 gcc_assert (GET_CODE (operands[2]) == CONST_INT); 5565 gcc_assert (GET_CODE (operands[2]) == CONST_INT);
5567 5566
5568 /* If we can't generate an immediate instruction, promote to register. */ 5567 /* If we can't generate an immediate instruction, promote to register. */
5569 if (! IN_RANGE_P (INTVAL (range), -2048, 2047)) 5568 if (! IN_RANGE (INTVAL (range), -2048, 2047))
5570 range = force_reg (SImode, range); 5569 range = force_reg (SImode, range);
5571 5570
5572 /* If low bound is 0, we don't have to subtract it. */ 5571 /* If low bound is 0, we don't have to subtract it. */
5573 if (INTVAL (operands[1]) == 0) 5572 if (INTVAL (operands[1]) == 0)
5574 indx = operands[0]; 5573 indx = operands[0];
5575 else 5574 else
5576 { 5575 {
5577 indx = gen_reg_rtx (SImode); 5576 indx = gen_reg_rtx (SImode);
5578 if (IN_RANGE_P (INTVAL (low), -2047, 2048)) 5577 if (IN_RANGE (INTVAL (low), -2047, 2048))
5579 emit_insn (gen_addsi3 (indx, operands[0], GEN_INT (- INTVAL (low)))); 5578 emit_insn (gen_addsi3 (indx, operands[0], GEN_INT (- INTVAL (low))));
5580 else 5579 else
5581 emit_insn (gen_subsi3 (indx, operands[0], force_reg (SImode, low))); 5580 emit_insn (gen_subsi3 (indx, operands[0], force_reg (SImode, low)));
5582 } 5581 }
5583 5582