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comparison gcc/config/mips/mips-dspr2.md @ 67:f6334be47118

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update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
author nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
date Tue, 22 Mar 2011 17:18:12 +0900
parents 77e2b8dfacca
children 04ced10e8804
comparison
equal deleted inserted replaced
65:65488c3d617d 67:f6334be47118
1 ;; Copyright (C) 2007 Free Software Foundation, Inc. 1 ;; Copyright (C) 2007, 2010 Free Software Foundation, Inc.
2 ;; 2 ;;
3 ;; This file is part of GCC. 3 ;; This file is part of GCC.
4 ;; 4 ;;
5 ;; GCC is free software; you can redistribute it and/or modify 5 ;; GCC is free software; you can redistribute it and/or modify
6 ;; it under the terms of the GNU General Public License as published by 6 ;; it under the terms of the GNU General Public License as published by
16 ;; along with GCC; see the file COPYING3. If not see 16 ;; along with GCC; see the file COPYING3. If not see
17 ;; <http://www.gnu.org/licenses/>. 17 ;; <http://www.gnu.org/licenses/>.
18 ;; 18 ;;
19 ; MIPS DSP ASE REV 2 Revision 0.02 11/24/2006 19 ; MIPS DSP ASE REV 2 Revision 0.02 11/24/2006
20 20
21 (define_c_enum "unspec" [
22 UNSPEC_ABSQ_S_QB
23 UNSPEC_ADDU_PH
24 UNSPEC_ADDU_S_PH
25 UNSPEC_ADDUH_QB
26 UNSPEC_ADDUH_R_QB
27 UNSPEC_APPEND
28 UNSPEC_BALIGN
29 UNSPEC_CMPGDU_EQ_QB
30 UNSPEC_CMPGDU_LT_QB
31 UNSPEC_CMPGDU_LE_QB
32 UNSPEC_DPA_W_PH
33 UNSPEC_DPS_W_PH
34 UNSPEC_MADD
35 UNSPEC_MADDU
36 UNSPEC_MSUB
37 UNSPEC_MSUBU
38 UNSPEC_MUL_PH
39 UNSPEC_MUL_S_PH
40 UNSPEC_MULQ_RS_W
41 UNSPEC_MULQ_S_PH
42 UNSPEC_MULQ_S_W
43 UNSPEC_MULSA_W_PH
44 UNSPEC_MULT
45 UNSPEC_MULTU
46 UNSPEC_PRECR_QB_PH
47 UNSPEC_PRECR_SRA_PH_W
48 UNSPEC_PRECR_SRA_R_PH_W
49 UNSPEC_PREPEND
50 UNSPEC_SHRA_QB
51 UNSPEC_SHRA_R_QB
52 UNSPEC_SHRL_PH
53 UNSPEC_SUBU_PH
54 UNSPEC_SUBU_S_PH
55 UNSPEC_SUBUH_QB
56 UNSPEC_SUBUH_R_QB
57 UNSPEC_ADDQH_PH
58 UNSPEC_ADDQH_R_PH
59 UNSPEC_ADDQH_W
60 UNSPEC_ADDQH_R_W
61 UNSPEC_SUBQH_PH
62 UNSPEC_SUBQH_R_PH
63 UNSPEC_SUBQH_W
64 UNSPEC_SUBQH_R_W
65 UNSPEC_DPAX_W_PH
66 UNSPEC_DPSX_W_PH
67 UNSPEC_DPAQX_S_W_PH
68 UNSPEC_DPAQX_SA_W_PH
69 UNSPEC_DPSQX_S_W_PH
70 UNSPEC_DPSQX_SA_W_PH
71 ])
72
21 (define_insn "mips_absq_s_qb" 73 (define_insn "mips_absq_s_qb"
22 [(parallel 74 [(parallel
23 [(set (match_operand:V4QI 0 "register_operand" "=d") 75 [(set (match_operand:V4QI 0 "register_operand" "=d")
24 (unspec:V4QI [(match_operand:V4QI 1 "reg_or_0_operand" "dYG")] 76 (unspec:V4QI [(match_operand:V4QI 1 "reg_or_0_operand" "dYG")]
25 UNSPEC_ABSQ_S_QB)) 77 UNSPEC_ABSQ_S_QB))
170 "ISA_HAS_DSPR2 && !TARGET_64BIT" 222 "ISA_HAS_DSPR2 && !TARGET_64BIT"
171 "dps.w.ph\t%q0,%z2,%z3" 223 "dps.w.ph\t%q0,%z2,%z3"
172 [(set_attr "type" "imadd") 224 [(set_attr "type" "imadd")
173 (set_attr "mode" "SI")]) 225 (set_attr "mode" "SI")])
174 226
175 (define_expand "mips_madd<u>"
176 [(set (match_operand:DI 0 "register_operand")
177 (plus:DI
178 (mult:DI (any_extend:DI (match_operand:SI 2 "register_operand"))
179 (any_extend:DI (match_operand:SI 3 "register_operand")))
180 (match_operand:DI 1 "register_operand")))]
181 "ISA_HAS_DSPR2 && !TARGET_64BIT")
182
183 (define_expand "mips_msub<u>"
184 [(set (match_operand:DI 0 "register_operand")
185 (minus:DI
186 (match_operand:DI 1 "register_operand")
187 (mult:DI (any_extend:DI (match_operand:SI 2 "register_operand"))
188 (any_extend:DI (match_operand:SI 3 "register_operand")))))]
189 "ISA_HAS_DSPR2 && !TARGET_64BIT")
190
191 (define_insn "mulv2hi3" 227 (define_insn "mulv2hi3"
192 [(parallel 228 [(parallel
193 [(set (match_operand:V2HI 0 "register_operand" "=d") 229 [(set (match_operand:V2HI 0 "register_operand" "=d")
194 (mult:V2HI (match_operand:V2HI 1 "register_operand" "d") 230 (mult:V2HI (match_operand:V2HI 1 "register_operand" "d")
195 (match_operand:V2HI 2 "register_operand" "d"))) 231 (match_operand:V2HI 2 "register_operand" "d")))
264 (match_operand:V2HI 3 "reg_or_0_operand" "dYG")] 300 (match_operand:V2HI 3 "reg_or_0_operand" "dYG")]
265 UNSPEC_MULSA_W_PH))] 301 UNSPEC_MULSA_W_PH))]
266 "ISA_HAS_DSPR2 && !TARGET_64BIT" 302 "ISA_HAS_DSPR2 && !TARGET_64BIT"
267 "mulsa.w.ph\t%q0,%z2,%z3" 303 "mulsa.w.ph\t%q0,%z2,%z3"
268 [(set_attr "type" "imadd") 304 [(set_attr "type" "imadd")
269 (set_attr "mode" "SI")])
270
271 (define_insn "mips_mult"
272 [(set (match_operand:DI 0 "register_operand" "=a")
273 (mult:DI
274 (sign_extend:DI (match_operand:SI 1 "register_operand" "d"))
275 (sign_extend:DI (match_operand:SI 2 "register_operand" "d"))))]
276 "ISA_HAS_DSPR2 && !TARGET_64BIT"
277 "mult\t%q0,%1,%2"
278 [(set_attr "type" "imul")
279 (set_attr "mode" "SI")])
280
281 (define_insn "mips_multu"
282 [(set (match_operand:DI 0 "register_operand" "=a")
283 (mult:DI
284 (zero_extend:DI (match_operand:SI 1 "register_operand" "d"))
285 (zero_extend:DI (match_operand:SI 2 "register_operand" "d"))))]
286 "ISA_HAS_DSPR2 && !TARGET_64BIT"
287 "multu\t%q0,%1,%2"
288 [(set_attr "type" "imul")
289 (set_attr "mode" "SI")]) 305 (set_attr "mode" "SI")])
290 306
291 (define_insn "mips_precr_qb_ph" 307 (define_insn "mips_precr_qb_ph"
292 [(set (match_operand:V4QI 0 "register_operand" "=d") 308 [(set (match_operand:V4QI 0 "register_operand" "=d")
293 (unspec:V4QI [(match_operand:V2HI 1 "reg_or_0_operand" "dYG") 309 (unspec:V4QI [(match_operand:V2HI 1 "reg_or_0_operand" "dYG")