Mercurial > hg > CbC > CbC_gcc
diff gcc/config/mips/mips-dspr2.md @ 67:f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
| author | nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp> |
|---|---|
| date | Tue, 22 Mar 2011 17:18:12 +0900 |
| parents | 77e2b8dfacca |
| children | 04ced10e8804 |
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--- a/gcc/config/mips/mips-dspr2.md Tue May 25 18:58:51 2010 +0900 +++ b/gcc/config/mips/mips-dspr2.md Tue Mar 22 17:18:12 2011 +0900 @@ -1,4 +1,4 @@ -;; Copyright (C) 2007 Free Software Foundation, Inc. +;; Copyright (C) 2007, 2010 Free Software Foundation, Inc. ;; ;; This file is part of GCC. ;; @@ -18,6 +18,58 @@ ;; ; MIPS DSP ASE REV 2 Revision 0.02 11/24/2006 +(define_c_enum "unspec" [ + UNSPEC_ABSQ_S_QB + UNSPEC_ADDU_PH + UNSPEC_ADDU_S_PH + UNSPEC_ADDUH_QB + UNSPEC_ADDUH_R_QB + UNSPEC_APPEND + UNSPEC_BALIGN + UNSPEC_CMPGDU_EQ_QB + UNSPEC_CMPGDU_LT_QB + UNSPEC_CMPGDU_LE_QB + UNSPEC_DPA_W_PH + UNSPEC_DPS_W_PH + UNSPEC_MADD + UNSPEC_MADDU + UNSPEC_MSUB + UNSPEC_MSUBU + UNSPEC_MUL_PH + UNSPEC_MUL_S_PH + UNSPEC_MULQ_RS_W + UNSPEC_MULQ_S_PH + UNSPEC_MULQ_S_W + UNSPEC_MULSA_W_PH + UNSPEC_MULT + UNSPEC_MULTU + UNSPEC_PRECR_QB_PH + UNSPEC_PRECR_SRA_PH_W + UNSPEC_PRECR_SRA_R_PH_W + UNSPEC_PREPEND + UNSPEC_SHRA_QB + UNSPEC_SHRA_R_QB + UNSPEC_SHRL_PH + UNSPEC_SUBU_PH + UNSPEC_SUBU_S_PH + UNSPEC_SUBUH_QB + UNSPEC_SUBUH_R_QB + UNSPEC_ADDQH_PH + UNSPEC_ADDQH_R_PH + UNSPEC_ADDQH_W + UNSPEC_ADDQH_R_W + UNSPEC_SUBQH_PH + UNSPEC_SUBQH_R_PH + UNSPEC_SUBQH_W + UNSPEC_SUBQH_R_W + UNSPEC_DPAX_W_PH + UNSPEC_DPSX_W_PH + UNSPEC_DPAQX_S_W_PH + UNSPEC_DPAQX_SA_W_PH + UNSPEC_DPSQX_S_W_PH + UNSPEC_DPSQX_SA_W_PH +]) + (define_insn "mips_absq_s_qb" [(parallel [(set (match_operand:V4QI 0 "register_operand" "=d") @@ -172,22 +224,6 @@ [(set_attr "type" "imadd") (set_attr "mode" "SI")]) -(define_expand "mips_madd<u>" - [(set (match_operand:DI 0 "register_operand") - (plus:DI - (mult:DI (any_extend:DI (match_operand:SI 2 "register_operand")) - (any_extend:DI (match_operand:SI 3 "register_operand"))) - (match_operand:DI 1 "register_operand")))] - "ISA_HAS_DSPR2 && !TARGET_64BIT") - -(define_expand "mips_msub<u>" - [(set (match_operand:DI 0 "register_operand") - (minus:DI - (match_operand:DI 1 "register_operand") - (mult:DI (any_extend:DI (match_operand:SI 2 "register_operand")) - (any_extend:DI (match_operand:SI 3 "register_operand")))))] - "ISA_HAS_DSPR2 && !TARGET_64BIT") - (define_insn "mulv2hi3" [(parallel [(set (match_operand:V2HI 0 "register_operand" "=d") @@ -268,26 +304,6 @@ [(set_attr "type" "imadd") (set_attr "mode" "SI")]) -(define_insn "mips_mult" - [(set (match_operand:DI 0 "register_operand" "=a") - (mult:DI - (sign_extend:DI (match_operand:SI 1 "register_operand" "d")) - (sign_extend:DI (match_operand:SI 2 "register_operand" "d"))))] - "ISA_HAS_DSPR2 && !TARGET_64BIT" - "mult\t%q0,%1,%2" - [(set_attr "type" "imul") - (set_attr "mode" "SI")]) - -(define_insn "mips_multu" - [(set (match_operand:DI 0 "register_operand" "=a") - (mult:DI - (zero_extend:DI (match_operand:SI 1 "register_operand" "d")) - (zero_extend:DI (match_operand:SI 2 "register_operand" "d"))))] - "ISA_HAS_DSPR2 && !TARGET_64BIT" - "multu\t%q0,%1,%2" - [(set_attr "type" "imul") - (set_attr "mode" "SI")]) - (define_insn "mips_precr_qb_ph" [(set (match_operand:V4QI 0 "register_operand" "=d") (unspec:V4QI [(match_operand:V2HI 1 "reg_or_0_operand" "dYG")