CbC/CbC_gcc: gcc/config/mn10300/mn10300.h comparison

comparison gcc/config/mn10300/mn10300.h @ 67:f6334be47118

update gcc from gcc-4.6-20100522 to gcc-4.6-20110318

author	nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
date	Tue, 22 Mar 2011 17:18:12 +0900
parents	b7f97abdc517
children	04ced10e8804

comparison

equal deleted inserted replaced

-:65488c3d617d
+:f6334be47118
 Matsushita MN10300 series
 Copyright (C) 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2004, 2005,
 2007, 2008, 2009, 2010 Free Software Foundation, Inc.
 Contributed by Jeff Law (law@cygnus.com).
 This file is part of GCC.
 GCC is free software; you can redistribute it and/or modify
 it under the terms of the GNU General Public License as published by
 the Free Software Foundation; either version 3, or (at your option)
 any later version.
 GCC is distributed in the hope that it will be useful,
 but WITHOUT ANY WARRANTY; without even the implied warranty of
 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 GNU General Public License for more details.
 You should have received a copy of the GNU General Public License
 along with GCC; see the file COPYING3.  If not see
 <http://www.gnu.org/licenses/>.  */
 #undef ASM_SPEC
 #undef LIB_SPEC
 #undef ENDFILE_SPEC
-#undef LINK_SPEC
+#undef  LINK_SPEC
 #define LINK_SPEC "%{mrelax:--relax}"
-#undef STARTFILE_SPEC
+#undef  STARTFILE_SPEC
 #define STARTFILE_SPEC "%{!mno-crt0:%{!shared:%{pg:gcrt0%O%s}%{!pg:%{p:mcrt0%O%s}%{!p:crt0%O%s}}}}"
 /* Names to predefine in the preprocessor for this target machine.  */
 #define TARGET_CPU_CPP_BUILTINS()		\
 {						\
 builtin_define ("__mn10300__");		\
 builtin_define ("__MN10300__");		\
 builtin_assert ("cpu=mn10300");		\
 builtin_assert ("machine=mn10300");	\
+						\
+if (TARGET_AM34)				\
+{ 					\
+builtin_define ("__AM33__=4");	\
+builtin_define ("__AM34__");		\
+}					\
+else if (TARGET_AM33_2)			\
+{ 					\
+builtin_define ("__AM33__=2");	\
+builtin_define ("__AM33_2__");	\
+}					\
+else if (TARGET_AM33)			\
+builtin_define ("__AM33__=1");		\
+						\
+builtin_define (TARGET_ALLOW_LIW ?	\
+		      "__LIW__" : "__NO_LIW__");\
+						\
 }						\
 while (0)
-#define CPP_SPEC "%{mam33:-D__AM33__} %{mam33-2:-D__AM33__=2 -D__AM33_2__}"
+enum processor_type
+{
-extern GTY(()) int mn10300_unspec_int_label_counter;
-enum processor_type {
 PROCESSOR_MN10300,
 PROCESSOR_AM33,
-PROCESSOR_AM33_2
+PROCESSOR_AM33_2,
+PROCESSOR_AM34
 };
 extern enum processor_type mn10300_processor;
+extern enum processor_type mn10300_tune_cpu;
 #define TARGET_AM33	(mn10300_processor >= PROCESSOR_AM33)
-#define TARGET_AM33_2	(mn10300_processor == PROCESSOR_AM33_2)
+#define TARGET_AM33_2	(mn10300_processor >= PROCESSOR_AM33_2)
+#define TARGET_AM34	(mn10300_processor >= PROCESSOR_AM34)
 #ifndef PROCESSOR_DEFAULT
 #define PROCESSOR_DEFAULT PROCESSOR_MN10300
 #endif
-#define OVERRIDE_OPTIONS mn10300_override_options ()
 /* Print subsidiary information on the compiler version in use.  */
 #define TARGET_VERSION fprintf (stderr, " (MN10300)");
 /* No data type wants to be aligned rounder than this.  */
 #define BIGGEST_ALIGNMENT	32
 /* Alignment of field after `int : 0' in a structure.  */
-#define EMPTY_FIELD_BOUNDARY 32
+#define EMPTY_FIELD_BOUNDARY    32
 /* Define this if move instructions will actually fail to work
 when given unaligned data.  */
 #define STRICT_ALIGNMENT 1
 /* Define this as 1 if `char' should by default be signed; else as 0.  */
 #define DEFAULT_SIGNED_CHAR 0
+#undef  SIZE_TYPE
+#define SIZE_TYPE "unsigned int"
+#undef  PTRDIFF_TYPE
+#define PTRDIFF_TYPE "int"
+#undef  WCHAR_TYPE
+#define WCHAR_TYPE "long int"
+#undef  WCHAR_TYPE_SIZE
+#define WCHAR_TYPE_SIZE BITS_PER_WORD
 /* Standard register usage.  */
 /* Number of actual hardware registers.
 The hardware registers are assigned numbers for the compiler
 from 0 to just below FIRST_PSEUDO_REGISTER.
 All registers that the compiler knows about must be given numbers,
 even those that are not normally considered general registers.  */
-#define FIRST_PSEUDO_REGISTER 50
+#define FIRST_PSEUDO_REGISTER 52
-/* Specify machine-specific register numbers.  */
+/* Specify machine-specific register numbers.  The commented out entries
-#define FIRST_DATA_REGNUM 0
+are defined in mn10300.md.  */
-#define LAST_DATA_REGNUM 3
+#define FIRST_DATA_REGNUM      0
-#define FIRST_ADDRESS_REGNUM 4
+#define LAST_DATA_REGNUM       3
-#define LAST_ADDRESS_REGNUM 8
+#define FIRST_ADDRESS_REGNUM   4
+/* #define PIC_REG             6 */
+#define LAST_ADDRESS_REGNUM    8
+/* #define SP_REG              9 */
 #define FIRST_EXTENDED_REGNUM 10
-#define LAST_EXTENDED_REGNUM 17
+#define LAST_EXTENDED_REGNUM  17
-#define FIRST_FP_REGNUM 18
+#define FIRST_FP_REGNUM       18
-#define LAST_FP_REGNUM 49
+#define LAST_FP_REGNUM        49
-#define FIRST_ARGUMENT_REGNUM 0
+/* #define MDR_REG            50 */
+/* #define CC_REG             51 */
+#define FIRST_ARGUMENT_REGNUM  0
 /* Specify the registers used for certain standard purposes.
 The values of these macros are register numbers.  */
 /* Register to use for pushing function arguments.  */
-#define STACK_POINTER_REGNUM (LAST_ADDRESS_REGNUM+1)
+#define STACK_POINTER_REGNUM (LAST_ADDRESS_REGNUM + 1)
 /* Base register for access to local variables of the function.  */
-#define FRAME_POINTER_REGNUM (LAST_ADDRESS_REGNUM-1)
+#define FRAME_POINTER_REGNUM (LAST_ADDRESS_REGNUM - 1)
 /* Base register for access to arguments of the function.  This
 is a fake register and will be eliminated into either the frame
 pointer or stack pointer.  */
 #define ARG_POINTER_REGNUM LAST_ADDRESS_REGNUM
 /* Register in which static-chain is passed to a function.  */
-#define STATIC_CHAIN_REGNUM (FIRST_ADDRESS_REGNUM+1)
+#define STATIC_CHAIN_REGNUM (FIRST_ADDRESS_REGNUM + 1)
 /* 1 for registers that have pervasive standard uses
 and are not available for the register allocator.  */
 #define FIXED_REGISTERS \
-{ 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0 \
+{ 0, 0, 0, 0,				/* data regs */		\
-, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 \
+0, 0, 0, 0,				/* addr regs */		\
-, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 \
+1,					/* arg reg */		\
+1,					/* sp reg */		\
+0, 0, 0, 0, 0, 0, 0, 0,		/* extended regs */	\
+0, 0,				/* fp regs (18-19) */	\
+0, 0, 0, 0, 0, 0, 0, 0, 0, 0,	/* fp regs (20-29) */	\
+0, 0, 0, 0, 0, 0, 0, 0, 0, 0,	/* fp regs (30-39) */	\
+0, 0, 0, 0, 0, 0, 0, 0, 0, 0,	/* fp regs (40-49) */	\
+0,					/* mdr reg */		\
+1					/* cc reg */		\
 }
 /* 1 for registers not available across function calls.
 These must include the FIXED_REGISTERS and also any
 registers that can be used without being saved.
 and the register where structure-value addresses are passed.
 Aside from that, you can include as many other registers as you
 like.  */
 #define CALL_USED_REGISTERS \
-{ 1, 1, 0, 0, 1, 1, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0 \
+{ 1, 1, 0, 0,				/* data regs */		\
-, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 \
+1, 1, 0, 0,				/* addr regs */		\
-, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1 \
+1,					/* arg reg */		\
+1,					/* sp reg */		\
+1, 1, 1, 1, 0, 0, 0, 0,		/* extended regs */	\
+1, 1,				/* fp regs (18-19) */	\
+1, 1, 0, 0, 0, 0, 0, 0, 0, 0,	/* fp regs (20-29) */	\
+0, 0, 0, 0, 0, 0, 0, 0, 1, 1,	/* fp regs (30-39) */	\
+1, 1, 1, 1, 1, 1, 1, 1, 1, 1,	/* fp regs (40-49) */	\
+1,					/* mdr reg */		\
+1					/* cc reg */		\
 }
 /* Note: The definition of CALL_REALLY_USED_REGISTERS is not
 redundant.  It is needed when compiling in PIC mode because
 the a2 register becomes fixed (and hence must be marked as
 #define CALL_REALLY_USED_REGISTERS CALL_USED_REGISTERS
 #define REG_ALLOC_ORDER \
 { 0, 1, 4, 5, 2, 3, 6, 7, 10, 11, 12, 13, 14, 15, 16, 17, 8, 9 \
 , 42, 43, 44, 45, 46, 47, 48, 49, 34, 35, 36, 37, 38, 39, 40, 41 \
-, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33 \
+, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 50, 51 \
 }
-#define CONDITIONAL_REGISTER_USAGE \
-{						\
-unsigned int i;				\
-						\
-if (!TARGET_AM33)				\
-{						\
-for (i = FIRST_EXTENDED_REGNUM; 		\
-	   i <= LAST_EXTENDED_REGNUM; i++) 	\
-	fixed_regs[i] = call_used_regs[i] = 1; 	\
-}						\
-if (!TARGET_AM33_2)				\
-{						\
-for (i = FIRST_FP_REGNUM;			\
-	   i <= LAST_FP_REGNUM; 		\
-i++) 				\
-	fixed_regs[i] = call_used_regs[i] = 1;	\
-}						\
-if (flag_pic)					\
-fixed_regs[PIC_OFFSET_TABLE_REGNUM] =       \
-call_used_regs[PIC_OFFSET_TABLE_REGNUM] = 1;\
-}
 /* Return number of consecutive hard regs needed starting at reg REGNO
 to hold something of mode MODE.
 This is ordinarily the length in words of a value of mode MODE
 #define HARD_REGNO_NREGS(REGNO, MODE)   \
 ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
 /* Value is 1 if hard register REGNO can hold a value of machine-mode
 MODE.  */
 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
-((REGNO_REG_CLASS (REGNO) == DATA_REGS \
+mn10300_hard_regno_mode_ok ((REGNO), (MODE))
-|| (TARGET_AM33 && REGNO_REG_CLASS (REGNO) == ADDRESS_REGS) \
-|| REGNO_REG_CLASS (REGNO) == EXTENDED_REGS) \
-? ((REGNO) & 1) == 0 || GET_MODE_SIZE (MODE) <= 4	\
-: ((REGNO) & 1) == 0 || GET_MODE_SIZE (MODE) == 4)
 /* Value is 1 if it is a good idea to tie two pseudo registers
 when one has mode MODE1 and one has mode MODE2.
 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
 for any hard reg, then this must be 0 for correct output.  */
 #define MODES_TIEABLE_P(MODE1, MODE2) \
-(TARGET_AM33  \
+mn10300_modes_tieable ((MODE1), (MODE2))
-|| MODE1 == MODE2 \
-|| (GET_MODE_SIZE (MODE1) <= 4 && GET_MODE_SIZE (MODE2) <= 4))
 /* 4 data, and effectively 3 address registers is small as far as I'm
 concerned.  */
 #define TARGET_SMALL_REGISTER_CLASSES_FOR_MODE_P hook_bool_mode_true
 in a smaller-numbered class.
 For any two classes, it is very desirable that there be another
 class that represents their union.  */
-enum reg_class {
+enum reg_class
-NO_REGS, DATA_REGS, ADDRESS_REGS, SP_REGS,
+{
-DATA_OR_ADDRESS_REGS, SP_OR_ADDRESS_REGS,
+NO_REGS, DATA_REGS, ADDRESS_REGS, SP_REGS, SP_OR_ADDRESS_REGS,
-EXTENDED_REGS, DATA_OR_EXTENDED_REGS, ADDRESS_OR_EXTENDED_REGS,
+EXTENDED_REGS, FP_REGS, FP_ACC_REGS, CC_REGS, MDR_REGS,
-SP_OR_EXTENDED_REGS, SP_OR_ADDRESS_OR_EXTENDED_REGS,
+GENERAL_REGS, SP_OR_GENERAL_REGS, ALL_REGS, LIM_REG_CLASSES
-FP_REGS, FP_ACC_REGS,
-GENERAL_REGS, ALL_REGS, LIM_REG_CLASSES
 };
 #define N_REG_CLASSES (int) LIM_REG_CLASSES
 /* Give names of register classes as strings for dump file.  */
-#define REG_CLASS_NAMES \
+#define REG_CLASS_NAMES					   		\
-{ "NO_REGS", "DATA_REGS", "ADDRESS_REGS", \
+{ "NO_REGS", "DATA_REGS", "ADDRESS_REGS", "SP_REGS", "SP_OR_ADDRESS_REGS", \
-"SP_REGS", "DATA_OR_ADDRESS_REGS", "SP_OR_ADDRESS_REGS", \
+"EXTENDED_REGS", "FP_REGS", "FP_ACC_REGS", "CC_REGS", "MDR_REGS",	\
-"EXTENDED_REGS", \
+"GENERAL_REGS", "SP_OR_GENERAL_REGS", "ALL_REGS", "LIM_REGS"		\
-"DATA_OR_EXTENDED_REGS", "ADDRESS_OR_EXTENDED_REGS", \
+}
-"SP_OR_EXTENDED_REGS", "SP_OR_ADDRESS_OR_EXTENDED_REGS", \
-"FP_REGS", "FP_ACC_REGS", \
-"GENERAL_REGS", "ALL_REGS", "LIM_REGS" }
 /* Define which registers fit in which classes.
 This is an initializer for a vector of HARD_REG_SET
 of length N_REG_CLASSES.  */
-#define REG_CLASS_CONTENTS  			\
+#define REG_CLASS_CONTENTS					\
-{  { 0,	0 },		/* No regs      */	\
+{ { 0,	        0 },	  /* No regs */				\
-{ 0x0000f, 0 },	/* DATA_REGS */		\
+{ 0x0000000f, 0 },	  /* DATA_REGS */			\
-{ 0x001f0, 0 },	/* ADDRESS_REGS */	\
+{ 0x000001f0, 0 },	  /* ADDRESS_REGS */			\
-{ 0x00200, 0 },	/* SP_REGS */		\
+{ 0x00000200, 0 },	  /* SP_REGS */				\
-{ 0x001ff, 0 },	/* DATA_OR_ADDRESS_REGS */\
+{ 0x000003f0, 0 },	  /* SP_OR_ADDRESS_REGS */		\
-{ 0x003f0, 0 },	/* SP_OR_ADDRESS_REGS */\
+{ 0x0003fc00, 0 },	  /* EXTENDED_REGS */			\
-{ 0x3fc00, 0 },	/* EXTENDED_REGS */	\
+{ 0xfffc0000, 0x3ffff },/* FP_REGS */				\
-{ 0x3fc0f, 0 },	/* DATA_OR_EXTENDED_REGS */	\
+{ 0x03fc0000, 0 },	  /* FP_ACC_REGS */			\
-{ 0x3fdf0, 0 },	/* ADDRESS_OR_EXTENDED_REGS */	\
+{ 0x00000000, 0x80000 },/* CC_REGS */				\
-{ 0x3fe00, 0 },	/* SP_OR_EXTENDED_REGS */	\
+{ 0x00000000, 0x40000 },/* MDR_REGS */			\
-{ 0x3fff0, 0 },	/* SP_OR_ADDRESS_OR_EXTENDED_REGS */	\
+{ 0x0003fdff, 0 }, 	  /* GENERAL_REGS */			\
-{ 0xfffc0000, 0x3ffff }, /* FP_REGS */		\
+{ 0x0003ffff, 0 },      /* SP_OR_GENERAL_REGS */		\
-{ 0x03fc0000, 0 },	/* FP_ACC_REGS */	\
+{ 0xffffffff, 0xfffff } /* ALL_REGS */			\
-{ 0x3fdff, 0 }, 	/* GENERAL_REGS */	\
-{ 0xffffffff, 0x3ffff } /* ALL_REGS 	*/	\
 }
 /* The following macro defines cover classes for Integrated Register
 Allocator.  Cover classes is a set of non-intersected register
 classes covering all hard registers used for register allocation
 purpose.  Any move between two registers of a cover class should be
 cheaper than load or store of the registers.  The macro value is
 array of register classes with LIM_REG_CLASSES used as the end
 marker.  */
-#define IRA_COVER_CLASSES                                                    \
+#define IRA_COVER_CLASSES					\
-{                                                                            \
+{								\
-GENERAL_REGS, FP_REGS, LIM_REG_CLASSES \
+GENERAL_REGS, FP_REGS, MDR_REGS, LIM_REG_CLASSES		\
 }
 /* The same information, inverted:
 Return the class number of the smallest class containing
 reg number REGNO.  This could be a conditional expression
 or could index an array.  */
-#define REGNO_REG_CLASS(REGNO) \
+#define REGNO_REG_CLASS(REGNO)			     \
-((REGNO) <= LAST_DATA_REGNUM ? DATA_REGS : \
+((REGNO) <= LAST_DATA_REGNUM ? DATA_REGS :	     \
-(REGNO) <= LAST_ADDRESS_REGNUM ? ADDRESS_REGS : \
+(REGNO) <= LAST_ADDRESS_REGNUM ? ADDRESS_REGS :   \
-(REGNO) == STACK_POINTER_REGNUM ? SP_REGS : \
+(REGNO) == STACK_POINTER_REGNUM ? SP_REGS :	     \
 (REGNO) <= LAST_EXTENDED_REGNUM ? EXTENDED_REGS : \
-(REGNO) <= LAST_FP_REGNUM ? FP_REGS : \
+(REGNO) <= LAST_FP_REGNUM ? FP_REGS :	     \
+(REGNO) == MDR_REG ? MDR_REGS :		     \
+(REGNO) == CC_REG ? CC_REGS :		     \
 NO_REGS)
 /* The class value for index registers, and the one for base regs.  */
-#define INDEX_REG_CLASS DATA_OR_EXTENDED_REGS
+#define INDEX_REG_CLASS \
-#define BASE_REG_CLASS  SP_OR_ADDRESS_REGS
+(TARGET_AM33 ? GENERAL_REGS : DATA_REGS)
+#define BASE_REG_CLASS \
+(TARGET_AM33 ? SP_OR_GENERAL_REGS : SP_OR_ADDRESS_REGS)
 /* Macros to check register numbers against specific register classes.  */
 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
 and check its validity for a certain class.
 # define REG_STRICT 0
 #else
 # define REG_STRICT 1
 #endif
-# define REGNO_IN_RANGE_P(regno,min,max,strict) \
-(IN_RANGE ((regno), (min), (max)) 		\
-|| ((strict)					\
-? (reg_renumber				\
-	  && reg_renumber[(regno)] >= (min)	\
-	  && reg_renumber[(regno)] <= (max))	\
-: (regno) >= FIRST_PSEUDO_REGISTER))
 #define REGNO_DATA_P(regno, strict) \
-(REGNO_IN_RANGE_P ((regno), FIRST_DATA_REGNUM, LAST_DATA_REGNUM, \
+mn10300_regno_in_class_p (regno, DATA_REGS, strict)
-		     (strict)))
 #define REGNO_ADDRESS_P(regno, strict) \
-(REGNO_IN_RANGE_P ((regno), FIRST_ADDRESS_REGNUM, LAST_ADDRESS_REGNUM, \
+mn10300_regno_in_class_p (regno, ADDRESS_REGS, strict)
-		     (strict)))
-#define REGNO_SP_P(regno, strict) \
-(REGNO_IN_RANGE_P ((regno), STACK_POINTER_REGNUM, STACK_POINTER_REGNUM, \
-		     (strict)))
 #define REGNO_EXTENDED_P(regno, strict) \
-(REGNO_IN_RANGE_P ((regno), FIRST_EXTENDED_REGNUM, LAST_EXTENDED_REGNUM, \
+mn10300_regno_in_class_p (regno, EXTENDED_REGS, strict)
-		     (strict)))
+#define REGNO_GENERAL_P(regno, strict) \
-#define REGNO_AM33_P(regno, strict) \
+mn10300_regno_in_class_p (regno, GENERAL_REGS, strict)
-(REGNO_DATA_P ((regno), (strict)) || REGNO_ADDRESS_P ((regno), (strict)) \
-|| REGNO_EXTENDED_P ((regno), (strict)))
-#define REGNO_FP_P(regno, strict) \
-(REGNO_IN_RANGE_P ((regno), FIRST_FP_REGNUM, LAST_FP_REGNUM, (strict)))
 #define REGNO_STRICT_OK_FOR_BASE_P(regno, strict) \
-(REGNO_SP_P ((regno), (strict)) \
+mn10300_regno_in_class_p (regno, BASE_REG_CLASS, strict)
-|| REGNO_ADDRESS_P ((regno), (strict)) \
-|| REGNO_EXTENDED_P ((regno), (strict)))
 #define REGNO_OK_FOR_BASE_P(regno) \
 (REGNO_STRICT_OK_FOR_BASE_P ((regno), REG_STRICT))
 #define REG_OK_FOR_BASE_P(X) \
 (REGNO_OK_FOR_BASE_P (REGNO (X)))
 #define REGNO_STRICT_OK_FOR_BIT_BASE_P(regno, strict) \
-(REGNO_SP_P ((regno), (strict)) || REGNO_ADDRESS_P ((regno), (strict)))
+mn10300_regno_in_class_p (regno, ADDRESS_REGS, strict)
 #define REGNO_OK_FOR_BIT_BASE_P(regno) \
 (REGNO_STRICT_OK_FOR_BIT_BASE_P ((regno), REG_STRICT))
 #define REG_OK_FOR_BIT_BASE_P(X) \
 (REGNO_OK_FOR_BIT_BASE_P (REGNO (X)))
 #define REGNO_STRICT_OK_FOR_INDEX_P(regno, strict) \
-(REGNO_DATA_P ((regno), (strict)) || REGNO_EXTENDED_P ((regno), (strict)))
+mn10300_regno_in_class_p (regno, INDEX_REG_CLASS, strict)
 #define REGNO_OK_FOR_INDEX_P(regno) \
 (REGNO_STRICT_OK_FOR_INDEX_P ((regno), REG_STRICT))
 #define REG_OK_FOR_INDEX_P(X) \
 (REGNO_OK_FOR_INDEX_P (REGNO (X)))
-/* Given an rtx X being reloaded into a reg required to be
-in class CLASS, return the class of reg to actually use.
-In general this is just CLASS; but on some machines
-in some cases it is preferable to use a more restrictive class.  */
-#define PREFERRED_RELOAD_CLASS(X,CLASS)				\
-((X) == stack_pointer_rtx && (CLASS) != SP_REGS		\
-? ADDRESS_OR_EXTENDED_REGS					\
-: (GET_CODE (X) == MEM					\
-|| (GET_CODE (X) == REG					\
-	  && REGNO (X) >= FIRST_PSEUDO_REGISTER)		\
-|| (GET_CODE (X) == SUBREG				\
-	  && GET_CODE (SUBREG_REG (X)) == REG			\
-	  && REGNO (SUBREG_REG (X)) >= FIRST_PSEUDO_REGISTER)	\
-? LIMIT_RELOAD_CLASS (GET_MODE (X), CLASS)		\
-: (CLASS)))
-#define PREFERRED_OUTPUT_RELOAD_CLASS(X,CLASS) \
-(X == stack_pointer_rtx && CLASS != SP_REGS \
-? ADDRESS_OR_EXTENDED_REGS : CLASS)
 #define LIMIT_RELOAD_CLASS(MODE, CLASS) \
 (!TARGET_AM33 && (MODE == QImode || MODE == HImode) ? DATA_REGS : CLASS)
-#define SECONDARY_RELOAD_CLASS(CLASS,MODE,IN) \
-mn10300_secondary_reload_class(CLASS,MODE,IN)
 /* Return the maximum number of consecutive registers
 needed to represent mode MODE in a register of class CLASS.  */
 #define CLASS_MAX_NREGS(CLASS, MODE)	\
 /* Is equal to the size of the saved fp + pc, even if an fp isn't
 saved since the value is used before we know.  */
 #define FIRST_PARM_OFFSET(FNDECL) 4
+/* But the CFA is at the arg pointer directly, not at the first argument.  */
+#define ARG_POINTER_CFA_OFFSET(FNDECL) 0
 #define ELIMINABLE_REGS				\
 {{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM},	\
 { ARG_POINTER_REGNUM, FRAME_POINTER_REGNUM},	\
 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}}
 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
-OFFSET = initial_offset (FROM, TO)
+OFFSET = mn10300_initial_offset (FROM, TO)
-/* We can debug without frame pointers on the mn10300, so eliminate
-them whenever possible.  */
-#define CAN_DEBUG_WITHOUT_FP
-/* Value is the number of bytes of arguments automatically
-popped when returning from a subroutine call.
-FUNDECL is the declaration node of the function (as a tree),
-FUNTYPE is the data type of the function (as a tree),
-or for a library call it is an identifier node for the subroutine name.
-SIZE is the number of bytes of arguments passed on the stack.  */
-#define RETURN_POPS_ARGS(FUNDECL,FUNTYPE,SIZE) 0
 /* We use d0/d1 for passing parameters, so allocate 8 bytes of space
 for a register flushback area.  */
 #define REG_PARM_STACK_SPACE(DECL) 8
 #define OUTGOING_REG_PARM_STACK_SPACE(FNTYPE) 1
 On the MN10300, this is a single integer, which is a number of bytes
 of arguments scanned so far.  */
 #define CUMULATIVE_ARGS struct cum_arg
-struct cum_arg {int nbytes; };
+struct cum_arg
+{
+int nbytes;
+};
 /* Initialize a variable CUM of type CUMULATIVE_ARGS
 for a call to a function whose data type is FNTYPE.
 For a library call, FNTYPE is 0.
 On the MN10300, the offset starts at 0.  */
 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, INDIRECT, N_NAMED_ARGS) \
 ((CUM).nbytes = 0)
-/* Update the data in CUM to advance over an argument
-of mode MODE and data type TYPE.
-(TYPE is null for libcalls where that information may not be available.)  */
-#define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED)	\
-((CUM).nbytes += ((MODE) != BLKmode			\
-	           ? (GET_MODE_SIZE (MODE) + 3) & ~3	\
-	           : (int_size_in_bytes (TYPE) + 3) & ~3))
-/* Define where to put the arguments to a function.
-Value is zero to push the argument on the stack,
-or a hard register in which to store the argument.
-MODE is the argument's machine mode.
-TYPE is the data type of the argument (as a tree).
-This is null for libcalls where that information may
-not be available.
-CUM is a variable of type CUMULATIVE_ARGS which gives info about
-the preceding args and about the function being called.
-NAMED is nonzero if this argument is a named parameter
-(otherwise it is an extra parameter matching an ellipsis).  */
-#define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
-function_arg (&CUM, MODE, TYPE, NAMED)
 #define FUNCTION_VALUE_REGNO_P(N)  mn10300_function_value_regno_p (N)
 #define DEFAULT_PCC_STRUCT_RETURN 0
 #define FUNCTION_PROFILER(FILE, LABELNO) ;
 /* Length in units of the trampoline for entering a nested function.  */
-#define TRAMPOLINE_SIZE 0x1b
+#define TRAMPOLINE_SIZE		16
+#define TRAMPOLINE_ALIGNMENT	32
-#define TRAMPOLINE_ALIGNMENT 32
 /* A C expression whose value is RTL representing the value of the return
 address for the frame COUNT steps up from the current frame.
 On the mn10300, the return address is not at a constant location
 #define RETURN_ADDR_RTX(COUNT, FRAME)   \
 ((COUNT == 0)                         \
 ? gen_rtx_MEM (Pmode, arg_pointer_rtx) \
 : (rtx) 0)
+/* The return address is saved both in the stack and in MDR.  Using
+the stack location is handiest for what unwinding needs.  */
+#define INCOMING_RETURN_ADDR_RTX \
+gen_rtx_MEM (VOIDmode, gen_rtx_REG (VOIDmode, STACK_POINTER_REGNUM))
 /* Maximum number of registers that can appear in a valid memory address.  */
 #define MAX_REGS_PER_ADDRESS 2
-#define HAVE_POST_INCREMENT (TARGET_AM33)
+/* We have post-increments.  */
+#define HAVE_POST_INCREMENT	TARGET_AM33
+#define HAVE_POST_MODIFY_DISP	TARGET_AM33
+/* ... But we don't want to use them for block moves.  Small offsets are
+just as effective, at least for inline block move sizes, and appears
+to produce cleaner code.  */
+#define USE_LOAD_POST_INCREMENT(M)	0
+#define USE_STORE_POST_INCREMENT(M)	0
 /* Accept either REG or SUBREG where a register is valid.  */
 #define RTX_OK_FOR_BASE_P(X, strict)				\
 ((REG_P (X) && REGNO_STRICT_OK_FOR_BASE_P (REGNO (X),		\
 					     (strict))) 	\
 || (GET_CODE (X) == SUBREG && REG_P (SUBREG_REG (X))		\
 && REGNO_STRICT_OK_FOR_BASE_P (REGNO (SUBREG_REG (X)),	\
 				      (strict))))
+#define LEGITIMIZE_RELOAD_ADDRESS(X,MODE,OPNUM,TYPE,IND_L,WIN)		     \
+do {									     \
+rtx new_x = mn10300_legitimize_reload_address (X, MODE, OPNUM, TYPE, IND_L); \
+if (new_x)								     \
+{									     \
+X = new_x;							     \
+goto WIN;								     \
+}									     \
+} while (0)
 /* Nonzero if the constant value X is a legitimate general operand.
 It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE.  */
+#define LEGITIMATE_CONSTANT_P(X) mn10300_legitimate_constant_p (X)
-#define LEGITIMATE_CONSTANT_P(X) 1
 /* Zero if this needs fixing up to become PIC.  */
-#define LEGITIMATE_PIC_OPERAND_P(X) (legitimate_pic_operand_p (X))
+#define LEGITIMATE_PIC_OPERAND_P(X) \
+mn10300_legitimate_pic_operand_p (X)
 /* Register to hold the addressing base for
 position independent code access to data items.  */
 #define PIC_OFFSET_TABLE_REGNUM	PIC_REG
 ((GET_CODE (X) == SYMBOL_REF || GET_CODE (X) == LABEL_REF)	\
 && ! LEGITIMATE_PIC_OPERAND_P (X))
 /* Non-global SYMBOL_REFs have SYMBOL_REF_FLAG enabled.  */
 #define MN10300_GLOBAL_P(X) (! SYMBOL_REF_FLAG (X))
-/* Recognize machine-specific patterns that may appear within
+#define SELECT_CC_MODE(OP, X, Y)  mn10300_select_cc_mode (OP, X, Y)
-constants.  Used for PIC-specific UNSPECs.  */
+#define REVERSIBLE_CC_MODE(MODE)  0
-#define OUTPUT_ADDR_CONST_EXTRA(STREAM, X, FAIL) \
-do									\
-if (GET_CODE (X) == UNSPEC)						\
-{									\
-	switch (XINT ((X), 1))						\
-	  {								\
-	  case UNSPEC_INT_LABEL:					\
-	    asm_fprintf ((STREAM), ".%LLIL" HOST_WIDE_INT_PRINT_DEC,	\
-			 INTVAL (XVECEXP ((X), 0, 0)));			\
-	    break;							\
-	  case UNSPEC_PIC:						\
-	    /* GLOBAL_OFFSET_TABLE or local symbols, no suffix.  */	\
-	    output_addr_const ((STREAM), XVECEXP ((X), 0, 0));		\
-	    break;							\
-	  case UNSPEC_GOT:						\
-	    output_addr_const ((STREAM), XVECEXP ((X), 0, 0));		\
-	    fputs ("@GOT", (STREAM));					\
-	    break;							\
-	  case UNSPEC_GOTOFF:						\
-	    output_addr_const ((STREAM), XVECEXP ((X), 0, 0));		\
-	    fputs ("@GOTOFF", (STREAM));				\
-	    break;							\
-	  case UNSPEC_PLT:						\
-	    output_addr_const ((STREAM), XVECEXP ((X), 0, 0));		\
-	    fputs ("@PLT", (STREAM));					\
-	    break;							\
-	  case UNSPEC_GOTSYM_OFF:					\
-	    assemble_name (STREAM, GOT_SYMBOL_NAME);			\
-	    fputs ("-(", STREAM);					\
-	    output_addr_const (STREAM, XVECEXP (X, 0, 0));		\
-	    fputs ("-.)", STREAM);					\
-	    break;							\
-	  default:							\
-	    goto FAIL;							\
-	  }								\
-	break;								\
-}									\
-else								\
-goto FAIL;							\
-while (0)
-/* Tell final.c how to eliminate redundant test instructions.  */
-/* Here we define machine-dependent flags and fields in cc_status
-(see `conditions.h').  No extra ones are needed for the VAX.  */
-/* Store in cc_status the expressions
-that the condition codes will describe
-after execution of an instruction whose pattern is EXP.
-Do not alter them if the instruction would not alter the cc's.  */
-#define CC_OVERFLOW_UNUSABLE 0x200
-#define CC_NO_CARRY CC_NO_OVERFLOW
-#define NOTICE_UPDATE_CC(EXP, INSN) notice_update_cc(EXP, INSN)
-#define REGISTER_MOVE_COST(MODE, CLASS1, CLASS2) \
-((CLASS1 == CLASS2 && (CLASS1 == ADDRESS_REGS || CLASS1 == DATA_REGS)) ? 2 :\
-((CLASS1 == ADDRESS_REGS || CLASS1 == DATA_REGS) && \
-(CLASS2 == ADDRESS_REGS || CLASS2 == DATA_REGS)) ? 4 : \
-(CLASS1 == SP_REGS && CLASS2 == ADDRESS_REGS) ? 2 : \
-(CLASS1 == ADDRESS_REGS && CLASS2 == SP_REGS) ? 4 : \
-! TARGET_AM33 ? 6 : \
-(CLASS1 == SP_REGS || CLASS2 == SP_REGS) ? 6 : \
-(CLASS1 == CLASS2 && CLASS1 == EXTENDED_REGS) ? 6 : \
-(CLASS1 == FP_REGS || CLASS2 == FP_REGS) ? 6 : \
-(CLASS1 == EXTENDED_REGS || CLASS2 == EXTENDED_REGS) ? 4 : \
-4)
 /* Nonzero if access to memory by bytes or half words is no faster
 than accessing full words.  */
 #define SLOW_BYTE_ACCESS 1
 #define NO_FUNCTION_CSE
 for the MN10300 series, that's our primary concern.  */
 #define MOVE_RATIO(speed) 6
 #define TEXT_SECTION_ASM_OP "\t.section .text"
 #define DATA_SECTION_ASM_OP "\t.section .data"
-#define BSS_SECTION_ASM_OP "\t.section .bss"
+#define BSS_SECTION_ASM_OP  "\t.section .bss"
 #define ASM_COMMENT_START "#"
 /* Output to assembler file text saying following lines
 may contain character constants, extra white space, comments, etc.  */
 #define GLOBAL_ASM_OP "\t.global "
 /* This is how to output a reference to a user-level label named NAME.
 `assemble_name' uses this.  */
-#undef ASM_OUTPUT_LABELREF
+#undef  ASM_OUTPUT_LABELREF
 #define ASM_OUTPUT_LABELREF(FILE, NAME) \
 asm_fprintf (FILE, "%U%s", (*targetm.strip_name_encoding) (NAME))
-#define ASM_PN_FORMAT "%s___%lu"
 /* This is how we tell the assembler that two symbols have the same value.  */
 #define ASM_OUTPUT_DEF(FILE,NAME1,NAME2) \
-do { assemble_name(FILE, NAME1); 	 \
+do					 \
-fputs(" = ", FILE);		 \
+{					 \
-assemble_name(FILE, NAME2);	 \
+assemble_name (FILE, NAME1);	 \
-fputc('\n', FILE); } while (0)
+fputs (" = ", FILE);		 \
+assemble_name (FILE, NAME2);	 \
+fputc ('\n', FILE);		 \
+}					 \
+while (0)
 /* How to refer to registers in assembler output.
 This sequence is indexed by compiler's hard-register-number (see above).  */
-#define REGISTER_NAMES \
+#define REGISTER_NAMES							\
-{ "d0", "d1", "d2", "d3", "a0", "a1", "a2", "a3", "ap", "sp", \
+{ "d0", "d1", "d2", "d3", "a0", "a1", "a2", "a3", "ap", "sp",		\
-"r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7" \
+"r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7"			\
-, "fs0", "fs1", "fs2", "fs3", "fs4", "fs5", "fs6", "fs7" \
+, "fs0", "fs1", "fs2", "fs3", "fs4", "fs5", "fs6", "fs7"		\
-, "fs8", "fs9", "fs10", "fs11", "fs12", "fs13", "fs14", "fs15" \
+, "fs8", "fs9", "fs10", "fs11", "fs12", "fs13", "fs14", "fs15"		\
-, "fs16", "fs17", "fs18", "fs19", "fs20", "fs21", "fs22", "fs23" \
+, "fs16", "fs17", "fs18", "fs19", "fs20", "fs21", "fs22", "fs23"	\
-, "fs24", "fs25", "fs26", "fs27", "fs28", "fs29", "fs30", "fs31" \
+, "fs24", "fs25", "fs26", "fs27", "fs28", "fs29", "fs30", "fs31"	\
+, "mdr", "EPSW"								\
 }
-#define ADDITIONAL_REGISTER_NAMES \
+#define ADDITIONAL_REGISTER_NAMES				\
-{ {"r8",  4}, {"r9",  5}, {"r10", 6}, {"r11", 7}, \
+{ {"r8",  4}, {"r9",  5}, {"r10", 6}, {"r11", 7},		\
-{"r12", 0}, {"r13", 1}, {"r14", 2}, {"r15", 3}, \
+{"r12", 0}, {"r13", 1}, {"r14", 2}, {"r15", 3},		\
-{"e0", 10}, {"e1", 11}, {"e2", 12}, {"e3", 13}, \
+{"e0", 10}, {"e1", 11}, {"e2", 12}, {"e3", 13},		\
-{"e4", 14}, {"e5", 15}, {"e6", 16}, {"e7", 17} \
+{"e4", 14}, {"e5", 15}, {"e6", 16}, {"e7", 17}		\
-, {"fd0", 18}, {"fd2", 20}, {"fd4", 22}, {"fd6", 24} \
+, {"fd0", 18}, {"fd2", 20}, {"fd4", 22}, {"fd6", 24}		\
-, {"fd8", 26}, {"fd10", 28}, {"fd12", 30}, {"fd14", 32} \
+, {"fd8", 26}, {"fd10", 28}, {"fd12", 30}, {"fd14", 32}		\
-, {"fd16", 34}, {"fd18", 36}, {"fd20", 38}, {"fd22", 40} \
+, {"fd16", 34}, {"fd18", 36}, {"fd20", 38}, {"fd22", 40}	\
-, {"fd24", 42}, {"fd26", 44}, {"fd28", 46}, {"fd30", 48} \
+, {"fd24", 42}, {"fd26", 44}, {"fd28", 46}, {"fd30", 48}	\
+, {"cc", CC_REG}						\
 }
 /* Print an instruction operand X on file FILE.
 look in mn10300.c for details */
-#define PRINT_OPERAND(FILE, X, CODE)  print_operand(FILE,X,CODE)
+#define PRINT_OPERAND(FILE, X, CODE) \
+mn10300_print_operand (FILE, X, CODE)
 /* Print a memory operand whose address is X, on file FILE.
 This uses a function in output-vax.c.  */
-#define PRINT_OPERAND_ADDRESS(FILE, ADDR) print_operand_address (FILE, ADDR)
+#define PRINT_OPERAND_ADDRESS(FILE, ADDR) \
+mn10300_print_operand_address (FILE, ADDR)
-#define ASM_OUTPUT_REG_PUSH(FILE,REGNO)
-#define ASM_OUTPUT_REG_POP(FILE,REGNO)
 /* This is how to output an element of a case-vector that is absolute.  */
 #define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) \
 fprintf (FILE, "\t%s .L%d\n", ".long", VALUE)
 /* We don't have to worry about dbx compatibility for the mn10300.  */
 #define DEFAULT_GDB_EXTENSIONS 1
 /* Use dwarf2 debugging info by default.  */
-#undef PREFERRED_DEBUGGING_TYPE
+#undef  PREFERRED_DEBUGGING_TYPE
 #define PREFERRED_DEBUGGING_TYPE DWARF2_DEBUG
+#define DWARF2_DEBUGGING_INFO 1
 #define DWARF2_ASM_LINE_DEBUG_INFO 1
-/* GDB always assumes the current function's frame begins at the value
-of the stack pointer upon entry to the current function.  Accessing
-local variables and parameters passed on the stack is done using the
-base of the frame + an offset provided by GCC.
-For functions which have frame pointers this method works fine;
-the (frame pointer) == (stack pointer at function entry) and GCC provides
-an offset relative to the frame pointer.
-This loses for functions without a frame pointer; GCC provides an offset
-which is relative to the stack pointer after adjusting for the function's
-frame size.  GDB would prefer the offset to be relative to the value of
-the stack pointer at the function's entry.  Yuk!  */
-#define DEBUGGER_AUTO_OFFSET(X) \
-((GET_CODE (X) == PLUS ? INTVAL (XEXP (X, 1)) : 0) \
-+ (frame_pointer_needed \
-? 0 : -initial_offset (FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM)))
-#define DEBUGGER_ARG_OFFSET(OFFSET, X) \
-((GET_CODE (X) == PLUS ? OFFSET : 0) \
-+ (frame_pointer_needed \
-? 0 : -initial_offset (ARG_POINTER_REGNUM, STACK_POINTER_REGNUM)))
 /* Specify the machine mode that this machine uses
 for the index in the tablejump instruction.  */
 #define CASE_VECTOR_MODE Pmode
 /* The assembler op to get a word.  */
 #define FILE_ASM_OP "\t.file\n"
-typedef struct mn10300_cc_status_mdep
-{
-int fpCC;
-}
-cc_status_mdep;
-#define CC_STATUS_MDEP cc_status_mdep
-#define CC_STATUS_MDEP_INIT (cc_status.mdep.fpCC = 0)

Mercurial > hg > CbC > CbC_gcc

comparison gcc/config/mn10300/mn10300.h @ 67:f6334be47118