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comparison gcc/config/pa/pa32-regs.h @ 67:f6334be47118

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update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
author nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
date Tue, 22 Mar 2011 17:18:12 +0900
parents 77e2b8dfacca
children 04ced10e8804
comparison
equal deleted inserted replaced
65:65488c3d617d 67:f6334be47118
1 /* Copyright (C) 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 1 /* Copyright (C) 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007,
2 2008 Free Software Foundation, Inc. 2 2008, 2010 Free Software Foundation, Inc.
3 3
4 This file is part of GCC. 4 This file is part of GCC.
5 5
6 GCC is free software; you can redistribute it and/or modify it under 6 GCC is free software; you can redistribute it and/or modify it under
7 the terms of the GNU General Public License as published by the Free 7 the terms of the GNU General Public License as published by the Free
41 differently: the left and right halves of registers are addressable 41 differently: the left and right halves of registers are addressable
42 as 32-bit registers. So, we will set things up like the 68k which 42 as 32-bit registers. So, we will set things up like the 68k which
43 has different fp units: define separate register sets for the 1.0 43 has different fp units: define separate register sets for the 1.0
44 and 1.1 fp units. */ 44 and 1.1 fp units. */
45 45
46 #define FIRST_PSEUDO_REGISTER 89 /* 32 general regs + 56 fp regs + 46 #define FIRST_PSEUDO_REGISTER 90 /* 32 general regs + 56 fp regs +
47 + 1 shift reg */ 47 + 1 shift reg + frame pointer */
48 48
49 /* 1 for registers that have pervasive standard uses 49 /* 1 for registers that have pervasive standard uses
50 and are not available for the register allocator. 50 and are not available for the register allocator.
51 51
52 On the HP-PA, these are: 52 On the HP-PA, these are:
94 0, 0, 0, 0, 0, 0, 0, 0, \ 94 0, 0, 0, 0, 0, 0, 0, 0, \
95 0, 0, 0, 0, 0, 0, 0, 0, \ 95 0, 0, 0, 0, 0, 0, 0, 0, \
96 0, 0, 0, 0, 0, 0, 0, 0, \ 96 0, 0, 0, 0, 0, 0, 0, 0, \
97 0, 0, 0, 0, 0, 0, 0, 0, \ 97 0, 0, 0, 0, 0, 0, 0, 0, \
98 0, 0, 0, 0, 0, 0, 0, 0, \ 98 0, 0, 0, 0, 0, 0, 0, 0, \
99 0} 99 /* shift register and soft frame pointer */ \
100 0, 1}
100 101
101 /* 1 for registers not available across function calls. 102 /* 1 for registers not available across function calls.
102 These must include the FIXED_REGISTERS and also any 103 These must include the FIXED_REGISTERS and also any
103 registers that can be used without being saved. 104 registers that can be used without being saved.
104 The latter must include the registers where values are returned 105 The latter must include the registers where values are returned
115 0, 0, 0, 0, 0, 0, 0, 0, \ 116 0, 0, 0, 0, 0, 0, 0, 0, \
116 0, 0, 0, 0, 0, 0, 0, 0, \ 117 0, 0, 0, 0, 0, 0, 0, 0, \
117 0, 0, 0, 0, 1, 1, 1, 1, \ 118 0, 0, 0, 0, 1, 1, 1, 1, \
118 1, 1, 1, 1, 1, 1, 1, 1, \ 119 1, 1, 1, 1, 1, 1, 1, 1, \
119 1, 1, 1, 1, 1, 1, 1, 1, \ 120 1, 1, 1, 1, 1, 1, 1, 1, \
120 1} 121 /* shift register and soft frame pointer */ \
121 122 1, 1}
122 #define CONDITIONAL_REGISTER_USAGE \
123 { \
124 int i; \
125 if (!TARGET_PA_11) \
126 { \
127 for (i = 56; i < 88; i++) \
128 fixed_regs[i] = call_used_regs[i] = 1; \
129 for (i = 33; i < 88; i += 2) \
130 fixed_regs[i] = call_used_regs[i] = 1; \
131 } \
132 if (TARGET_DISABLE_FPREGS || TARGET_SOFT_FLOAT)\
133 { \
134 for (i = 32; i < 88; i++) \
135 fixed_regs[i] = call_used_regs[i] = 1; \
136 } \
137 if (flag_pic) \
138 fixed_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \
139 }
140 123
141 /* Allocate the call used registers first. This should minimize 124 /* Allocate the call used registers first. This should minimize
142 the number of registers that need to be saved (as call used 125 the number of registers that need to be saved (as call used
143 registers will generally not be allocated across a call). 126 registers will generally not be allocated across a call).
144 127
170 65, 67, \ 153 65, 67, \
171 /* callee-saved general regs. */ \ 154 /* callee-saved general regs. */ \
172 3, 4, 5, 6, 7, 8, 9, 10, \ 155 3, 4, 5, 6, 7, 8, 9, 10, \
173 11, 12, 13, 14, 15, 16, 17, 18, \ 156 11, 12, 13, 14, 15, 16, 17, 18, \
174 /* special registers. */ \ 157 /* special registers. */ \
175 1, 30, 0, 88} 158 1, 30, 0, 88, 89}
176 159
177 160
178 /* Return number of consecutive hard regs needed starting at reg REGNO 161 /* Return number of consecutive hard regs needed starting at reg REGNO
179 to hold something of mode MODE. 162 to hold something of mode MODE.
180 This is ordinarily the length in words of a value of mode MODE 163 This is ordinarily the length in words of a value of mode MODE
302 is in no class. */ 285 is in no class. */
303 286
304 #define REG_CLASS_CONTENTS \ 287 #define REG_CLASS_CONTENTS \
305 {{0x00000000, 0x00000000, 0x00000000}, /* NO_REGS */ \ 288 {{0x00000000, 0x00000000, 0x00000000}, /* NO_REGS */ \
306 {0x00000002, 0x00000000, 0x00000000}, /* R1_REGS */ \ 289 {0x00000002, 0x00000000, 0x00000000}, /* R1_REGS */ \
307 {0xfffffffe, 0x00000000, 0x00000000}, /* GENERAL_REGS */ \ 290 {0xfffffffe, 0x00000000, 0x02000000}, /* GENERAL_REGS */ \
308 {0x00000000, 0xff000000, 0x00ffffff}, /* FPUPPER_REGS */ \ 291 {0x00000000, 0xff000000, 0x00ffffff}, /* FPUPPER_REGS */ \
309 {0x00000000, 0xffffffff, 0x00ffffff}, /* FP_REGS */ \ 292 {0x00000000, 0xffffffff, 0x00ffffff}, /* FP_REGS */ \
310 {0xfffffffe, 0xffffffff, 0x00ffffff}, /* GENERAL_OR_FP_REGS */ \ 293 {0xfffffffe, 0xffffffff, 0x02ffffff}, /* GENERAL_OR_FP_REGS */ \
311 {0x00000000, 0x00000000, 0x01000000}, /* SHIFT_REGS */ \ 294 {0x00000000, 0x00000000, 0x01000000}, /* SHIFT_REGS */ \
312 {0xfffffffe, 0xffffffff, 0x01ffffff}} /* ALL_REGS */ 295 {0xfffffffe, 0xffffffff, 0x03ffffff}} /* ALL_REGS */
313 296
314 /* The following macro defines cover classes for Integrated Register 297 /* The following macro defines cover classes for Integrated Register
315 Allocator. Cover classes is a set of non-intersected register 298 Allocator. Cover classes is a set of non-intersected register
316 classes covering all hard registers used for register allocation 299 classes covering all hard registers used for register allocation
317 purpose. Any move between two registers of a cover class should be 300 purpose. Any move between two registers of a cover class should be
334 or could index an array. */ 317 or could index an array. */
335 318
336 #define REGNO_REG_CLASS(REGNO) \ 319 #define REGNO_REG_CLASS(REGNO) \
337 ((REGNO) == 0 ? NO_REGS \ 320 ((REGNO) == 0 ? NO_REGS \
338 : (REGNO) == 1 ? R1_REGS \ 321 : (REGNO) == 1 ? R1_REGS \
339 : (REGNO) < 32 ? GENERAL_REGS \ 322 : (REGNO) < 32 || (REGNO) == 89 ? GENERAL_REGS \
340 : (REGNO) < 56 ? FP_REGS \ 323 : (REGNO) < 56 ? FP_REGS \
341 : (REGNO) < 88 ? FPUPPER_REGS \ 324 : (REGNO) < 88 ? FPUPPER_REGS \
342 : SHIFT_REGS) 325 : SHIFT_REGS)
343 326
344 /* Return the maximum number of consecutive registers 327 /* Return the maximum number of consecutive registers
368 "%fr12", "%fr12R", "%fr13", "%fr13R", "%fr14", "%fr14R", "%fr15", "%fr15R", \ 351 "%fr12", "%fr12R", "%fr13", "%fr13R", "%fr14", "%fr14R", "%fr15", "%fr15R", \
369 "%fr16", "%fr16R", "%fr17", "%fr17R", "%fr18", "%fr18R", "%fr19", "%fr19R", \ 352 "%fr16", "%fr16R", "%fr17", "%fr17R", "%fr18", "%fr18R", "%fr19", "%fr19R", \
370 "%fr20", "%fr20R", "%fr21", "%fr21R", "%fr22", "%fr22R", "%fr23", "%fr23R", \ 353 "%fr20", "%fr20R", "%fr21", "%fr21R", "%fr22", "%fr22R", "%fr23", "%fr23R", \
371 "%fr24", "%fr24R", "%fr25", "%fr25R", "%fr26", "%fr26R", "%fr27", "%fr27R", \ 354 "%fr24", "%fr24R", "%fr25", "%fr25R", "%fr26", "%fr26R", "%fr27", "%fr27R", \
372 "%fr28", "%fr28R", "%fr29", "%fr29R", "%fr30", "%fr30R", "%fr31", "%fr31R", \ 355 "%fr28", "%fr28R", "%fr29", "%fr29R", "%fr30", "%fr30R", "%fr31", "%fr31R", \
373 "SAR"} 356 "SAR", "sfp"}
374 357
375 #define ADDITIONAL_REGISTER_NAMES \ 358 #define ADDITIONAL_REGISTER_NAMES \
376 {{"%fr4L",32}, {"%fr5L",34}, {"%fr6L",36}, {"%fr7L",38}, \ 359 {{"%fr4L",32}, {"%fr5L",34}, {"%fr6L",36}, {"%fr7L",38}, \
377 {"%fr8L",40}, {"%fr9L",42}, {"%fr10L",44}, {"%fr11L",46}, \ 360 {"%fr8L",40}, {"%fr9L",42}, {"%fr10L",44}, {"%fr11L",46}, \
378 {"%fr12L",48}, {"%fr13L",50}, {"%fr14L",52}, {"%fr15L",54}, \ 361 {"%fr12L",48}, {"%fr13L",50}, {"%fr14L",52}, {"%fr15L",54}, \