Mercurial > hg > CbC > CbC_gcc
annotate gcc/config/pa/pa32-regs.h @ 67:f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
| author | nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp> |
|---|---|
| date | Tue, 22 Mar 2011 17:18:12 +0900 |
| parents | 77e2b8dfacca |
| children | 04ced10e8804 |
| rev | line source |
|---|---|
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1 /* Copyright (C) 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, |
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2 2008, 2010 Free Software Foundation, Inc. |
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3 |
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4 This file is part of GCC. |
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5 |
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6 GCC is free software; you can redistribute it and/or modify it under |
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7 the terms of the GNU General Public License as published by the Free |
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8 Software Foundation; either version 3, or (at your option) any later |
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9 version. |
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10 |
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11 GCC is distributed in the hope that it will be useful, but WITHOUT ANY |
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12 WARRANTY; without even the implied warranty of MERCHANTABILITY or |
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13 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License |
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14 for more details. |
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15 |
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16 Under Section 7 of GPL version 3, you are granted additional |
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17 permissions described in the GCC Runtime Library Exception, version |
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18 3.1, as published by the Free Software Foundation. |
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19 |
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20 You should have received a copy of the GNU General Public License and |
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21 a copy of the GCC Runtime Library Exception along with this program; |
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22 see the files COPYING3 and COPYING.RUNTIME respectively. If not, see |
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23 <http://www.gnu.org/licenses/>. */ |
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24 |
| 0 | 25 /* Standard register usage. */ |
| 26 | |
| 27 /* Number of actual hardware registers. | |
| 28 The hardware registers are assigned numbers for the compiler | |
| 29 from 0 to just below FIRST_PSEUDO_REGISTER. | |
| 30 All registers that the compiler knows about must be given numbers, | |
| 31 even those that are not normally considered general registers. | |
| 32 | |
| 33 HP-PA 1.0 has 32 fullword registers and 16 floating point | |
| 34 registers. The floating point registers hold either word or double | |
| 35 word values. | |
| 36 | |
| 37 16 additional registers are reserved. | |
| 38 | |
| 39 HP-PA 1.1 has 32 fullword registers and 32 floating point | |
| 40 registers. However, the floating point registers behave | |
| 41 differently: the left and right halves of registers are addressable | |
| 42 as 32-bit registers. So, we will set things up like the 68k which | |
| 43 has different fp units: define separate register sets for the 1.0 | |
| 44 and 1.1 fp units. */ | |
| 45 | |
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46 #define FIRST_PSEUDO_REGISTER 90 /* 32 general regs + 56 fp regs + |
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47 + 1 shift reg + frame pointer */ |
| 0 | 48 |
| 49 /* 1 for registers that have pervasive standard uses | |
| 50 and are not available for the register allocator. | |
| 51 | |
| 52 On the HP-PA, these are: | |
| 53 Reg 0 = 0 (hardware). However, 0 is used for condition code, | |
| 54 so is not fixed. | |
| 55 Reg 1 = ADDIL target/Temporary (hardware). | |
| 56 Reg 2 = Return Pointer | |
| 57 Reg 3 = Frame Pointer | |
| 58 Reg 4 = Frame Pointer (>8k varying frame with HP compilers only) | |
| 59 Reg 4-18 = Preserved Registers | |
| 60 Reg 19 = Linkage Table Register in HPUX 8.0 shared library scheme. | |
| 61 Reg 20-22 = Temporary Registers | |
| 62 Reg 23-26 = Temporary/Parameter Registers | |
| 63 Reg 27 = Global Data Pointer (hp) | |
| 64 Reg 28 = Temporary/Return Value register | |
| 65 Reg 29 = Temporary/Static Chain/Return Value register #2 | |
| 66 Reg 30 = stack pointer | |
| 67 Reg 31 = Temporary/Millicode Return Pointer (hp) | |
| 68 | |
| 69 Freg 0-3 = Status Registers -- Not known to the compiler. | |
| 70 Freg 4-7 = Arguments/Return Value | |
| 71 Freg 8-11 = Temporary Registers | |
| 72 Freg 12-15 = Preserved Registers | |
| 73 | |
| 74 Freg 16-31 = Reserved | |
| 75 | |
| 76 On the Snake, fp regs are | |
| 77 | |
| 78 Freg 0-3 = Status Registers -- Not known to the compiler. | |
| 79 Freg 4L-7R = Arguments/Return Value | |
| 80 Freg 8L-11R = Temporary Registers | |
| 81 Freg 12L-21R = Preserved Registers | |
| 82 Freg 22L-31R = Temporary Registers | |
| 83 | |
| 84 */ | |
| 85 | |
| 86 #define FIXED_REGISTERS \ | |
| 87 {0, 0, 0, 0, 0, 0, 0, 0, \ | |
| 88 0, 0, 0, 0, 0, 0, 0, 0, \ | |
| 89 0, 0, 0, 0, 0, 0, 0, 0, \ | |
| 90 0, 0, 0, 1, 0, 0, 1, 0, \ | |
| 91 /* fp registers */ \ | |
| 92 0, 0, 0, 0, 0, 0, 0, 0, \ | |
| 93 0, 0, 0, 0, 0, 0, 0, 0, \ | |
| 94 0, 0, 0, 0, 0, 0, 0, 0, \ | |
| 95 0, 0, 0, 0, 0, 0, 0, 0, \ | |
| 96 0, 0, 0, 0, 0, 0, 0, 0, \ | |
| 97 0, 0, 0, 0, 0, 0, 0, 0, \ | |
| 98 0, 0, 0, 0, 0, 0, 0, 0, \ | |
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99 /* shift register and soft frame pointer */ \ |
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100 0, 1} |
| 0 | 101 |
| 102 /* 1 for registers not available across function calls. | |
| 103 These must include the FIXED_REGISTERS and also any | |
| 104 registers that can be used without being saved. | |
| 105 The latter must include the registers where values are returned | |
| 106 and the register where structure-value addresses are passed. | |
| 107 Aside from that, you can include as many other registers as you like. */ | |
| 108 #define CALL_USED_REGISTERS \ | |
| 109 {1, 1, 1, 0, 0, 0, 0, 0, \ | |
| 110 0, 0, 0, 0, 0, 0, 0, 0, \ | |
| 111 0, 0, 0, 1, 1, 1, 1, 1, \ | |
| 112 1, 1, 1, 1, 1, 1, 1, 1, \ | |
| 113 /* fp registers */ \ | |
| 114 1, 1, 1, 1, 1, 1, 1, 1, \ | |
| 115 1, 1, 1, 1, 1, 1, 1, 1, \ | |
| 116 0, 0, 0, 0, 0, 0, 0, 0, \ | |
| 117 0, 0, 0, 0, 0, 0, 0, 0, \ | |
| 118 0, 0, 0, 0, 1, 1, 1, 1, \ | |
| 119 1, 1, 1, 1, 1, 1, 1, 1, \ | |
| 120 1, 1, 1, 1, 1, 1, 1, 1, \ | |
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121 /* shift register and soft frame pointer */ \ |
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122 1, 1} |
| 0 | 123 |
| 124 /* Allocate the call used registers first. This should minimize | |
| 125 the number of registers that need to be saved (as call used | |
| 126 registers will generally not be allocated across a call). | |
| 127 | |
| 128 Experimentation has shown slightly better results by allocating | |
| 129 FP registers first. We allocate the caller-saved registers more | |
| 130 or less in reverse order to their allocation as arguments. | |
| 131 | |
| 132 FP registers are ordered so that all L registers are selected before | |
| 133 R registers. This works around a false dependency interlock on the | |
| 134 PA8000 when accessing the high and low parts of an FP register | |
| 135 independently. */ | |
| 136 | |
| 137 #define REG_ALLOC_ORDER \ | |
| 138 { \ | |
| 139 /* caller-saved fp regs. */ \ | |
| 140 68, 70, 72, 74, 76, 78, 80, 82, \ | |
| 141 84, 86, 40, 42, 44, 46, 38, 36, \ | |
| 142 34, 32, \ | |
| 143 69, 71, 73, 75, 77, 79, 81, 83, \ | |
| 144 85, 87, 41, 43, 45, 47, 39, 37, \ | |
| 145 35, 33, \ | |
| 146 /* caller-saved general regs. */ \ | |
| 147 28, 19, 20, 21, 22, 31, 27, 29, \ | |
| 148 23, 24, 25, 26, 2, \ | |
| 149 /* callee-saved fp regs. */ \ | |
| 150 48, 50, 52, 54, 56, 58, 60, 62, \ | |
| 151 64, 66, \ | |
| 152 49, 51, 53, 55, 57, 59, 61, 63, \ | |
| 153 65, 67, \ | |
| 154 /* callee-saved general regs. */ \ | |
| 155 3, 4, 5, 6, 7, 8, 9, 10, \ | |
| 156 11, 12, 13, 14, 15, 16, 17, 18, \ | |
| 157 /* special registers. */ \ | |
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158 1, 30, 0, 88, 89} |
| 0 | 159 |
| 160 | |
| 161 /* Return number of consecutive hard regs needed starting at reg REGNO | |
| 162 to hold something of mode MODE. | |
| 163 This is ordinarily the length in words of a value of mode MODE | |
| 164 but can be less for certain modes in special long registers. | |
| 165 | |
| 166 On the HP-PA, general registers are 32 bits wide. The floating | |
| 167 point registers are 64 bits wide. Snake fp regs are treated as | |
| 168 32 bits wide since the left and right parts are independently | |
| 169 accessible. */ | |
| 170 #define HARD_REGNO_NREGS(REGNO, MODE) \ | |
| 171 (FP_REGNO_P (REGNO) \ | |
| 172 ? (!TARGET_PA_11 \ | |
| 173 ? COMPLEX_MODE_P (MODE) ? 2 : 1 \ | |
| 174 : (GET_MODE_SIZE (MODE) + 4 - 1) / 4) \ | |
| 175 : (GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD) | |
| 176 | |
| 177 /* There are no instructions that use DImode in PA 1.0, so we only | |
| 178 allow it in PA 1.1 and later. */ | |
| 179 #define VALID_FP_MODE_P(MODE) \ | |
| 180 ((MODE) == SFmode || (MODE) == DFmode \ | |
| 181 || (MODE) == SCmode || (MODE) == DCmode \ | |
| 182 || (MODE) == SImode || (TARGET_PA_11 && (MODE) == DImode)) | |
| 183 | |
| 184 /* Value is 1 if hard register REGNO can hold a value of machine-mode MODE. | |
| 185 | |
| 186 On the HP-PA, the cpu registers can hold any mode that fits in 32 bits. | |
| 187 For the 64-bit modes, we choose a set of non-overlapping general registers | |
| 188 that includes the incoming arguments and the return value. We specify a | |
| 189 set with no overlaps so that we don't have to specify that the destination | |
| 190 register is an early clobber in patterns using this mode. Except for the | |
| 191 return value, the starting registers are odd. For 128 and 256 bit modes, | |
| 192 we similarly specify non-overlapping sets of cpu registers. However, | |
| 193 there aren't any patterns defined for modes larger than 64 bits at the | |
| 194 moment. | |
| 195 | |
| 196 We limit the modes allowed in the floating point registers to the | |
| 197 set of modes used in the machine definition. In addition, we allow | |
| 198 the complex modes SCmode and DCmode. The real and imaginary parts | |
| 199 of complex modes are allocated to separate registers. This might | |
| 200 allow patterns to be defined in the future to operate on these values. | |
| 201 | |
| 202 The PA 2.0 architecture specifies that quad-precision floating-point | |
| 203 values should start on an even floating point register. Thus, we | |
| 204 choose non-overlapping sets of registers starting on even register | |
| 205 boundaries for large modes. However, there is currently no support | |
| 206 in the machine definition for modes larger than 64 bits. TFmode is | |
| 207 supported under HP-UX using libcalls. Since TFmode values are passed | |
| 208 by reference, they never need to be loaded into the floating-point | |
| 209 registers. */ | |
| 210 #define HARD_REGNO_MODE_OK(REGNO, MODE) \ | |
| 211 ((REGNO) == 0 ? (MODE) == CCmode || (MODE) == CCFPmode \ | |
| 212 : !TARGET_PA_11 && FP_REGNO_P (REGNO) \ | |
| 213 ? (VALID_FP_MODE_P (MODE) \ | |
| 214 && (GET_MODE_SIZE (MODE) <= 8 \ | |
| 215 || (GET_MODE_SIZE (MODE) == 16 && ((REGNO) & 3) == 0))) \ | |
| 216 : FP_REGNO_P (REGNO) \ | |
| 217 ? (VALID_FP_MODE_P (MODE) \ | |
| 218 && (GET_MODE_SIZE (MODE) <= 4 \ | |
| 219 || (GET_MODE_SIZE (MODE) == 8 && ((REGNO) & 1) == 0) \ | |
| 220 || (GET_MODE_SIZE (MODE) == 16 && ((REGNO) & 3) == 0) \ | |
| 221 || (GET_MODE_SIZE (MODE) == 32 && ((REGNO) & 7) == 0))) \ | |
| 222 : (GET_MODE_SIZE (MODE) <= UNITS_PER_WORD \ | |
| 223 || (GET_MODE_SIZE (MODE) == 2 * UNITS_PER_WORD \ | |
| 224 && ((((REGNO) & 1) == 1 && (REGNO) <= 25) || (REGNO) == 28)) \ | |
| 225 || (GET_MODE_SIZE (MODE) == 4 * UNITS_PER_WORD \ | |
| 226 && ((REGNO) & 3) == 3 && (REGNO) <= 23) \ | |
| 227 || (GET_MODE_SIZE (MODE) == 8 * UNITS_PER_WORD \ | |
| 228 && ((REGNO) & 7) == 3 && (REGNO) <= 19))) | |
| 229 | |
| 230 /* How to renumber registers for dbx and gdb. | |
| 231 | |
| 232 Registers 0 - 31 remain unchanged. | |
| 233 | |
| 234 Registers 32 - 87 are mapped to 72 - 127 | |
| 235 | |
| 236 Register 88 is mapped to 32. */ | |
| 237 | |
| 238 #define DBX_REGISTER_NUMBER(REGNO) \ | |
| 239 ((REGNO) <= 31 ? (REGNO) : \ | |
| 240 ((REGNO) <= 87 ? (REGNO) + 40 : 32)) | |
| 241 | |
| 242 /* We must not use the DBX register numbers for the DWARF 2 CFA column | |
| 243 numbers because that maps to numbers beyond FIRST_PSEUDO_REGISTER. | |
| 244 Instead use the identity mapping. */ | |
| 245 #define DWARF_FRAME_REGNUM(REG) REG | |
| 246 | |
| 247 /* Define the classes of registers for register constraints in the | |
| 248 machine description. Also define ranges of constants. | |
| 249 | |
| 250 One of the classes must always be named ALL_REGS and include all hard regs. | |
| 251 If there is more than one class, another class must be named NO_REGS | |
| 252 and contain no registers. | |
| 253 | |
| 254 The name GENERAL_REGS must be the name of a class (or an alias for | |
| 255 another name such as ALL_REGS). This is the class of registers | |
| 256 that is allowed by "g" or "r" in a register constraint. | |
| 257 Also, registers outside this class are allocated only when | |
| 258 instructions express preferences for them. | |
| 259 | |
| 260 The classes must be numbered in nondecreasing order; that is, | |
| 261 a larger-numbered class must never be contained completely | |
| 262 in a smaller-numbered class. | |
| 263 | |
| 264 For any two classes, it is very desirable that there be another | |
| 265 class that represents their union. */ | |
| 266 | |
| 267 /* The HP-PA has four kinds of registers: general regs, 1.0 fp regs, | |
| 268 1.1 fp regs, and the high 1.1 fp regs, to which the operands of | |
| 269 fmpyadd and fmpysub are restricted. */ | |
| 270 | |
| 271 enum reg_class { NO_REGS, R1_REGS, GENERAL_REGS, FPUPPER_REGS, FP_REGS, | |
| 272 GENERAL_OR_FP_REGS, SHIFT_REGS, ALL_REGS, LIM_REG_CLASSES}; | |
| 273 | |
| 274 #define N_REG_CLASSES (int) LIM_REG_CLASSES | |
| 275 | |
| 276 /* Give names of register classes as strings for dump file. */ | |
| 277 | |
| 278 #define REG_CLASS_NAMES \ | |
| 279 {"NO_REGS", "R1_REGS", "GENERAL_REGS", "FPUPPER_REGS", "FP_REGS", \ | |
| 280 "GENERAL_OR_FP_REGS", "SHIFT_REGS", "ALL_REGS"} | |
| 281 | |
| 282 /* Define which registers fit in which classes. | |
| 283 This is an initializer for a vector of HARD_REG_SET | |
| 284 of length N_REG_CLASSES. Register 0, the "condition code" register, | |
| 285 is in no class. */ | |
| 286 | |
| 287 #define REG_CLASS_CONTENTS \ | |
| 288 {{0x00000000, 0x00000000, 0x00000000}, /* NO_REGS */ \ | |
| 289 {0x00000002, 0x00000000, 0x00000000}, /* R1_REGS */ \ | |
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290 {0xfffffffe, 0x00000000, 0x02000000}, /* GENERAL_REGS */ \ |
| 0 | 291 {0x00000000, 0xff000000, 0x00ffffff}, /* FPUPPER_REGS */ \ |
| 292 {0x00000000, 0xffffffff, 0x00ffffff}, /* FP_REGS */ \ | |
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293 {0xfffffffe, 0xffffffff, 0x02ffffff}, /* GENERAL_OR_FP_REGS */ \ |
| 0 | 294 {0x00000000, 0x00000000, 0x01000000}, /* SHIFT_REGS */ \ |
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295 {0xfffffffe, 0xffffffff, 0x03ffffff}} /* ALL_REGS */ |
| 0 | 296 |
| 297 /* The following macro defines cover classes for Integrated Register | |
| 298 Allocator. Cover classes is a set of non-intersected register | |
| 299 classes covering all hard registers used for register allocation | |
| 300 purpose. Any move between two registers of a cover class should be | |
| 301 cheaper than load or store of the registers. The macro value is | |
| 302 array of register classes with LIM_REG_CLASSES used as the end | |
| 303 marker. */ | |
| 304 | |
| 305 #define IRA_COVER_CLASSES \ | |
| 306 { \ | |
| 307 GENERAL_REGS, FP_REGS, SHIFT_REGS, LIM_REG_CLASSES \ | |
| 308 } | |
| 309 | |
| 310 /* Defines invalid mode changes. */ | |
| 311 | |
| 312 #define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS) \ | |
| 313 pa_cannot_change_mode_class (FROM, TO, CLASS) | |
| 314 | |
| 315 /* Return the class number of the smallest class containing | |
| 316 reg number REGNO. This could be a conditional expression | |
| 317 or could index an array. */ | |
| 318 | |
| 319 #define REGNO_REG_CLASS(REGNO) \ | |
| 320 ((REGNO) == 0 ? NO_REGS \ | |
| 321 : (REGNO) == 1 ? R1_REGS \ | |
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322 : (REGNO) < 32 || (REGNO) == 89 ? GENERAL_REGS \ |
| 0 | 323 : (REGNO) < 56 ? FP_REGS \ |
| 324 : (REGNO) < 88 ? FPUPPER_REGS \ | |
| 325 : SHIFT_REGS) | |
| 326 | |
| 327 /* Return the maximum number of consecutive registers | |
| 328 needed to represent mode MODE in a register of class CLASS. */ | |
| 329 #define CLASS_MAX_NREGS(CLASS, MODE) \ | |
| 330 ((CLASS) == FP_REGS || (CLASS) == FPUPPER_REGS \ | |
| 331 ? (!TARGET_PA_11 \ | |
| 332 ? COMPLEX_MODE_P (MODE) ? 2 : 1 \ | |
| 333 : (GET_MODE_SIZE (MODE) + 4 - 1) / 4) \ | |
| 334 : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)) | |
| 335 | |
| 336 /* 1 if N is a possible register number for function argument passing. */ | |
| 337 | |
| 338 #define FUNCTION_ARG_REGNO_P(N) \ | |
| 339 (((N) >= 23 && (N) <= 26) || (! TARGET_SOFT_FLOAT && (N) >= 32 && (N) <= 39)) | |
| 340 | |
| 341 /* How to refer to registers in assembler output. | |
| 342 This sequence is indexed by compiler's hard-register-number (see above). */ | |
| 343 | |
| 344 #define REGISTER_NAMES \ | |
| 345 {"%r0", "%r1", "%r2", "%r3", "%r4", "%r5", "%r6", "%r7", \ | |
| 346 "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15", \ | |
| 347 "%r16", "%r17", "%r18", "%r19", "%r20", "%r21", "%r22", "%r23", \ | |
| 348 "%r24", "%r25", "%r26", "%r27", "%r28", "%r29", "%r30", "%r31", \ | |
| 349 "%fr4", "%fr4R", "%fr5", "%fr5R", "%fr6", "%fr6R", "%fr7", "%fr7R", \ | |
| 350 "%fr8", "%fr8R", "%fr9", "%fr9R", "%fr10", "%fr10R", "%fr11", "%fr11R", \ | |
| 351 "%fr12", "%fr12R", "%fr13", "%fr13R", "%fr14", "%fr14R", "%fr15", "%fr15R", \ | |
| 352 "%fr16", "%fr16R", "%fr17", "%fr17R", "%fr18", "%fr18R", "%fr19", "%fr19R", \ | |
| 353 "%fr20", "%fr20R", "%fr21", "%fr21R", "%fr22", "%fr22R", "%fr23", "%fr23R", \ | |
| 354 "%fr24", "%fr24R", "%fr25", "%fr25R", "%fr26", "%fr26R", "%fr27", "%fr27R", \ | |
| 355 "%fr28", "%fr28R", "%fr29", "%fr29R", "%fr30", "%fr30R", "%fr31", "%fr31R", \ | |
|
67
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
356 "SAR", "sfp"} |
| 0 | 357 |
| 358 #define ADDITIONAL_REGISTER_NAMES \ | |
| 359 {{"%fr4L",32}, {"%fr5L",34}, {"%fr6L",36}, {"%fr7L",38}, \ | |
| 360 {"%fr8L",40}, {"%fr9L",42}, {"%fr10L",44}, {"%fr11L",46}, \ | |
| 361 {"%fr12L",48}, {"%fr13L",50}, {"%fr14L",52}, {"%fr15L",54}, \ | |
| 362 {"%fr16L",56}, {"%fr17L",58}, {"%fr18L",60}, {"%fr19L",62}, \ | |
| 363 {"%fr20L",64}, {"%fr21L",66}, {"%fr22L",68}, {"%fr23L",70}, \ | |
| 364 {"%fr24L",72}, {"%fr25L",74}, {"%fr26L",76}, {"%fr27L",78}, \ | |
| 365 {"%fr28L",80}, {"%fr29L",82}, {"%fr30L",84}, {"%fr31R",86}, \ | |
| 366 {"%cr11",88}} | |
| 367 | |
| 368 #define FP_SAVED_REG_LAST 66 | |
| 369 #define FP_SAVED_REG_FIRST 48 | |
| 370 #define FP_REG_STEP 2 | |
| 371 #define FP_REG_FIRST 32 | |
| 372 #define FP_REG_LAST 87 |