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comparison gcc/config/sh/sh.h @ 67:f6334be47118

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update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
author nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
date Tue, 22 Mar 2011 17:18:12 +0900
parents b7f97abdc517
children 04ced10e8804
comparison
equal deleted inserted replaced
65:65488c3d617d 67:f6334be47118
96 builtin_define ("__FMOVD_ENABLED__"); \ 96 builtin_define ("__FMOVD_ENABLED__"); \
97 builtin_define (TARGET_LITTLE_ENDIAN \ 97 builtin_define (TARGET_LITTLE_ENDIAN \
98 ? "__LITTLE_ENDIAN__" : "__BIG_ENDIAN__"); \ 98 ? "__LITTLE_ENDIAN__" : "__BIG_ENDIAN__"); \
99 } while (0) 99 } while (0)
100 100
101 #define CAN_DEBUG_WITHOUT_FP
102
103 /* Value should be nonzero if functions must have frame pointers. 101 /* Value should be nonzero if functions must have frame pointers.
104 Zero means the frame pointer need not be set up (and parms may be accessed 102 Zero means the frame pointer need not be set up (and parms may be accessed
105 via the stack pointer) in functions that seem suitable. */ 103 via the stack pointer) in functions that seem suitable. */
106 104
107 #ifndef SUBTARGET_FRAME_POINTER_REQUIRED 105 #ifndef SUBTARGET_FRAME_POINTER_REQUIRED
108 #define SUBTARGET_FRAME_POINTER_REQUIRED 0 106 #define SUBTARGET_FRAME_POINTER_REQUIRED 0
109 #endif 107 #endif
110 108
111 #define CONDITIONAL_REGISTER_USAGE do \
112 { \
113 int regno; \
114 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno ++) \
115 if (! VALID_REGISTER_P (regno)) \
116 fixed_regs[regno] = call_used_regs[regno] = 1; \
117 /* R8 and R9 are call-clobbered on SH5, but not on earlier SH ABIs. */ \
118 if (TARGET_SH5) \
119 { \
120 call_used_regs[FIRST_GENERAL_REG + 8] \
121 = call_used_regs[FIRST_GENERAL_REG + 9] = 1; \
122 call_really_used_regs[FIRST_GENERAL_REG + 8] \
123 = call_really_used_regs[FIRST_GENERAL_REG + 9] = 1; \
124 } \
125 if (TARGET_SHMEDIA) \
126 { \
127 regno_reg_class[FIRST_GENERAL_REG] = GENERAL_REGS; \
128 CLEAR_HARD_REG_SET (reg_class_contents[FP0_REGS]); \
129 regno_reg_class[FIRST_FP_REG] = FP_REGS; \
130 } \
131 if (flag_pic) \
132 { \
133 fixed_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \
134 call_used_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \
135 } \
136 /* Renesas saves and restores mac registers on call. */ \
137 if (TARGET_HITACHI && ! TARGET_NOMACSAVE) \
138 { \
139 call_really_used_regs[MACH_REG] = 0; \
140 call_really_used_regs[MACL_REG] = 0; \
141 } \
142 for (regno = FIRST_FP_REG + (TARGET_LITTLE_ENDIAN != 0); \
143 regno <= LAST_FP_REG; regno += 2) \
144 SET_HARD_REG_BIT (reg_class_contents[DF_HI_REGS], regno); \
145 if (TARGET_SHMEDIA) \
146 { \
147 for (regno = FIRST_TARGET_REG; regno <= LAST_TARGET_REG; regno ++)\
148 if (! fixed_regs[regno] && call_really_used_regs[regno]) \
149 SET_HARD_REG_BIT (reg_class_contents[SIBCALL_REGS], regno); \
150 } \
151 else \
152 for (regno = FIRST_GENERAL_REG; regno <= LAST_GENERAL_REG; regno++) \
153 if (! fixed_regs[regno] && call_really_used_regs[regno]) \
154 SET_HARD_REG_BIT (reg_class_contents[SIBCALL_REGS], regno); \
155 } while (0)
156 109
157 /* Nonzero if this is an ELF target - compile time only */ 110 /* Nonzero if this is an ELF target - compile time only */
158 #define TARGET_ELF 0 111 #define TARGET_ELF 0
159 112
160 /* Nonzero if we should generate code using type 2E insns. */ 113 /* Nonzero if we should generate code using type 2E insns. */
450 #endif /* MASK_SH5 */ 403 #endif /* MASK_SH5 */
451 404
452 #define SUBTARGET_LINK_EMUL_SUFFIX "" 405 #define SUBTARGET_LINK_EMUL_SUFFIX ""
453 #define SUBTARGET_LINK_SPEC "" 406 #define SUBTARGET_LINK_SPEC ""
454 407
455 /* svr4.h redefines LINK_SPEC inappropriately, so go via SH_LINK_SPEC, 408 /* Go via SH_LINK_SPEC to avoid code replication. */
456 so that we can undo the damage without code replication. */
457 #define LINK_SPEC SH_LINK_SPEC 409 #define LINK_SPEC SH_LINK_SPEC
458 410
459 #define SH_LINK_SPEC "\ 411 #define SH_LINK_SPEC "\
460 -m %(link_emul_prefix)\ 412 -m %(link_emul_prefix)\
461 %{m5-compact*|m5-32media*:32}\ 413 %{m5-compact*|m5-32media*:32}\
467 #ifndef SH_DIV_STR_FOR_SIZE 419 #ifndef SH_DIV_STR_FOR_SIZE
468 #define SH_DIV_STR_FOR_SIZE "call" 420 #define SH_DIV_STR_FOR_SIZE "call"
469 #endif 421 #endif
470 422
471 #define DRIVER_SELF_SPECS "%{m2a:%{ml:%eSH2a does not support little-endian}}" 423 #define DRIVER_SELF_SPECS "%{m2a:%{ml:%eSH2a does not support little-endian}}"
472
473 #define OPTIMIZATION_OPTIONS(LEVEL,SIZE) sh_optimization_options (LEVEL, SIZE)
474 424
475 #define ASSEMBLER_DIALECT assembler_dialect 425 #define ASSEMBLER_DIALECT assembler_dialect
476 426
477 extern int assembler_dialect; 427 extern int assembler_dialect;
478 428
503 #define SH_DIV_STRATEGY_DEFAULT SH_DIV_CALL 453 #define SH_DIV_STRATEGY_DEFAULT SH_DIV_CALL
504 #endif 454 #endif
505 455
506 #define SUBTARGET_OVERRIDE_OPTIONS (void) 0 456 #define SUBTARGET_OVERRIDE_OPTIONS (void) 0
507 457
508 extern const char *sh_fixed_range_str;
509
510 #define OVERRIDE_OPTIONS sh_override_options ()
511
512 458
513 /* Target machine storage layout. */ 459 /* Target machine storage layout. */
514 460
515 /* Define this if most significant bit is lowest numbered 461 /* Define this if most significant bit is lowest numbered
516 in instructions that operate on numbered bit-fields. */ 462 in instructions that operate on numbered bit-fields. */
521 #define BYTES_BIG_ENDIAN (TARGET_LITTLE_ENDIAN == 0) 467 #define BYTES_BIG_ENDIAN (TARGET_LITTLE_ENDIAN == 0)
522 468
523 /* Define this if most significant word of a multiword number is the lowest 469 /* Define this if most significant word of a multiword number is the lowest
524 numbered. */ 470 numbered. */
525 #define WORDS_BIG_ENDIAN (TARGET_LITTLE_ENDIAN == 0) 471 #define WORDS_BIG_ENDIAN (TARGET_LITTLE_ENDIAN == 0)
526
527 /* Define this to set the endianness to use in libgcc2.c, which can
528 not depend on target_flags. */
529 #if defined(__LITTLE_ENDIAN__)
530 #define LIBGCC2_WORDS_BIG_ENDIAN 0
531 #else
532 #define LIBGCC2_WORDS_BIG_ENDIAN 1
533 #endif
534 472
535 #define MAX_BITS_PER_WORD 64 473 #define MAX_BITS_PER_WORD 64
536 474
537 /* Width in bits of an `int'. We want just 32-bits, even if words are 475 /* Width in bits of an `int'. We want just 32-bits, even if words are
538 longer. */ 476 longer. */
627 /* If LABEL_AFTER_BARRIER demands an alignment, return its base 2 logarithm. */ 565 /* If LABEL_AFTER_BARRIER demands an alignment, return its base 2 logarithm. */
628 #define LABEL_ALIGN_AFTER_BARRIER(LABEL_AFTER_BARRIER) \ 566 #define LABEL_ALIGN_AFTER_BARRIER(LABEL_AFTER_BARRIER) \
629 barrier_align (LABEL_AFTER_BARRIER) 567 barrier_align (LABEL_AFTER_BARRIER)
630 568
631 #define LOOP_ALIGN(A_LABEL) \ 569 #define LOOP_ALIGN(A_LABEL) \
632 ((! optimize || TARGET_HARD_SH4 || TARGET_SMALLCODE) \ 570 ((! optimize || TARGET_HARD_SH4 || optimize_size) \
633 ? 0 : sh_loop_align (A_LABEL)) 571 ? 0 : sh_loop_align (A_LABEL))
634 572
635 #define LABEL_ALIGN(A_LABEL) \ 573 #define LABEL_ALIGN(A_LABEL) \
636 ( \ 574 ( \
637 (PREV_INSN (A_LABEL) \ 575 (PREV_INSN (A_LABEL) \
820 758
821 #define SHMEDIA_REGISTER_P(REGNO) \ 759 #define SHMEDIA_REGISTER_P(REGNO) \
822 (GENERAL_REGISTER_P (REGNO) || FP_REGISTER_P (REGNO) \ 760 (GENERAL_REGISTER_P (REGNO) || FP_REGISTER_P (REGNO) \
823 || TARGET_REGISTER_P (REGNO)) 761 || TARGET_REGISTER_P (REGNO))
824 762
825 /* This is to be used in CONDITIONAL_REGISTER_USAGE, to mark registers 763 /* This is to be used in TARGET_CONDITIONAL_REGISTER_USAGE, to mark
826 that should be fixed. */ 764 registers that should be fixed. */
827 #define VALID_REGISTER_P(REGNO) \ 765 #define VALID_REGISTER_P(REGNO) \
828 (SHMEDIA_REGISTER_P (REGNO) || XD_REGISTER_P (REGNO) \ 766 (SHMEDIA_REGISTER_P (REGNO) || XD_REGISTER_P (REGNO) \
829 || (REGNO) == AP_REG || (REGNO) == RAP_REG \ 767 || (REGNO) == AP_REG || (REGNO) == RAP_REG \
830 || (REGNO) == FRAME_POINTER_REGNUM \ 768 || (REGNO) == FRAME_POINTER_REGNUM \
831 || (TARGET_SH1 && (SPECIAL_REGISTER_P (REGNO) || (REGNO) == PR_REG)) \ 769 || (TARGET_SH1 && (SPECIAL_REGISTER_P (REGNO) || (REGNO) == PR_REG)) \
922 1, 1, 1, 1, 1, 1, 1, 1, \ 860 1, 1, 1, 1, 1, 1, 1, 1, \
923 /*"rap", "sfp" */ \ 861 /*"rap", "sfp" */ \
924 1, 1, \ 862 1, 1, \
925 } 863 }
926 864
927 /* CONDITIONAL_REGISTER_USAGE might want to make a register call-used, yet 865 /* TARGET_CONDITIONAL_REGISTER_USAGE might want to make a register
928 fixed, like PIC_OFFSET_TABLE_REGNUM. */ 866 call-used, yet fixed, like PIC_OFFSET_TABLE_REGNUM. */
929 #define CALL_REALLY_USED_REGISTERS CALL_USED_REGISTERS 867 #define CALL_REALLY_USED_REGISTERS CALL_USED_REGISTERS
930 868
931 /* Only the lower 32-bits of R10-R14 are guaranteed to be preserved 869 /* Only the lower 32-bits of R10-R14 are guaranteed to be preserved
932 across SHcompact function calls. We can't tell whether a called 870 across SHcompact function calls. We can't tell whether a called
933 function is SHmedia or SHcompact, so we assume it may be when 871 function is SHmedia or SHcompact, so we assume it may be when
1161 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00080000 }, \ 1099 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00080000 }, \
1162 /* MAC_REGS: */ \ 1100 /* MAC_REGS: */ \
1163 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00300000 }, \ 1101 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00300000 }, \
1164 /* FPUL_REGS: */ \ 1102 /* FPUL_REGS: */ \
1165 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00400000 }, \ 1103 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00400000 }, \
1166 /* SIBCALL_REGS: Initialized in CONDITIONAL_REGISTER_USAGE. */ \ 1104 /* SIBCALL_REGS: Initialized in TARGET_CONDITIONAL_REGISTER_USAGE. */ \
1167 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, \ 1105 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, \
1168 /* GENERAL_REGS: */ \ 1106 /* GENERAL_REGS: */ \
1169 { 0xffffffff, 0xffffffff, 0x00000000, 0x00000000, 0x03020000 }, \ 1107 { 0xffffffff, 0xffffffff, 0x00000000, 0x00000000, 0x03020000 }, \
1170 /* FP0_REGS: */ \ 1108 /* FP0_REGS: */ \
1171 { 0x00000000, 0x00000000, 0x00000001, 0x00000000, 0x00000000 }, \ 1109 { 0x00000000, 0x00000000, 0x00000001, 0x00000000, 0x00000000 }, \
1172 /* FP_REGS: */ \ 1110 /* FP_REGS: */ \
1173 { 0x00000000, 0x00000000, 0xffffffff, 0xffffffff, 0x00000000 }, \ 1111 { 0x00000000, 0x00000000, 0xffffffff, 0xffffffff, 0x00000000 }, \
1174 /* DF_HI_REGS: Initialized in CONDITIONAL_REGISTER_USAGE. */ \ 1112 /* DF_HI_REGS: Initialized in TARGET_CONDITIONAL_REGISTER_USAGE. */ \
1175 { 0x00000000, 0x00000000, 0xffffffff, 0xffffffff, 0x0000ff00 }, \ 1113 { 0x00000000, 0x00000000, 0xffffffff, 0xffffffff, 0x0000ff00 }, \
1176 /* DF_REGS: */ \ 1114 /* DF_REGS: */ \
1177 { 0x00000000, 0x00000000, 0xffffffff, 0xffffffff, 0x0000ff00 }, \ 1115 { 0x00000000, 0x00000000, 0xffffffff, 0xffffffff, 0x0000ff00 }, \
1178 /* FPSCR_REGS: */ \ 1116 /* FPSCR_REGS: */ \
1179 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00800000 }, \ 1117 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00800000 }, \
1272 || (HOST_BITS_PER_WIDE_INT >= 64 && (VALUE) == (HOST_WIDE_INT) -1 << 32)) 1210 || (HOST_BITS_PER_WIDE_INT >= 64 && (VALUE) == (HOST_WIDE_INT) -1 << 32))
1273 1211
1274 #define CONST_OK_FOR_K08(VALUE) (((HOST_WIDE_INT)(VALUE))>= 0 \ 1212 #define CONST_OK_FOR_K08(VALUE) (((HOST_WIDE_INT)(VALUE))>= 0 \
1275 && ((HOST_WIDE_INT)(VALUE)) <= 255) 1213 && ((HOST_WIDE_INT)(VALUE)) <= 255)
1276 1214
1277 /* Given an rtx X being reloaded into a reg required to be
1278 in class CLASS, return the class of reg to actually use.
1279 In general this is just CLASS; but on some machines
1280 in some cases it is preferable to use a more restrictive class. */
1281
1282 #define PREFERRED_RELOAD_CLASS(X, CLASS) \
1283 ((CLASS) == NO_REGS && TARGET_SHMEDIA \
1284 && (GET_CODE (X) == CONST_DOUBLE \
1285 || GET_CODE (X) == SYMBOL_REF \
1286 || PIC_ADDR_P (X)) \
1287 ? GENERAL_REGS \
1288 : (CLASS)) \
1289
1290 #if 0 1215 #if 0
1291 #define SECONDARY_INOUT_RELOAD_CLASS(CLASS,MODE,X,ELSE) \ 1216 #define SECONDARY_INOUT_RELOAD_CLASS(CLASS,MODE,X,ELSE) \
1292 ((((REGCLASS_HAS_FP_REG (CLASS) \ 1217 ((((REGCLASS_HAS_FP_REG (CLASS) \
1293 && (REG_P (X) \ 1218 && (REG_P (X) \
1294 && (GENERAL_OR_AP_REGISTER_P (REGNO (X)) \ 1219 && (GENERAL_OR_AP_REGISTER_P (REGNO (X)) \
1421 #endif 1346 #endif
1422 1347
1423 /* Offset of first parameter from the argument pointer register value. */ 1348 /* Offset of first parameter from the argument pointer register value. */
1424 #define FIRST_PARM_OFFSET(FNDECL) 0 1349 #define FIRST_PARM_OFFSET(FNDECL) 0
1425 1350
1426 /* Value is the number of byte of arguments automatically
1427 popped when returning from a subroutine call.
1428 FUNDECL is the declaration node of the function (as a tree),
1429 FUNTYPE is the data type of the function (as a tree),
1430 or for a library call it is an identifier node for the subroutine name.
1431 SIZE is the number of bytes of arguments passed on the stack.
1432
1433 On the SH, the caller does not pop any of its arguments that were passed
1434 on the stack. */
1435 #define RETURN_POPS_ARGS(FUNDECL,FUNTYPE,SIZE) 0
1436
1437 /* Value is the number of bytes of arguments automatically popped when 1351 /* Value is the number of bytes of arguments automatically popped when
1438 calling a subroutine. 1352 calling a subroutine.
1439 CUM is the accumulated argument list. 1353 CUM is the accumulated argument list.
1440 1354
1441 On SHcompact, the call trampoline pops arguments off the stack. */ 1355 On SHcompact, the call trampoline pops arguments off the stack. */
1459 ? FIRST_FP_PARM_REG \ 1373 ? FIRST_FP_PARM_REG \
1460 : (TARGET_SH4 || TARGET_SH2A_DOUBLE) && (GET_MODE_CLASS (MODE) == MODE_FLOAT \ 1374 : (TARGET_SH4 || TARGET_SH2A_DOUBLE) && (GET_MODE_CLASS (MODE) == MODE_FLOAT \
1461 || GET_MODE_CLASS (MODE) == MODE_COMPLEX_FLOAT)\ 1375 || GET_MODE_CLASS (MODE) == MODE_COMPLEX_FLOAT)\
1462 ? FIRST_FP_PARM_REG \ 1376 ? FIRST_FP_PARM_REG \
1463 : FIRST_PARM_REG) 1377 : FIRST_PARM_REG)
1464
1465 #define FUNCTION_VALUE_REGNO_P(REGNO) sh_function_value_regno_p (REGNO)
1466 1378
1467 /* 1 if N is a possible register number for function argument passing. */ 1379 /* 1 if N is a possible register number for function argument passing. */
1468 /* ??? There are some callers that pass REGNO as int, and others that pass 1380 /* ??? There are some callers that pass REGNO as int, and others that pass
1469 it as unsigned. We get warnings unless we do casts everywhere. */ 1381 it as unsigned. We get warnings unless we do casts everywhere. */
1470 #define FUNCTION_ARG_REGNO_P(REGNO) \ 1382 #define FUNCTION_ARG_REGNO_P(REGNO) \
1634 sh_init_cumulative_args (& (CUM), (FNTYPE), (LIBNAME), (FNDECL), (N_NAMED_ARGS), VOIDmode) 1546 sh_init_cumulative_args (& (CUM), (FNTYPE), (LIBNAME), (FNDECL), (N_NAMED_ARGS), VOIDmode)
1635 1547
1636 #define INIT_CUMULATIVE_LIBCALL_ARGS(CUM, MODE, LIBNAME) \ 1548 #define INIT_CUMULATIVE_LIBCALL_ARGS(CUM, MODE, LIBNAME) \
1637 sh_init_cumulative_args (& (CUM), NULL_TREE, (LIBNAME), NULL_TREE, 0, (MODE)) 1549 sh_init_cumulative_args (& (CUM), NULL_TREE, (LIBNAME), NULL_TREE, 0, (MODE))
1638 1550
1639 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
1640 sh_function_arg_advance (&(CUM), (MODE), (TYPE), (NAMED))
1641 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
1642 sh_function_arg (&(CUM), (MODE), (TYPE), (NAMED))
1643
1644 /* Return boolean indicating arg of mode MODE will be passed in a reg. 1551 /* Return boolean indicating arg of mode MODE will be passed in a reg.
1645 This macro is only used in this file. */ 1552 This macro is only used in this file. */
1646 1553
1647 #define PASS_IN_REG_P(CUM, MODE, TYPE) \ 1554 #define PASS_IN_REG_P(CUM, MODE, TYPE) \
1648 (((TYPE) == 0 \ 1555 (((TYPE) == 0 \
1649 || (! TREE_ADDRESSABLE ((tree)(TYPE)) \ 1556 || (! TREE_ADDRESSABLE ((TYPE)) \
1650 && (! (TARGET_HITACHI || (CUM).renesas_abi) \ 1557 && (! (TARGET_HITACHI || (CUM).renesas_abi) \
1651 || ! (AGGREGATE_TYPE_P (TYPE) \ 1558 || ! (AGGREGATE_TYPE_P (TYPE) \
1652 || (!TARGET_FPU_ANY \ 1559 || (!TARGET_FPU_ANY \
1653 && (GET_MODE_CLASS (MODE) == MODE_FLOAT \ 1560 && (GET_MODE_CLASS (MODE) == MODE_FLOAT \
1654 && GET_MODE_SIZE (MODE) > GET_MODE_SIZE (SFmode))))))) \ 1561 && GET_MODE_SIZE (MODE) > GET_MODE_SIZE (SFmode))))))) \
1803 /* Length in units of the trampoline for entering a nested function. */ 1710 /* Length in units of the trampoline for entering a nested function. */
1804 #define TRAMPOLINE_SIZE (TARGET_SHMEDIA64 ? 40 : TARGET_SH5 ? 24 : 16) 1711 #define TRAMPOLINE_SIZE (TARGET_SHMEDIA64 ? 40 : TARGET_SH5 ? 24 : 16)
1805 1712
1806 /* Alignment required for a trampoline in bits . */ 1713 /* Alignment required for a trampoline in bits . */
1807 #define TRAMPOLINE_ALIGNMENT \ 1714 #define TRAMPOLINE_ALIGNMENT \
1808 ((CACHE_LOG < 3 || (TARGET_SMALLCODE && ! TARGET_HARVARD)) ? 32 \ 1715 ((CACHE_LOG < 3 || (optimize_size && ! TARGET_HARVARD)) ? 32 \
1809 : TARGET_SHMEDIA ? 256 : 64) 1716 : TARGET_SHMEDIA ? 256 : 64)
1810 1717
1811 /* A C expression whose value is RTL representing the value of the return 1718 /* A C expression whose value is RTL representing the value of the return
1812 address for the frame COUNT steps up from the current frame. 1719 address for the frame COUNT steps up from the current frame.
1813 FRAMEADDR is already the frame pointer of the COUNT frame, so we 1720 FRAMEADDR is already the frame pointer of the COUNT frame, so we
1835 #define USE_STORE_PRE_DECREMENT(mode) ((mode == SImode || mode == DImode) \ 1742 #define USE_STORE_PRE_DECREMENT(mode) ((mode == SImode || mode == DImode) \
1836 ? 0 : TARGET_SH1) 1743 ? 0 : TARGET_SH1)
1837 1744
1838 #define MOVE_BY_PIECES_P(SIZE, ALIGN) \ 1745 #define MOVE_BY_PIECES_P(SIZE, ALIGN) \
1839 (move_by_pieces_ninsns (SIZE, ALIGN, MOVE_MAX_PIECES + 1) \ 1746 (move_by_pieces_ninsns (SIZE, ALIGN, MOVE_MAX_PIECES + 1) \
1840 < (TARGET_SMALLCODE ? 2 : ((ALIGN >= 32) ? 16 : 2))) 1747 < (optimize_size ? 2 : ((ALIGN >= 32) ? 16 : 2)))
1841 1748
1842 #define STORE_BY_PIECES_P(SIZE, ALIGN) \ 1749 #define STORE_BY_PIECES_P(SIZE, ALIGN) \
1843 (move_by_pieces_ninsns (SIZE, ALIGN, STORE_MAX_PIECES + 1) \ 1750 (move_by_pieces_ninsns (SIZE, ALIGN, STORE_MAX_PIECES + 1) \
1844 < (TARGET_SMALLCODE ? 2 : ((ALIGN >= 32) ? 16 : 2))) 1751 < (optimize_size ? 2 : ((ALIGN >= 32) ? 16 : 2)))
1845 1752
1846 #define SET_BY_PIECES_P(SIZE, ALIGN) STORE_BY_PIECES_P(SIZE, ALIGN) 1753 #define SET_BY_PIECES_P(SIZE, ALIGN) STORE_BY_PIECES_P(SIZE, ALIGN)
1847 1754
1848 /* Macros to check register numbers against specific register classes. */ 1755 /* Macros to check register numbers against specific register classes. */
1849 1756
2050 1957
2051 /* Since the SH2e has only `float' support, it is desirable to make all 1958 /* Since the SH2e has only `float' support, it is desirable to make all
2052 floating point types equivalent to `float'. */ 1959 floating point types equivalent to `float'. */
2053 #define DOUBLE_TYPE_SIZE ((TARGET_SH2E && ! TARGET_SH4 && ! TARGET_SH2A_DOUBLE) ? 32 : 64) 1960 #define DOUBLE_TYPE_SIZE ((TARGET_SH2E && ! TARGET_SH4 && ! TARGET_SH2A_DOUBLE) ? 32 : 64)
2054 1961
2055 #if defined(__SH2E__) || defined(__SH3E__) || defined( __SH2A_SINGLE_ONLY__) || defined( __SH4_SINGLE_ONLY__)
2056 #define LIBGCC2_DOUBLE_TYPE_SIZE 32
2057 #else
2058 #define LIBGCC2_DOUBLE_TYPE_SIZE 64
2059 #endif
2060
2061 /* 'char' is signed by default. */ 1962 /* 'char' is signed by default. */
2062 #define DEFAULT_SIGNED_CHAR 1 1963 #define DEFAULT_SIGNED_CHAR 1
2063 1964
2064 /* The type of size_t unsigned int. */ 1965 /* The type of size_t unsigned int. */
2065 #define SIZE_TYPE (TARGET_SH5 ? "long unsigned int" : "unsigned int") 1966 #define SIZE_TYPE (TARGET_SH5 ? "long unsigned int" : "unsigned int")
2187 || (! TARGET_SHMEDIA && (CLASS) == SIBCALL_REGS)) 2088 || (! TARGET_SHMEDIA && (CLASS) == SIBCALL_REGS))
2188 2089
2189 #define REGCLASS_HAS_FP_REG(CLASS) \ 2090 #define REGCLASS_HAS_FP_REG(CLASS) \
2190 ((CLASS) == FP0_REGS || (CLASS) == FP_REGS \ 2091 ((CLASS) == FP0_REGS || (CLASS) == FP_REGS \
2191 || (CLASS) == DF_REGS || (CLASS) == DF_HI_REGS) 2092 || (CLASS) == DF_REGS || (CLASS) == DF_HI_REGS)
2192
2193 #define REGISTER_MOVE_COST(MODE, SRCCLASS, DSTCLASS) \
2194 sh_register_move_cost ((MODE), (SRCCLASS), (DSTCLASS))
2195 2093
2196 /* ??? Perhaps make MEMORY_MOVE_COST depend on compiler option? This 2094 /* ??? Perhaps make MEMORY_MOVE_COST depend on compiler option? This
2197 would be so that people with slow memory systems could generate 2095 would be so that people with slow memory systems could generate
2198 different code that does fewer memory accesses. */ 2096 different code that does fewer memory accesses. */
2199 2097
2310 } 2208 }
2311 2209
2312 /* DBX register number for a given compiler register number. */ 2210 /* DBX register number for a given compiler register number. */
2313 /* GDB has FPUL at 23 and FP0 at 25, so we must add one to all FP registers 2211 /* GDB has FPUL at 23 and FP0 at 25, so we must add one to all FP registers
2314 to match gdb. */ 2212 to match gdb. */
2315 /* svr4.h undefines this macro, yet we really want to use the same numbers
2316 for coff as for elf, so we go via another macro: SH_DBX_REGISTER_NUMBER. */
2317 /* expand_builtin_init_dwarf_reg_sizes uses this to test if a 2213 /* expand_builtin_init_dwarf_reg_sizes uses this to test if a
2318 register exists, so we should return -1 for invalid register numbers. */ 2214 register exists, so we should return -1 for invalid register numbers. */
2319 #define DBX_REGISTER_NUMBER(REGNO) SH_DBX_REGISTER_NUMBER (REGNO) 2215 #define DBX_REGISTER_NUMBER(REGNO) SH_DBX_REGISTER_NUMBER (REGNO)
2320 2216
2321 /* SHcompact PR_REG used to use the encoding 241, and SHcompact FP registers 2217 /* SHcompact PR_REG used to use the encoding 241, and SHcompact FP registers
2439 by changing the contents of the vector. */ 2335 by changing the contents of the vector. */
2440 2336
2441 #define FINAL_PRESCAN_INSN(INSN, OPVEC, NOPERANDS) \ 2337 #define FINAL_PRESCAN_INSN(INSN, OPVEC, NOPERANDS) \
2442 final_prescan_insn ((INSN), (OPVEC), (NOPERANDS)) 2338 final_prescan_insn ((INSN), (OPVEC), (NOPERANDS))
2443 2339
2444 /* Print operand X (an rtx) in assembler syntax to file FILE.
2445 CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
2446 For `%' followed by punctuation, CODE is the punctuation and X is null. */
2447
2448 #define PRINT_OPERAND(STREAM, X, CODE) print_operand ((STREAM), (X), (CODE))
2449
2450 /* Print a memory address as an operand to reference that memory location. */
2451
2452 #define PRINT_OPERAND_ADDRESS(STREAM,X) print_operand_address ((STREAM), (X))
2453
2454 #define PRINT_OPERAND_PUNCT_VALID_P(CHAR) \
2455 ((CHAR) == '.' || (CHAR) == '#' || (CHAR) == '@' || (CHAR) == ',' \
2456 || (CHAR) == '$' || (CHAR) == '\'' || (CHAR) == '>')
2457
2458 /* Recognize machine-specific patterns that may appear within
2459 constants. Used for PIC-specific UNSPECs. */
2460 #define OUTPUT_ADDR_CONST_EXTRA(STREAM, X, FAIL) \
2461 do \
2462 if (GET_CODE (X) == UNSPEC) \
2463 { \
2464 switch (XINT ((X), 1)) \
2465 { \
2466 case UNSPEC_DATALABEL: \
2467 fputs ("datalabel ", (STREAM)); \
2468 output_addr_const ((STREAM), XVECEXP ((X), 0, 0)); \
2469 break; \
2470 case UNSPEC_PIC: \
2471 /* GLOBAL_OFFSET_TABLE or local symbols, no suffix. */ \
2472 output_addr_const ((STREAM), XVECEXP ((X), 0, 0)); \
2473 break; \
2474 case UNSPEC_GOT: \
2475 output_addr_const ((STREAM), XVECEXP ((X), 0, 0)); \
2476 fputs ("@GOT", (STREAM)); \
2477 break; \
2478 case UNSPEC_GOTOFF: \
2479 output_addr_const ((STREAM), XVECEXP ((X), 0, 0)); \
2480 fputs ("@GOTOFF", (STREAM)); \
2481 break; \
2482 case UNSPEC_PLT: \
2483 output_addr_const ((STREAM), XVECEXP ((X), 0, 0)); \
2484 fputs ("@PLT", (STREAM)); \
2485 break; \
2486 case UNSPEC_GOTPLT: \
2487 output_addr_const ((STREAM), XVECEXP ((X), 0, 0)); \
2488 fputs ("@GOTPLT", (STREAM)); \
2489 break; \
2490 case UNSPEC_DTPOFF: \
2491 output_addr_const ((STREAM), XVECEXP ((X), 0, 0)); \
2492 fputs ("@DTPOFF", (STREAM)); \
2493 break; \
2494 case UNSPEC_GOTTPOFF: \
2495 output_addr_const ((STREAM), XVECEXP ((X), 0, 0)); \
2496 fputs ("@GOTTPOFF", (STREAM)); \
2497 break; \
2498 case UNSPEC_TPOFF: \
2499 output_addr_const ((STREAM), XVECEXP ((X), 0, 0)); \
2500 fputs ("@TPOFF", (STREAM)); \
2501 break; \
2502 case UNSPEC_CALLER: \
2503 { \
2504 char name[32]; \
2505 /* LPCS stands for Label for PIC Call Site. */ \
2506 ASM_GENERATE_INTERNAL_LABEL \
2507 (name, "LPCS", INTVAL (XVECEXP ((X), 0, 0))); \
2508 assemble_name ((STREAM), name); \
2509 } \
2510 break; \
2511 case UNSPEC_EXTRACT_S16: \
2512 case UNSPEC_EXTRACT_U16: \
2513 { \
2514 rtx val, shift; \
2515 \
2516 val = XVECEXP (X, 0, 0); \
2517 shift = XVECEXP (X, 0, 1); \
2518 fputc ('(', STREAM); \
2519 if (shift != const0_rtx) \
2520 fputc ('(', STREAM); \
2521 if (GET_CODE (val) == CONST \
2522 || GET_RTX_CLASS (GET_CODE (val)) != RTX_OBJ) \
2523 { \
2524 fputc ('(', STREAM); \
2525 output_addr_const (STREAM, val); \
2526 fputc (')', STREAM); \
2527 } \
2528 else \
2529 output_addr_const (STREAM, val); \
2530 if (shift != const0_rtx) \
2531 { \
2532 fputs (" >> ", STREAM); \
2533 output_addr_const (STREAM, shift); \
2534 fputc (')', STREAM); \
2535 } \
2536 fputs (" & 65535)", STREAM); \
2537 } \
2538 break; \
2539 case UNSPEC_SYMOFF: \
2540 output_addr_const (STREAM, XVECEXP (X, 0, 0)); \
2541 fputc ('-', STREAM); \
2542 if (GET_CODE (XVECEXP (X, 0, 1)) == CONST) \
2543 { \
2544 fputc ('(', STREAM); \
2545 output_addr_const (STREAM, XVECEXP (X, 0, 1)); \
2546 fputc (')', STREAM); \
2547 } \
2548 else \
2549 output_addr_const (STREAM, XVECEXP (X, 0, 1)); \
2550 break; \
2551 case UNSPEC_PCREL_SYMOFF: \
2552 output_addr_const (STREAM, XVECEXP (X, 0, 0)); \
2553 fputs ("-(", STREAM); \
2554 output_addr_const (STREAM, XVECEXP (X, 0, 1)); \
2555 fputs ("-.)", STREAM); \
2556 break; \
2557 default: \
2558 goto FAIL; \
2559 } \
2560 break; \
2561 } \
2562 else \
2563 goto FAIL; \
2564 while (0)
2565
2566 2340
2567 extern struct rtx_def *sh_compare_op0; 2341 extern struct rtx_def *sh_compare_op0;
2568 extern struct rtx_def *sh_compare_op1; 2342 extern struct rtx_def *sh_compare_op1;
2569 2343
2570 /* Which processor to schedule for. The elements of the enumeration must 2344 /* Which processor to schedule for. The elements of the enumeration must
2583 }; 2357 };
2584 2358
2585 #define sh_cpu_attr ((enum attr_cpu)sh_cpu) 2359 #define sh_cpu_attr ((enum attr_cpu)sh_cpu)
2586 extern enum processor_type sh_cpu; 2360 extern enum processor_type sh_cpu;
2587 2361
2588 extern int optimize; /* needed for gen_casesi. */
2589
2590 enum mdep_reorg_phase_e 2362 enum mdep_reorg_phase_e
2591 { 2363 {
2592 SH_BEFORE_MDEP_REORG, 2364 SH_BEFORE_MDEP_REORG,
2593 SH_INSERT_USES_LABELS, 2365 SH_INSERT_USES_LABELS,
2594 SH_SHORTEN_BRANCHES0, 2366 SH_SHORTEN_BRANCHES0,
2644 /* Better to allocate once the maximum space for outgoing args in the 2416 /* Better to allocate once the maximum space for outgoing args in the
2645 prologue rather than duplicate around each call. */ 2417 prologue rather than duplicate around each call. */
2646 #define ACCUMULATE_OUTGOING_ARGS TARGET_ACCUMULATE_OUTGOING_ARGS 2418 #define ACCUMULATE_OUTGOING_ARGS TARGET_ACCUMULATE_OUTGOING_ARGS
2647 2419
2648 #define SH_DYNAMIC_SHIFT_COST \ 2420 #define SH_DYNAMIC_SHIFT_COST \
2649 (TARGET_HARD_SH4 ? 1 : TARGET_SH3 ? (TARGET_SMALLCODE ? 1 : 2) : 20) 2421 (TARGET_HARD_SH4 ? 1 : TARGET_SH3 ? (optimize_size ? 1 : 2) : 20)
2650 2422
2651 2423
2652 #define NUM_MODES_FOR_MODE_SWITCHING { FP_MODE_NONE } 2424 #define NUM_MODES_FOR_MODE_SWITCHING { FP_MODE_NONE }
2653 2425
2654 #define OPTIMIZE_MODE_SWITCHING(ENTITY) (TARGET_SH4 || TARGET_SH2A_DOUBLE) 2426 #define OPTIMIZE_MODE_SWITCHING(ENTITY) (TARGET_SH4 || TARGET_SH2A_DOUBLE)