--- a/gcc/config/mips/24k.md	Sun Aug 21 07:07:55 2011 +0900
+++ b/gcc/config/mips/24k.md	Fri Oct 27 22:46:09 2017 +0900
@@ -8,7 +8,7 @@
 ;; References:
 ;;   "MIPS32 24K Processor Core Family Software User's Manual, Rev 3.04."
 ;;
-;; Copyright (C) 2005, 2007 Free Software Foundation, Inc.
+;; Copyright (C) 2005-2017 Free Software Foundation, Inc.
 ;;
 ;; This file is part of GCC.
 ;;
@@ -94,13 +94,13 @@
 ;; mfhi, mflo, mflhxu - deliver result to gpr in 5 cycles
 (define_insn_reservation "r24k_int_mfhilo" 5
   (and (eq_attr "cpu" "24kc,24kf2_1,24kf1_1")
-       (eq_attr "type" "mfhilo"))
+       (eq_attr "type" "mfhi,mflo"))
   "r24k_iss+(r24k_mul3a|r24k_mul3b|r24k_mul3c)")
 
 ;; mthi, mtlo, mtlhx - deliver result to hi/lo, thence madd, handled as bypass
 (define_insn_reservation "r24k_int_mthilo" 1
   (and (eq_attr "cpu" "24kc,24kf2_1,24kf1_1")
-       (eq_attr "type" "mthilo"))
+       (eq_attr "type" "mthi,mtlo"))
   "r24k_iss+(r24k_mul3a|r24k_mul3b|r24k_mul3c)")
 
 ;; div - default to 36 cycles for 32bit operands.  Faster for 24bit, 16bit and
@@ -122,18 +122,7 @@
 ;; 6. Store
 (define_insn_reservation "r24k_int_store" 1
   (and (eq_attr "cpu" "24kc,24kf2_1,24kf1_1")
-       (and (eq_attr "type" "store")
-	    (eq_attr "mode" "!unknown")))
-  "r24k_iss+r24k_ixu_arith")
-
-;; 6.1 Special case - matches the cprestore pattern which don't set the mode
-;;     attrib. This avoids being set as r24k_int_store and have it checked
-;;     against store_data_bypass_p, which would then fail because cprestore
-;;     does not have a normal SET pattern.
-(define_insn_reservation "r24k_unknown_store" 1
-  (and (eq_attr "cpu" "24kc,24kf2_1,24kf1_1")
-       (and (eq_attr "type" "store")
-	    (eq_attr "mode" "unknown")))
+       (eq_attr "type" "store"))
   "r24k_iss+r24k_ixu_arith")
 
 
@@ -149,7 +138,7 @@
 ;;    scheduling via log links, but not used here).
 (define_insn_reservation "r24k_int_unknown" 0
   (and (eq_attr "cpu" "24kc,24kf2_1,24kf1_1")
-       (eq_attr "type" "unknown"))
+       (eq_attr "type" "unknown,atomic,syncloop"))
   "r24k_iss")
 
 
@@ -169,7 +158,7 @@
 ;; load->store base: 3 cycles
 ;; load->prefetch:   3 cycles
 (define_bypass 3 "r24k_int_load" "r24k_int_load")
-(define_bypass 3 "r24k_int_load" "r24k_int_store" "!store_data_bypass_p")
+(define_bypass 3 "r24k_int_load" "r24k_int_store" "!mips_store_data_bypass_p")
 (define_bypass 3 "r24k_int_load" "r24k_int_prefetch")
 
 ;; arith->next use :  1 cycles (Default)
@@ -177,14 +166,14 @@
 ;; arith->store base: 2 cycles
 ;; arith->prefetch:   2 cycles
 (define_bypass 2 "r24k_int_arith" "r24k_int_load")
-(define_bypass 2 "r24k_int_arith" "r24k_int_store" "!store_data_bypass_p")
+(define_bypass 2 "r24k_int_arith" "r24k_int_store" "!mips_store_data_bypass_p")
 (define_bypass 2 "r24k_int_arith" "r24k_int_prefetch")
 
 ;; mul3->next use : 5 cycles (default)
 ;; mul3->l/s base : 6 cycles
 ;; mul3->prefetch : 6 cycles
 (define_bypass 6 "r24k_int_mul3" "r24k_int_load")
-(define_bypass 6 "r24k_int_mul3" "r24k_int_store" "!store_data_bypass_p")
+(define_bypass 6 "r24k_int_mul3" "r24k_int_store" "!mips_store_data_bypass_p")
 (define_bypass 6 "r24k_int_mul3" "r24k_int_prefetch")
 
 ;; mul3->madd/msub : 1 cycle
@@ -195,24 +184,121 @@
 ;; mfhilo->prefetch  : 6 cycles
 ;; mthilo->madd/msub : 2 cycle (only for mthi/lo not mfhi/lo)
 (define_bypass 6 "r24k_int_mfhilo" "r24k_int_load")
-(define_bypass 6 "r24k_int_mfhilo" "r24k_int_store" "!store_data_bypass_p")
+(define_bypass 6 "r24k_int_mfhilo" "r24k_int_store"
+  "!mips_store_data_bypass_p")
 (define_bypass 6 "r24k_int_mfhilo" "r24k_int_prefetch")
 (define_bypass 2 "r24k_int_mthilo" "r24k_int_madd")
 
 ;; cop->next use : 3 cycles (Default)
 ;; cop->l/s base : 4 cycles
 ;; (define_bypass 4 "r24k_int_cop" "r24k_int_load")
-;; (define_bypass 4 "r24k_int_cop" "r24k_int_store" "!store_data_bypass_p")
+;; (define_bypass 4 "r24k_int_cop" "r24k_int_store"
+;;   "!mips_store_data_bypass_p")
 
 ;; multi->next use : 1 cycles (Default)
 ;; multi->l/s base : 2 cycles
 ;; multi->prefetch : 2 cycles
 (define_bypass 2 "r24k_int_multi" "r24k_int_load")
-(define_bypass 2 "r24k_int_multi" "r24k_int_store" "!store_data_bypass_p")
+(define_bypass 2 "r24k_int_multi" "r24k_int_store" "!mips_store_data_bypass_p")
 (define_bypass 2 "r24k_int_multi" "r24k_int_prefetch")
 
 
 ;; --------------------------------------------------------------
+;; DSP instructions
+;; --------------------------------------------------------------
+
+;; absq, addq, addsc, addu, addwc, bitrev, cmp, cmpgu, cmpu, insv, modsub,
+;; packrl, pick, preceq, preceu, precequ, precrq, precrqu, raddu, rddsp, repl,
+;; replv, shll, shllv, shra, shrav, shrl, shrlv, subq, subu, wrdsp
+(define_insn_reservation "r24k_dsp_alu" 2
+  (and (eq_attr "cpu" "24kc,24kf2_1,24kf1_1")
+       (eq_attr "type" "dspalu,dspalusat"))
+  "r24k_iss+r24k_ixu_arith")
+
+;; dpaq_s, dpau, dpsq_s, dpsu, maq_s, mulsaq
+(define_insn_reservation "r24k_dsp_mac" 1
+  (and (eq_attr "cpu" "24kc,24kf2_1,24kf1_1")
+       (eq_attr "type" "dspmac"))
+  "r24k_iss+(r24k_mul3a|r24k_mul3b|r24k_mul3c)")
+
+;; dpaq_sa, dpsq_sa, maq_sa
+(define_insn_reservation "r24k_dsp_mac_sat" 1
+  (and (eq_attr "cpu" "24kc,24kf2_1,24kf1_1")
+       (eq_attr "type" "dspmacsat"))
+  "r24k_iss+(r24k_mul3a|r24k_mul3b|r24k_mul3c)")
+
+;; extp, extpdp, extpdpv, extpv, extr, extrv
+(define_insn_reservation "r24k_dsp_acc_ext" 5
+  (and (eq_attr "cpu" "24kc,24kf2_1,24kf1_1")
+       (eq_attr "type" "accext"))
+  "r24k_iss+(r24k_mul3a|r24k_mul3b|r24k_mul3c)")
+
+;; mthlip, shilo, shilov
+(define_insn_reservation "r24k_dsp_acc_mod" 1
+  (and (eq_attr "cpu" "24kc,24kf2_1,24kf1_1")
+       (eq_attr "type" "accmod"))
+  "r24k_iss+(r24k_mul3a|r24k_mul3b|r24k_mul3c)")
+
+
+;; mult/madd->dsp_acc_ext : 4 cycles
+;; mult/madd->dsp_acc_mod : 4 cycles
+(define_bypass 4 "r24k_int_mult" "r24k_dsp_acc_ext")
+(define_bypass 4 "r24k_int_mult" "r24k_dsp_acc_mod")
+
+;; mthilo->dsp_acc_ext : 4 cycles
+;; mthilo->dsp_acc_ext : 4 cycles
+(define_bypass 4 "r24k_int_mthilo" "r24k_dsp_acc_ext")
+(define_bypass 4 "r24k_int_mthilo" "r24k_dsp_acc_mod")
+
+;; dsp_mac->next use    : 1 cycles (default)
+;; dsp_mac->dsp_acc_ext : 4 cycles
+;; dsp_mac->dsp_acc_mod : 4 cycles
+(define_bypass 4 "r24k_dsp_mac" "r24k_dsp_acc_ext")
+(define_bypass 4 "r24k_dsp_mac" "r24k_dsp_acc_mod")
+
+;; dsp_mac_sat->next use    : 1 cycles (default)
+;; dsp_mac_sat->mult/madd   : 2 cycles
+;; dsp_mac_sat->dsp_mac     : 2 cycles
+;; dsp_mac_sat->dsp_mac_sat : 2 cycles
+;; dsp_mac_sat->dsp_acc_ext : 4 cycles
+;; dsp_mac_sat->dsp_acc_mod : 4 cycles
+(define_bypass 2 "r24k_dsp_mac_sat" "r24k_int_mult")
+(define_bypass 2 "r24k_dsp_mac_sat" "r24k_dsp_mac")
+(define_bypass 2 "r24k_dsp_mac_sat" "r24k_dsp_mac_sat")
+(define_bypass 4 "r24k_dsp_mac_sat" "r24k_dsp_acc_ext")
+(define_bypass 4 "r24k_dsp_mac_sat" "r24k_dsp_acc_mod")
+
+;; dsp_acc_ext->next use : 5 cycles (default)
+;; dsp_acc_ext->l/s base : 6 cycles
+;; dsp_acc_ext->prefetch : 6 cycles
+(define_bypass 6 "r24k_dsp_acc_ext" "r24k_int_load")
+(define_bypass 6 "r24k_dsp_acc_ext" "r24k_int_store"
+  "!mips_store_data_bypass_p")
+(define_bypass 6 "r24k_dsp_acc_ext" "r24k_int_prefetch")
+
+;; dsp_acc_mod->next use    : 1 cycles (default)
+;; dsp_acc_mod->mult/madd   : 2 cycles
+;; dsp_acc_mod->dsp_mac     : 2 cycles
+;; dsp_acc_mod->dsp_mac_sat : 2 cycles
+;; dsp_acc_mod->dsp_acc_ext : 4 cycles
+;; dsp_acc_mod->dsp_acc_mod : 4 cycles
+(define_bypass 2 "r24k_dsp_acc_mod" "r24k_int_mult")
+(define_bypass 2 "r24k_dsp_acc_mod" "r24k_dsp_mac")
+(define_bypass 2 "r24k_dsp_acc_mod" "r24k_dsp_mac_sat")
+(define_bypass 4 "r24k_dsp_acc_mod" "r24k_dsp_acc_ext")
+(define_bypass 4 "r24k_dsp_acc_mod" "r24k_dsp_acc_mod")
+
+;; dspalu->next use : 2 cycles (default)
+;; dspalu->l/s base : 3 cycles
+;; dspalu->prefetch : 3 cycles
+;; some pairs of dspalu (addsc/addwc, cmp/pick, wrdsp/insv) : 1 cycle
+(define_bypass 3 "r24k_dsp_alu" "r24k_int_load")
+(define_bypass 3 "r24k_dsp_alu" "r24k_int_store" "!mips_store_data_bypass_p")
+(define_bypass 3 "r24k_dsp_alu" "r24k_int_prefetch")
+(define_bypass 1 "r24k_dsp_alu" "r24k_dsp_alu" "mips_dspalu_bypass_p")
+
+
+;; --------------------------------------------------------------
 ;; Floating Point Instructions
 ;; --------------------------------------------------------------
 
@@ -330,13 +416,14 @@
 ;; r24kf2_1_fcvt_f2i->l/s base : 11 cycles
 ;; r24kf2_1_fcvt_f2i->prefetch : 11 cycles
 (define_bypass 11 "r24kf2_1_fcvt_f2i" "r24k_int_load")
-(define_bypass 11 "r24kf2_1_fcvt_f2i" "r24k_int_store" "!store_data_bypass_p")
+(define_bypass 11 "r24kf2_1_fcvt_f2i" "r24k_int_store"
+  "!mips_store_data_bypass_p")
 (define_bypass 11 "r24kf2_1_fcvt_f2i" "r24k_int_prefetch")
 
 ;; r24kf2_1_fxfer->l/s base : 5 cycles
 ;; r24kf2_1_fxfer->prefetch : 5 cycles
 (define_bypass 5 "r24kf2_1_fxfer" "r24k_int_load")
-(define_bypass 5 "r24kf2_1_fxfer" "r24k_int_store" "!store_data_bypass_p")
+(define_bypass 5 "r24kf2_1_fxfer" "r24k_int_store" "!mips_store_data_bypass_p")
 (define_bypass 5 "r24kf2_1_fxfer" "r24k_int_prefetch")
 
 ;; --------------------------------------------------------------
@@ -446,12 +533,13 @@
 ;; r24kf1_1_fcvt_f2i->l/s base : 6 cycles
 ;; r24kf1_1_fcvt_f2i->prefetch : 6 cycles
 (define_bypass 6 "r24kf1_1_fcvt_f2i" "r24k_int_load")
-(define_bypass 6 "r24kf1_1_fcvt_f2i" "r24k_int_store" "!store_data_bypass_p")
+(define_bypass 6 "r24kf1_1_fcvt_f2i" "r24k_int_store"
+  "!mips_store_data_bypass_p")
 (define_bypass 6 "r24kf1_1_fcvt_f2i" "r24k_int_prefetch")
 
 ;; r24kf1_1_fxfer->l/s base : 3 cycles
 ;; r24kf1_1_fxfer->prefetch : 3 cycles
 (define_bypass 3 "r24kf1_1_fxfer" "r24k_int_load")
-(define_bypass 3 "r24kf1_1_fxfer" "r24k_int_store" "!store_data_bypass_p")
+(define_bypass 3 "r24kf1_1_fxfer" "r24k_int_store" "!mips_store_data_bypass_p")
 (define_bypass 3 "r24kf1_1_fxfer" "r24k_int_prefetch")