--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/gcc/testsuite/gcc.target/powerpc/vec-strir-6.c	Mon May 25 07:50:57 2020 +0900
@@ -0,0 +1,21 @@
+/* { dg-do compile } */
+/* { dg-options "-mdejagnu-cpu=future" } */
+
+#include <altivec.h>
+
+extern void abort (void);
+
+/* Vector string isolate right-justified on array of signed short.  */
+vector signed short
+sirj (vector signed short arg)
+{
+  return vec_strir (arg);
+}
+
+/* Enforce that a single dot-form instruction which is properly biased
+   for the target's endianness implements this built-in.  */
+
+/* { dg-final { scan-assembler-times {\mvstrihr\M} 1 { target { be } } } } */
+/* { dg-final { scan-assembler-times {\mvstrihl} 0 { target { be } } } } */
+/* { dg-final { scan-assembler-times {\mvstrihl\M} 1 { target { le } } } } */
+/* { dg-final { scan-assembler-times {\mvstrihr} 0 { target { le } } } } */