--- a/gcc/config/s390/2084.md	Sun Feb 07 18:28:00 2010 +0900
+++ b/gcc/config/s390/2084.md	Fri Feb 12 23:39:51 2010 +0900
@@ -76,38 +76,38 @@
 (define_insn_reservation "x_lr" 1
   (and (eq_attr "cpu" "z990,z9_109")
        (eq_attr "type" "lr"))
-  "x-e1-st,x-wr-st") 
+  "x-e1-st,x-wr-st")
 
-(define_insn_reservation "x_la" 1 
+(define_insn_reservation "x_la" 1
   (and (eq_attr "cpu" "z990,z9_109")
        (eq_attr "type" "la"))
-  "x-e1-st,x-wr-st") 
+  "x-e1-st,x-wr-st")
 
-(define_insn_reservation "x_larl" 1 
+(define_insn_reservation "x_larl" 1
   (and (eq_attr "cpu" "z990,z9_109")
        (eq_attr "type" "larl"))
-  "x-e1-st,x-wr-st") 
+  "x-e1-st,x-wr-st")
 
-(define_insn_reservation "x_load" 1 
+(define_insn_reservation "x_load" 1
   (and (eq_attr "cpu" "z990,z9_109")
        (eq_attr "type" "load"))
-  "x-e1-st+x-mem,x-wr-st") 
+  "x-e1-st+x-mem,x-wr-st")
 
-(define_insn_reservation "x_store" 1 
+(define_insn_reservation "x_store" 1
   (and (eq_attr "cpu" "z990,z9_109")
        (eq_attr "type" "store"))
-  "x-e1-st+x_store_tok,x-wr-st") 
+  "x-e1-st+x_store_tok,x-wr-st")
 
-(define_insn_reservation "x_branch" 1 
+(define_insn_reservation "x_branch" 1
   (and (eq_attr "cpu" "z990,z9_109")
        (eq_attr "type" "branch"))
-  "x_e1_r,x_wr_r") 
+  "x_e1_r,x_wr_r")
 
-(define_insn_reservation "x_call" 5 
+(define_insn_reservation "x_call" 5
   (and (eq_attr "cpu" "z990,z9_109")
        (eq_attr "type" "jsr"))
   "x-e1-np*5,x-wr-np")
- 
+
 (define_insn_reservation "x_mul_hi" 2
   (and (eq_attr "cpu" "z990,z9_109")
        (eq_attr "type" "imulhi"))
@@ -123,162 +123,162 @@
        (eq_attr "type" "idiv"))
   "x-e1-np*10,x-wr-np")
 
-(define_insn_reservation "x_sem" 17 
+(define_insn_reservation "x_sem" 17
   (and (eq_attr "cpu" "z990,z9_109")
        (eq_attr "type" "sem"))
-  "x-e1-np+x-mem,x-e1-np*16,x-wr-st") 
+  "x-e1-np+x-mem,x-e1-np*16,x-wr-st")
 
 ;;
 ;; Multicycle insns
 ;;
 
-(define_insn_reservation "x_cs" 1 
+(define_insn_reservation "x_cs" 1
   (and (eq_attr "cpu" "z990,z9_109")
        (eq_attr "type" "cs"))
-  "x-e1-np,x-wr-np") 
+  "x-e1-np,x-wr-np")
 
-(define_insn_reservation "x_vs" 1 
+(define_insn_reservation "x_vs" 1
   (and (eq_attr "cpu" "z990,z9_109")
        (eq_attr "type" "vs"))
-  "x-e1-np*10,x-wr-np") 
+  "x-e1-np*10,x-wr-np")
 
-(define_insn_reservation "x_stm" 1 
+(define_insn_reservation "x_stm" 1
   (and (eq_attr "cpu" "z990,z9_109")
        (eq_attr "type" "stm"))
-  "(x-e1-np+x_store_tok)*10,x-wr-np") 
+  "(x-e1-np+x_store_tok)*10,x-wr-np")
 
-(define_insn_reservation "x_lm" 1 
+(define_insn_reservation "x_lm" 1
   (and (eq_attr "cpu" "z990,z9_109")
        (eq_attr "type" "lm"))
-  "x-e1-np*10,x-wr-np") 
+  "x-e1-np*10,x-wr-np")
 
-(define_insn_reservation "x_other" 1 
+(define_insn_reservation "x_other" 1
   (and (eq_attr "cpu" "z990,z9_109")
        (eq_attr "type" "other"))
-  "x-e1-np,x-wr-np") 
+  "x-e1-np,x-wr-np")
 
 ;;
 ;; Floating point insns
 ;;
 
-(define_insn_reservation "x_fsimptf" 7 
+(define_insn_reservation "x_fsimptf" 7
   (and (eq_attr "cpu" "z990,z9_109")
        (eq_attr "type" "fsimptf,fhex"))
-  "x_e1_t*2,x-wr-fp") 
+  "x_e1_t*2,x-wr-fp")
 
-(define_insn_reservation "x_fsimpdf" 6 
+(define_insn_reservation "x_fsimpdf" 6
   (and (eq_attr "cpu" "z990,z9_109")
        (eq_attr "type" "fsimpdf,fmuldf,fhex"))
-  "x_e1_t,x-wr-fp") 
+  "x_e1_t,x-wr-fp")
 
-(define_insn_reservation "x_fsimpsf" 6 
+(define_insn_reservation "x_fsimpsf" 6
   (and (eq_attr "cpu" "z990,z9_109")
        (eq_attr "type" "fsimpsf,fmulsf,fhex"))
-  "x_e1_t,x-wr-fp") 
+  "x_e1_t,x-wr-fp")
 
 
 (define_insn_reservation "x_fmultf" 33
   (and (eq_attr "cpu" "z990,z9_109")
        (eq_attr "type" "fmultf"))
-  "x_e1_t*27,x-wr-fp") 
+  "x_e1_t*27,x-wr-fp")
 
 
 (define_insn_reservation "x_fdivtf" 82
   (and (eq_attr "cpu" "z990,z9_109")
        (eq_attr "type" "fdivtf,fsqrttf"))
-  "x_e1_t*76,x-wr-fp") 
+  "x_e1_t*76,x-wr-fp")
 
 (define_insn_reservation "x_fdivdf" 36
   (and (eq_attr "cpu" "z990,z9_109")
        (eq_attr "type" "fdivdf,fsqrtdf"))
-  "x_e1_t*30,x-wr-fp") 
+  "x_e1_t*30,x-wr-fp")
 
-(define_insn_reservation "x_fdivsf" 36 
+(define_insn_reservation "x_fdivsf" 36
   (and (eq_attr "cpu" "z990,z9_109")
        (eq_attr "type" "fdivsf,fsqrtsf"))
-  "x_e1_t*30,x-wr-fp") 
+  "x_e1_t*30,x-wr-fp")
 
 
-(define_insn_reservation "x_floadtf" 6 
+(define_insn_reservation "x_floadtf" 6
   (and (eq_attr "cpu" "z990,z9_109")
        (eq_attr "type" "floadtf"))
-  "x_e1_t,x-wr-fp") 
+  "x_e1_t,x-wr-fp")
 
-(define_insn_reservation "x_floaddf" 6 
+(define_insn_reservation "x_floaddf" 6
   (and (eq_attr "cpu" "z990,z9_109")
        (eq_attr "type" "floaddf"))
-  "x_e1_t,x-wr-fp") 
+  "x_e1_t,x-wr-fp")
 
-(define_insn_reservation "x_floadsf" 6 
+(define_insn_reservation "x_floadsf" 6
   (and (eq_attr "cpu" "z990,z9_109")
        (eq_attr "type" "floadsf"))
-  "x_e1_t,x-wr-fp") 
+  "x_e1_t,x-wr-fp")
 
 
-(define_insn_reservation "x_fstoredf" 1 
+(define_insn_reservation "x_fstoredf" 1
   (and (eq_attr "cpu" "z990,z9_109")
        (eq_attr "type" "fstoredf"))
-  "x_e1_t,x-wr-fp") 
+  "x_e1_t,x-wr-fp")
 
-(define_insn_reservation "x_fstoresf" 1 
+(define_insn_reservation "x_fstoresf" 1
   (and (eq_attr "cpu" "z990,z9_109")
        (eq_attr "type" "fstoresf"))
-  "x_e1_t,x-wr-fp") 
+  "x_e1_t,x-wr-fp")
 
 
 (define_insn_reservation "x_ftrunctf" 16
   (and (eq_attr "cpu" "z990,z9_109")
        (eq_attr "type" "ftrunctf"))
-  "x_e1_t*10,x-wr-fp") 
+  "x_e1_t*10,x-wr-fp")
 
 (define_insn_reservation "x_ftruncdf" 11
   (and (eq_attr "cpu" "z990,z9_109")
        (eq_attr "type" "ftruncdf"))
-  "x_e1_t*5,x-wr-fp") 
+  "x_e1_t*5,x-wr-fp")
 
 
-(define_insn_reservation "x_ftoi" 1 
+(define_insn_reservation "x_ftoi" 1
   (and (eq_attr "cpu" "z990,z9_109")
        (eq_attr "type" "ftoi"))
-  "x_e1_t*3,x-wr-fp") 
+  "x_e1_t*3,x-wr-fp")
 
-(define_insn_reservation "x_itof" 7 
+(define_insn_reservation "x_itof" 7
   (and (eq_attr "cpu" "z990,z9_109")
        (eq_attr "type" "itoftf,itofdf,itofsf"))
-  "x_e1_t*3,x-wr-fp") 
+  "x_e1_t*3,x-wr-fp")
 
 (define_bypass 1 "x_fsimpdf" "x_fstoredf")
 
 (define_bypass 1 "x_fsimpsf" "x_fstoresf")
 
 (define_bypass 1 "x_floaddf" "x_fsimpdf,x_fstoredf,x_floaddf")
-	         
+
 (define_bypass 1 "x_floadsf" "x_fsimpsf,x_fstoresf,x_floadsf")
 
 ;;
-;; s390_agen_dep_p returns 1, if a register is set in the 
+;; s390_agen_dep_p returns 1, if a register is set in the
 ;; first insn and used in the dependent insn to form a address.
 ;;
 
 ;;
 ;; If an instruction uses a register to address memory, it needs
 ;; to be set 5 cycles in advance.
-;; 
+;;
 
-(define_bypass 5 "x_int,x_agen,x_lr" 
+(define_bypass 5 "x_int,x_agen,x_lr"
                  "x_agen,x_la,x_branch,x_call,x_load,x_store,x_cs,x_stm,x_lm,x_other"
 	         "s390_agen_dep_p")
 
-(define_bypass 9 "x_int,x_agen,x_lr" 
+(define_bypass 9 "x_int,x_agen,x_lr"
                  "x_floadtf, x_floaddf, x_floadsf, x_fstoredf, x_fstoresf,\
 		  x_fsimpdf, x_fsimpsf, x_fdivdf, x_fdivsf"
 	         "s390_agen_dep_p")
 ;;
-;; A load type instruction uses a bypass to feed the result back	
-;; to the address generation pipeline stage. 
+;; A load type instruction uses a bypass to feed the result back
+;; to the address generation pipeline stage.
 ;;
 
-(define_bypass 4 "x_load"    
+(define_bypass 4 "x_load"
                  "x_agen,x_la,x_branch,x_call,x_load,x_store,x_cs,x_stm,x_lm,x_other"
 	         "s390_agen_dep_p")
 
@@ -288,11 +288,11 @@
 	         "s390_agen_dep_p")
 
 ;;
-;; A load address type instruction uses a bypass to feed the 
-;; result back to the address generation pipeline stage. 
+;; A load address type instruction uses a bypass to feed the
+;; result back to the address generation pipeline stage.
 ;;
 
-(define_bypass 3 "x_larl,x_la" 
+(define_bypass 3 "x_larl,x_la"
                  "x_agen,x_la,x_branch,x_call,x_load,x_store,x_cs,x_stm,x_lm,x_other"
 	         "s390_agen_dep_p")