--- a/gcc/config/arc/arcHS.md	Fri Oct 27 22:46:09 2017 +0900
+++ b/gcc/config/arc/arcHS.md	Thu Oct 25 07:37:49 2018 +0900
@@ -1,6 +1,6 @@
 ;; DFA scheduling description of the Synopsys DesignWare ARC HS cpu
 ;; for GNU C compiler
-;; Copyright (C) 2007-2017 Free Software Foundation, Inc.
+;; Copyright (C) 2007-2018 Free Software Foundation, Inc.
 ;; Contributor: Claudiu Zissulescu <claudiu.zissulescu@synopsys.com>
 
 ;; This file is part of GCC.
@@ -25,42 +25,57 @@
 
 (define_insn_reservation "hs_data_load" 4
   (and (match_test "TARGET_HS")
+       (eq_attr "tune" "none")
        (eq_attr "type" "load"))
   "hs_issue+hs_ld_st,hs_ld_st,nothing*2")
 
 (define_insn_reservation "hs_data_store" 1
   (and (match_test "TARGET_HS")
+       (eq_attr "tune" "none")
        (eq_attr "type" "store"))
   "hs_issue+hs_ld_st")
 
-(define_insn_reservation "hs_alu0" 2
+;; Advanced ALU
+(define_insn_reservation "hs_alu0" 4
   (and (match_test "TARGET_HS")
+       (eq_attr "tune" "none")
        (eq_attr "type" "cc_arith, two_cycle_core, shift, lr, sr"))
-  "hs_issue+x1,x2")
+  "hs_issue+x1,x2, nothing*2")
 
+;; Basic ALU
 (define_insn_reservation "hs_alu1" 4
   (and (match_test "TARGET_HS")
+       (eq_attr "tune" "none")
        (eq_attr "type" "move, cmove, unary, binary, compare, misc"))
   "hs_issue+x1, nothing*3")
 
 (define_insn_reservation "hs_divrem" 13
   (and (match_test "TARGET_HS")
        (match_test "TARGET_DIVREM")
+       (eq_attr "tune" "none")
        (eq_attr "type" "div_rem"))
   "hs_issue+divrem_hs, (divrem_hs)*12")
 
-(define_insn_reservation "hs_mul" 3
+(define_insn_reservation "hs_mul" 4
   (and (match_test "TARGET_HS")
+       (eq_attr "tune" "none")
        (eq_attr "type" "mul16_em, multi, umulti"))
   "hs_issue+mul_hs, nothing*3")
 
-;; BYPASS EALU ->
+;; BYPASS Advanced ALU ->
 (define_bypass 1 "hs_alu0" "hs_divrem")
 (define_bypass 1 "hs_alu0" "hs_mul")
+(define_bypass 2 "hs_alu0" "hs_alu0")
+(define_bypass 1 "hs_alu0" "hs_alu1")
+(define_bypass 1 "hs_alu0" "hs_data_load")
+(define_bypass 1 "hs_alu0" "hs_data_store" "store_data_bypass_p")
+(define_bypass 2 "hs_alu0" "hs_data_store")
 
-;; BYPASS BALU ->
+;; BYPASS Basic ALU ->
 (define_bypass 1 "hs_alu1" "hs_alu1")
 (define_bypass 1 "hs_alu1" "hs_data_store" "store_data_bypass_p")
+(define_bypass 3 "hs_alu1" "hs_mul")
+(define_bypass 3 "hs_alu1" "hs_divrem")
 
 ;; BYPASS LD ->
 (define_bypass 1 "hs_data_load" "hs_alu1")
@@ -70,7 +85,7 @@
 (define_bypass 1 "hs_data_load" "hs_data_store" "store_data_bypass_p")
 
 ;; BYPASS MPY ->
-;;(define_bypass 3 "hs_mul" "hs_mul")
+(define_bypass 3 "hs_mul" "hs_mul")
 (define_bypass 1 "hs_mul" "hs_alu1")
 (define_bypass 3 "hs_mul" "hs_divrem")
 (define_bypass 1 "hs_mul" "hs_data_store" "store_data_bypass_p")