--- a/gcc/config/s390/s390.md	Thu Sep 24 13:21:57 2009 +0900
+++ b/gcc/config/s390/s390.md	Tue Dec 22 21:19:31 2009 +0900
@@ -202,7 +202,7 @@
 (define_attr "type" "none,integer,load,lr,la,larl,lm,stm,
 	             cs,vs,store,sem,idiv,
                      imulhi,imulsi,imuldi,
-		     branch,jsr,fsimptf,fsimpdf,fsimpsf,
+		     branch,jsr,fsimptf,fsimpdf,fsimpsf,fhex,
 		     floadtf,floaddf,floadsf,fstoredf,fstoresf,
 		     fmultf,fmuldf,fmulsf,fdivtf,fdivdf,fdivsf,
 		     ftoi,fsqrttf,fsqrtdf,fsqrtsf,
@@ -1076,6 +1076,64 @@
                       (const_int 6) (const_int 12)))]) ; 8 byte for clr/jg
                                                        ; 10 byte for clgr/jg
 
+; And now the same two patterns as above but with a negated CC mask.
+
+; cij, cgij, crj, cgrj, cfi, cgfi, cr, cgr
+; The following instructions do a complementary access of their second
+; operand (z01 only): crj_c, cgrjc, cr, cgr
+(define_insn "*icmp_and_br_signed_<mode>"
+  [(set (pc)
+	(if_then_else (match_operator 0 "s390_signed_integer_comparison"
+			[(match_operand:GPR 1 "register_operand"  "d,d")
+			 (match_operand:GPR 2 "nonmemory_operand" "d,C")])
+		      (pc)
+		      (label_ref (match_operand 3 "" ""))))
+   (clobber (reg:CC CC_REGNUM))]
+  "TARGET_Z10"
+{
+  if (get_attr_length (insn) == 6)
+    return which_alternative ?
+      "c<g>ij%D0\t%1,%c2,%l3" : "c<g>rj%D0\t%1,%2,%l3";
+  else
+    return which_alternative ?
+      "c<g>fi\t%1,%c2\;jg%D0\t%l3" : "c<g>r\t%1,%2\;jg%D0\t%l3";
+}
+  [(set_attr "op_type" "RIE")
+   (set_attr "type"    "branch")
+   (set_attr "z10prop" "z10_super_c,z10_super")
+   (set (attr "length")
+        (if_then_else (lt (abs (minus (pc) (match_dup 3))) (const_int 60000))
+                      (const_int 6) (const_int 12)))]) ; 8 byte for cr/jg
+                                                       ; 10 byte for cgr/jg
+
+; clij, clgij, clrj, clgrj, clfi, clgfi, clr, clgr
+; The following instructions do a complementary access of their second
+; operand (z10 only): clrj, clgrj, clr, clgr
+(define_insn "*icmp_and_br_unsigned_<mode>"
+  [(set (pc)
+	(if_then_else (match_operator 0 "s390_unsigned_integer_comparison"
+			[(match_operand:GPR 1 "register_operand"  "d,d")
+			 (match_operand:GPR 2 "nonmemory_operand" "d,I")])
+		      (pc)
+		      (label_ref (match_operand 3 "" ""))))
+   (clobber (reg:CC CC_REGNUM))]
+  "TARGET_Z10"
+{
+  if (get_attr_length (insn) == 6)
+    return which_alternative ?
+      "cl<g>ij%D0\t%1,%b2,%l3" : "cl<g>rj%D0\t%1,%2,%l3";
+  else
+    return which_alternative ?
+      "cl<g>fi\t%1,%b2\;jg%D0\t%l3" : "cl<g>r\t%1,%2\;jg%D0\t%l3";
+}
+  [(set_attr "op_type" "RIE")
+   (set_attr "type"    "branch")
+   (set_attr "z10prop" "z10_super_c,z10_super")
+   (set (attr "length")
+        (if_then_else (lt (abs (minus (pc) (match_dup 3))) (const_int 60000))
+                      (const_int 6) (const_int 12)))]) ; 8 byte for clr/jg
+                                                       ; 10 byte for clgr/jg
+
 ;;
 ;;- Move instructions.
 ;;
@@ -1470,7 +1528,7 @@
 
 (define_insn "*la_64"
   [(set (match_operand:DI 0 "register_operand" "=d,d")
-        (match_operand:QI 1 "address_operand" "U,W"))]
+        (match_operand:QI 1 "address_operand" "ZQZR,ZSZT"))]
   "TARGET_64BIT"
   "@
    la\t%0,%a1
@@ -1653,7 +1711,7 @@
 
 (define_insn "*la_31"
   [(set (match_operand:SI 0 "register_operand" "=d,d")
-        (match_operand:QI 1 "address_operand" "U,W"))]
+        (match_operand:QI 1 "address_operand" "ZQZR,ZSZT"))]
   "!TARGET_64BIT && legitimate_la_operand_p (operands[1])"
   "@
    la\t%0,%a1
@@ -1688,7 +1746,7 @@
 
 (define_insn "*la_31_and"
   [(set (match_operand:SI 0 "register_operand" "=d,d")
-        (and:SI (match_operand:QI 1 "address_operand" "U,W")
+        (and:SI (match_operand:QI 1 "address_operand" "ZQZR,ZSZT")
                 (const_int 2147483647)))]
   "!TARGET_64BIT"
   "@
@@ -1714,7 +1772,7 @@
 
 (define_insn "force_la_31"
   [(set (match_operand:SI 0 "register_operand" "=d,d")
-        (match_operand:QI 1 "address_operand" "U,W"))
+        (match_operand:QI 1 "address_operand" "ZQZR,ZSZT"))
    (use (const_int 0))]
   "!TARGET_64BIT"
   "@
@@ -1909,7 +1967,7 @@
    #
    #"
   [(set_attr "op_type" "RRE,RRE,*,*,RSY,RSY,*,*")
-   (set_attr "type"    "fsimptf,fsimptf,*,*,lm,stm,*,*")])
+   (set_attr "type"    "fhex,fsimptf,*,*,lm,stm,*,*")])
 
 (define_insn "*mov<mode>_31"
   [(set (match_operand:TD_TF 0 "nonimmediate_operand" "=f,f,f,o")
@@ -1921,7 +1979,7 @@
    #
    #"
   [(set_attr "op_type" "RRE,RRE,*,*")
-   (set_attr "type"    "fsimptf,fsimptf,*,*")])
+   (set_attr "type"    "fhex,fsimptf,*,*")])
 
 ; TFmode in GPRs splitters
 
@@ -2029,7 +2087,7 @@
    lg\t%0,%1
    stg\t%1,%0"
   [(set_attr "op_type" "RRE,RR,RRE,RRE,RX,RXY,RX,RXY,RRE,RXY,RXY")
-   (set_attr "type" "fsimpdf,floaddf,floaddf,floaddf,floaddf,floaddf,
+   (set_attr "type" "fhex,floaddf,floaddf,floaddf,floaddf,floaddf,
                      fstoredf,fstoredf,lr,load,store")
    (set_attr "z10prop" "*,
                         *,
@@ -2059,7 +2117,7 @@
    lg\t%0,%1
    stg\t%1,%0"
   [(set_attr "op_type" "RRE,RR,RX,RXY,RX,RXY,RRE,RXY,RXY")
-   (set_attr "type" "fsimp<mode>,fload<mode>,fload<mode>,fload<mode>,
+   (set_attr "type" "fhex,fload<mode>,fload<mode>,fload<mode>,
                      fstore<mode>,fstore<mode>,lr,load,store")
    (set_attr "z10prop" "*,
                         *,
@@ -2091,7 +2149,7 @@
    #
    #"
   [(set_attr "op_type" "RRE,RR,RX,RXY,RX,RXY,RS,RSY,RS,RSY,*,*")
-   (set_attr "type" "fsimp<mode>,fload<mode>,fload<mode>,fload<mode>,
+   (set_attr "type" "fhex,fload<mode>,fload<mode>,fload<mode>,
                      fstore<mode>,fstore<mode>,lm,lm,stm,stm,*,*")])
 
 (define_split
@@ -2158,7 +2216,7 @@
    st\t%1,%0
    sty\t%1,%0"
   [(set_attr "op_type" "RRE,RR,RX,RXY,RX,RXY,RR,RX,RXY,RX,RXY")
-   (set_attr "type" "fsimp<mode>,fload<mode>,fload<mode>,fload<mode>,
+   (set_attr "type" "fhex,fload<mode>,fload<mode>,fload<mode>,
                      fstore<mode>,fstore<mode>,lr,load,load,store,store")
    (set_attr "z10prop" "*,
                         *,
@@ -7407,7 +7465,7 @@
   [(set (pc)
         (if_then_else
           (match_operator 1 "s390_comparison" [(reg CC_REGNUM) (const_int 0)])
-          (match_operand 0 "address_operand" "U")
+          (match_operand 0 "address_operand" "ZQZR")
           (pc)))]
   ""
 {
@@ -7471,7 +7529,7 @@
         (if_then_else
           (match_operator 1 "s390_comparison" [(reg CC_REGNUM) (const_int 0)])
           (pc)
-          (match_operand 0 "address_operand" "U")))]
+          (match_operand 0 "address_operand" "ZQZR")))]
   ""
 {
   if (get_attr_op_type (insn) == OP_TYPE_RR)
@@ -7660,7 +7718,7 @@
         (if_then_else
           (ne (match_operand:SI 1 "register_operand" "d")
               (const_int 1))
-          (match_operand 0 "address_operand" "U")
+          (match_operand 0 "address_operand" "ZQZR")
           (pc)))
    (set (match_operand:SI 2 "register_operand" "=1")
         (plus:SI (match_dup 1) (const_int -1)))
@@ -7771,7 +7829,7 @@
 ;
 
 (define_insn "indirect_jump"
- [(set (pc) (match_operand 0 "address_operand" "U"))]
+ [(set (pc) (match_operand 0 "address_operand" "ZQZR"))]
   ""
 {
   if (get_attr_op_type (insn) == OP_TYPE_RR)
@@ -7790,7 +7848,7 @@
 ;
 
 (define_insn "casesi_jump"
- [(set (pc) (match_operand 0 "address_operand" "U"))
+ [(set (pc) (match_operand 0 "address_operand" "ZQZR"))
    (use (label_ref (match_operand 1 "" "")))]
   ""
 {
@@ -8012,7 +8070,7 @@
    (set_attr "type"    "jsr")])
 
 (define_insn "*basr"
-  [(call (mem:QI (match_operand 0 "address_operand" "U"))
+  [(call (mem:QI (match_operand 0 "address_operand" "ZQZR"))
          (match_operand 1 "const_int_operand" "n"))
    (clobber (match_operand 2 "register_operand" "=r"))]
   "!SIBLING_CALL_P (insn) && GET_MODE (operands[2]) == Pmode"
@@ -8070,7 +8128,7 @@
 
 (define_insn "*basr_r"
   [(set (match_operand 0 "" "")
-        (call (mem:QI (match_operand 1 "address_operand" "U"))
+        (call (mem:QI (match_operand 1 "address_operand" "ZQZR"))
               (match_operand 2 "const_int_operand" "n")))
    (clobber (match_operand 3 "register_operand" "=r"))]
   "!SIBLING_CALL_P (insn) && GET_MODE (operands[3]) == Pmode"
@@ -8170,7 +8228,7 @@
 
 (define_insn "*basr_tls"
   [(set (match_operand 0 "" "")
-        (call (mem:QI (match_operand 1 "address_operand" "U"))
+        (call (mem:QI (match_operand 1 "address_operand" "ZQZR"))
               (match_operand 2 "const_int_operand" "n")))
    (clobber (match_operand 3 "register_operand" "=r"))
    (use (match_operand 4 "" ""))]
@@ -8720,23 +8778,25 @@
 ;
 
 (define_insn "prefetch"
-  [(prefetch (match_operand 0 "address_operand" "UW,X")
-	     (match_operand:SI 1 "const_int_operand" "n,n")
-	     (match_operand:SI 2 "const_int_operand" "n,n"))]
+  [(prefetch (match_operand 0    "address_operand"   "ZQZRZSZT,X")
+	     (match_operand:SI 1 "const_int_operand" "       n,n")
+	     (match_operand:SI 2 "const_int_operand" "       n,n"))]
   "TARGET_Z10"
 {
-  if (larl_operand (operands[0], Pmode))
-    return INTVAL (operands[1]) == 1 ? "pfdrl\t2,%a0" : "pfdrl\t1,%a0";
-
-  if (s390_mem_constraint ("W", operands[0])
-      || s390_mem_constraint ("U", operands[0]))
-    return INTVAL (operands[1]) == 1 ? "pfd\t2,%a0" : "pfd\t1,%a0";
-
-  /* This point might be reached if op0 is a larl operand with an
-     uneven addend.  In this case we simply omit issuing a prefetch
-     instruction.  */
-
-  return "";
+  switch (which_alternative)
+    {
+      case 0:
+        return INTVAL (operands[1]) == 1 ? "pfd\t2,%a0" : "pfd\t1,%a0";
+      case 1:
+        if (larl_operand (operands[0], Pmode))
+	  return INTVAL (operands[1]) == 1 ? "pfdrl\t2,%a0" : "pfdrl\t1,%a0";
+      default:
+
+        /* This might be reached for symbolic operands with an odd
+           addend.  We simply omit the prefetch for such rare cases.  */
+
+        return "";
+     }
 }
   [(set_attr "type" "load,larl")
    (set_attr "op_type" "RXY,RIL")