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diff gcc/config/s390/2097.md @ 67:f6334be47118

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update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
author nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
date Tue, 22 Mar 2011 17:18:12 +0900
parents 3bfb6c00c1e0
children 04ced10e8804
line wrap: on
line diff
--- a/gcc/config/s390/2097.md	Tue May 25 18:58:51 2010 +0900
+++ b/gcc/config/s390/2097.md	Tue Mar 22 17:18:12 2011 +0900
@@ -1,5 +1,5 @@
 ;; Scheduling description for z10 (cpu 2097).
-;; Copyright (C) 2008 Free Software Foundation, Inc.
+;; Copyright (C) 2008, 2010 Free Software Foundation, Inc.
 ;; Contributed by Wolfgang Gellerich (gellerich@de.ibm.com).
 
 
@@ -463,21 +463,12 @@
 
 (define_insn_reservation "z10_fsimpdf" 6
   (and (eq_attr "cpu" "z10")
-       (eq_attr "type" "fsimpdf,fmuldf"))
-  "z10_e1_BOTH, z10_Gate_FP")
-
-; LOAD ZERO produces a hex value but we need bin. Using the stage 7
-; bypass causes an exception for format conversion which is very
-; expensive. So, make sure subsequent instructions only get the zero
-; in the normal way.
-(define_insn_reservation "z10_fhex" 12
-  (and (eq_attr "cpu" "z10")
-       (eq_attr "type" "fhex"))
+       (eq_attr "type" "fsimpdf,fmuldf,fmadddf"))
   "z10_e1_BOTH, z10_Gate_FP")
 
 (define_insn_reservation "z10_fsimpsf" 6
   (and (eq_attr "cpu" "z10")
-       (eq_attr "type" "fsimpsf,fmulsf"))
+       (eq_attr "type" "fsimpsf,fmulsf,fmaddsf"))
   "z10_e1_BOTH, z10_Gate_FP")
 
 (define_insn_reservation "z10_fmultf" 52