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1 //===- TargetPassConfig.cpp - Target independent code generation passes ---===//
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2 //
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3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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4 // See https://llvm.org/LICENSE.txt for license information.
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5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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6 //
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7 //===----------------------------------------------------------------------===//
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8 //
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9 // This file defines interfaces to access the target independent code
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10 // generation passes provided by the LLVM backend.
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11 //
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12 //===---------------------------------------------------------------------===//
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13
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14 #include "llvm/CodeGen/TargetPassConfig.h"
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15 #include "llvm/ADT/DenseMap.h"
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16 #include "llvm/ADT/SmallVector.h"
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17 #include "llvm/ADT/StringRef.h"
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18 #include "llvm/Analysis/BasicAliasAnalysis.h"
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19 #include "llvm/Analysis/CFLAndersAliasAnalysis.h"
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20 #include "llvm/Analysis/CFLSteensAliasAnalysis.h"
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21 #include "llvm/Analysis/CallGraphSCCPass.h"
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22 #include "llvm/Analysis/ScopedNoAliasAA.h"
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23 #include "llvm/Analysis/TargetTransformInfo.h"
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24 #include "llvm/Analysis/TypeBasedAliasAnalysis.h"
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25 #include "llvm/CodeGen/CSEConfigBase.h"
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26 #include "llvm/CodeGen/MachineFunctionPass.h"
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27 #include "llvm/CodeGen/MachinePassRegistry.h"
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28 #include "llvm/CodeGen/Passes.h"
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29 #include "llvm/CodeGen/RegAllocRegistry.h"
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30 #include "llvm/IR/IRPrintingPasses.h"
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31 #include "llvm/IR/LegacyPassManager.h"
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32 #include "llvm/IR/Verifier.h"
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33 #include "llvm/InitializePasses.h"
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34 #include "llvm/MC/MCAsmInfo.h"
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35 #include "llvm/MC/MCTargetOptions.h"
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36 #include "llvm/Pass.h"
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37 #include "llvm/Support/CodeGen.h"
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38 #include "llvm/Support/CommandLine.h"
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39 #include "llvm/Support/Compiler.h"
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40 #include "llvm/Support/Debug.h"
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41 #include "llvm/Support/ErrorHandling.h"
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42 #include "llvm/Support/SaveAndRestore.h"
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43 #include "llvm/Support/Threading.h"
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44 #include "llvm/Target/TargetMachine.h"
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45 #include "llvm/Transforms/Scalar.h"
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46 #include "llvm/Transforms/Utils.h"
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47 #include "llvm/Transforms/Utils/SymbolRewriter.h"
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48 #include <cassert>
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49 #include <string>
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50
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51 using namespace llvm;
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52
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53 static cl::opt<bool>
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54 EnableIPRA("enable-ipra", cl::init(false), cl::Hidden,
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55 cl::desc("Enable interprocedural register allocation "
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56 "to reduce load/store at procedure calls."));
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57 static cl::opt<bool> DisablePostRASched("disable-post-ra", cl::Hidden,
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58 cl::desc("Disable Post Regalloc Scheduler"));
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59 static cl::opt<bool> DisableBranchFold("disable-branch-fold", cl::Hidden,
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60 cl::desc("Disable branch folding"));
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61 static cl::opt<bool> DisableTailDuplicate("disable-tail-duplicate", cl::Hidden,
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62 cl::desc("Disable tail duplication"));
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63 static cl::opt<bool> DisableEarlyTailDup("disable-early-taildup", cl::Hidden,
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64 cl::desc("Disable pre-register allocation tail duplication"));
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65 static cl::opt<bool> DisableBlockPlacement("disable-block-placement",
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66 cl::Hidden, cl::desc("Disable probability-driven block placement"));
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67 static cl::opt<bool> EnableBlockPlacementStats("enable-block-placement-stats",
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68 cl::Hidden, cl::desc("Collect probability-driven block placement stats"));
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69 static cl::opt<bool> DisableSSC("disable-ssc", cl::Hidden,
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70 cl::desc("Disable Stack Slot Coloring"));
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71 static cl::opt<bool> DisableMachineDCE("disable-machine-dce", cl::Hidden,
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72 cl::desc("Disable Machine Dead Code Elimination"));
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73 static cl::opt<bool> DisableEarlyIfConversion("disable-early-ifcvt", cl::Hidden,
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74 cl::desc("Disable Early If-conversion"));
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75 static cl::opt<bool> DisableMachineLICM("disable-machine-licm", cl::Hidden,
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76 cl::desc("Disable Machine LICM"));
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77 static cl::opt<bool> DisableMachineCSE("disable-machine-cse", cl::Hidden,
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78 cl::desc("Disable Machine Common Subexpression Elimination"));
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79 static cl::opt<cl::boolOrDefault> OptimizeRegAlloc(
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80 "optimize-regalloc", cl::Hidden,
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81 cl::desc("Enable optimized register allocation compilation path."));
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82 static cl::opt<bool> DisablePostRAMachineLICM("disable-postra-machine-licm",
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83 cl::Hidden,
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84 cl::desc("Disable Machine LICM"));
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85 static cl::opt<bool> DisableMachineSink("disable-machine-sink", cl::Hidden,
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86 cl::desc("Disable Machine Sinking"));
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87 static cl::opt<bool> DisablePostRAMachineSink("disable-postra-machine-sink",
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88 cl::Hidden,
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89 cl::desc("Disable PostRA Machine Sinking"));
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90 static cl::opt<bool> DisableLSR("disable-lsr", cl::Hidden,
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91 cl::desc("Disable Loop Strength Reduction Pass"));
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92 static cl::opt<bool> DisableConstantHoisting("disable-constant-hoisting",
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93 cl::Hidden, cl::desc("Disable ConstantHoisting"));
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94 static cl::opt<bool> DisableCGP("disable-cgp", cl::Hidden,
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95 cl::desc("Disable Codegen Prepare"));
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96 static cl::opt<bool> DisableCopyProp("disable-copyprop", cl::Hidden,
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97 cl::desc("Disable Copy Propagation pass"));
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98 static cl::opt<bool> DisablePartialLibcallInlining("disable-partial-libcall-inlining",
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99 cl::Hidden, cl::desc("Disable Partial Libcall Inlining"));
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100 static cl::opt<bool> EnableImplicitNullChecks(
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101 "enable-implicit-null-checks",
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102 cl::desc("Fold null checks into faulting memory operations"),
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103 cl::init(false), cl::Hidden);
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104 static cl::opt<bool> DisableMergeICmps("disable-mergeicmps",
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105 cl::desc("Disable MergeICmps Pass"),
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106 cl::init(false), cl::Hidden);
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107 static cl::opt<bool> PrintLSR("print-lsr-output", cl::Hidden,
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108 cl::desc("Print LLVM IR produced by the loop-reduce pass"));
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109 static cl::opt<bool> PrintISelInput("print-isel-input", cl::Hidden,
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110 cl::desc("Print LLVM IR input to isel pass"));
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111 static cl::opt<bool> PrintGCInfo("print-gc", cl::Hidden,
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112 cl::desc("Dump garbage collector data"));
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113 static cl::opt<cl::boolOrDefault>
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114 VerifyMachineCode("verify-machineinstrs", cl::Hidden,
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115 cl::desc("Verify generated machine code"),
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116 cl::ZeroOrMore);
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117 enum RunOutliner { AlwaysOutline, NeverOutline, TargetDefault };
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118 // Enable or disable the MachineOutliner.
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119 static cl::opt<RunOutliner> EnableMachineOutliner(
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120 "enable-machine-outliner", cl::desc("Enable the machine outliner"),
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121 cl::Hidden, cl::ValueOptional, cl::init(TargetDefault),
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122 cl::values(clEnumValN(AlwaysOutline, "always",
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123 "Run on all functions guaranteed to be beneficial"),
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124 clEnumValN(NeverOutline, "never", "Disable all outlining"),
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125 // Sentinel value for unspecified option.
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126 clEnumValN(AlwaysOutline, "", "")));
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127 // Enable or disable FastISel. Both options are needed, because
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128 // FastISel is enabled by default with -fast, and we wish to be
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129 // able to enable or disable fast-isel independently from -O0.
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130 static cl::opt<cl::boolOrDefault>
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131 EnableFastISelOption("fast-isel", cl::Hidden,
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132 cl::desc("Enable the \"fast\" instruction selector"));
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133
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134 static cl::opt<cl::boolOrDefault> EnableGlobalISelOption(
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135 "global-isel", cl::Hidden,
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136 cl::desc("Enable the \"global\" instruction selector"));
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137
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138 static cl::opt<std::string> PrintMachineInstrs(
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139 "print-machineinstrs", cl::ValueOptional, cl::desc("Print machine instrs"),
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140 cl::value_desc("pass-name"), cl::init("option-unspecified"), cl::Hidden);
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141
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142 static cl::opt<GlobalISelAbortMode> EnableGlobalISelAbort(
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143 "global-isel-abort", cl::Hidden,
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144 cl::desc("Enable abort calls when \"global\" instruction selection "
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145 "fails to lower/select an instruction"),
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146 cl::values(
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147 clEnumValN(GlobalISelAbortMode::Disable, "0", "Disable the abort"),
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148 clEnumValN(GlobalISelAbortMode::Enable, "1", "Enable the abort"),
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149 clEnumValN(GlobalISelAbortMode::DisableWithDiag, "2",
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150 "Disable the abort but emit a diagnostic on failure")));
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151
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152 // Temporary option to allow experimenting with MachineScheduler as a post-RA
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153 // scheduler. Targets can "properly" enable this with
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154 // substitutePass(&PostRASchedulerID, &PostMachineSchedulerID).
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155 // Targets can return true in targetSchedulesPostRAScheduling() and
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156 // insert a PostRA scheduling pass wherever it wants.
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157 static cl::opt<bool> MISchedPostRA(
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158 "misched-postra", cl::Hidden,
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159 cl::desc(
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160 "Run MachineScheduler post regalloc (independent of preRA sched)"));
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161
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162 // Experimental option to run live interval analysis early.
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163 static cl::opt<bool> EarlyLiveIntervals("early-live-intervals", cl::Hidden,
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164 cl::desc("Run live interval analysis earlier in the pipeline"));
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165
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166 // Experimental option to use CFL-AA in codegen
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167 enum class CFLAAType { None, Steensgaard, Andersen, Both };
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168 static cl::opt<CFLAAType> UseCFLAA(
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169 "use-cfl-aa-in-codegen", cl::init(CFLAAType::None), cl::Hidden,
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170 cl::desc("Enable the new, experimental CFL alias analysis in CodeGen"),
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171 cl::values(clEnumValN(CFLAAType::None, "none", "Disable CFL-AA"),
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172 clEnumValN(CFLAAType::Steensgaard, "steens",
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173 "Enable unification-based CFL-AA"),
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174 clEnumValN(CFLAAType::Andersen, "anders",
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175 "Enable inclusion-based CFL-AA"),
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176 clEnumValN(CFLAAType::Both, "both",
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177 "Enable both variants of CFL-AA")));
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178
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179 /// Option names for limiting the codegen pipeline.
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180 /// Those are used in error reporting and we didn't want
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181 /// to duplicate their names all over the place.
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182 static const char StartAfterOptName[] = "start-after";
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183 static const char StartBeforeOptName[] = "start-before";
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184 static const char StopAfterOptName[] = "stop-after";
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185 static const char StopBeforeOptName[] = "stop-before";
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186
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187 static cl::opt<std::string>
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188 StartAfterOpt(StringRef(StartAfterOptName),
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189 cl::desc("Resume compilation after a specific pass"),
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190 cl::value_desc("pass-name"), cl::init(""), cl::Hidden);
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191
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192 static cl::opt<std::string>
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193 StartBeforeOpt(StringRef(StartBeforeOptName),
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194 cl::desc("Resume compilation before a specific pass"),
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195 cl::value_desc("pass-name"), cl::init(""), cl::Hidden);
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196
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197 static cl::opt<std::string>
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198 StopAfterOpt(StringRef(StopAfterOptName),
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199 cl::desc("Stop compilation after a specific pass"),
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200 cl::value_desc("pass-name"), cl::init(""), cl::Hidden);
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201
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202 static cl::opt<std::string>
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203 StopBeforeOpt(StringRef(StopBeforeOptName),
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204 cl::desc("Stop compilation before a specific pass"),
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205 cl::value_desc("pass-name"), cl::init(""), cl::Hidden);
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206
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207 /// Allow standard passes to be disabled by command line options. This supports
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208 /// simple binary flags that either suppress the pass or do nothing.
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209 /// i.e. -disable-mypass=false has no effect.
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210 /// These should be converted to boolOrDefault in order to use applyOverride.
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211 static IdentifyingPassPtr applyDisable(IdentifyingPassPtr PassID,
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212 bool Override) {
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213 if (Override)
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214 return IdentifyingPassPtr();
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215 return PassID;
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216 }
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217
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218 /// Allow standard passes to be disabled by the command line, regardless of who
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219 /// is adding the pass.
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220 ///
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221 /// StandardID is the pass identified in the standard pass pipeline and provided
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222 /// to addPass(). It may be a target-specific ID in the case that the target
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223 /// directly adds its own pass, but in that case we harmlessly fall through.
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224 ///
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225 /// TargetID is the pass that the target has configured to override StandardID.
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226 ///
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227 /// StandardID may be a pseudo ID. In that case TargetID is the name of the real
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228 /// pass to run. This allows multiple options to control a single pass depending
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229 /// on where in the pipeline that pass is added.
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230 static IdentifyingPassPtr overridePass(AnalysisID StandardID,
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231 IdentifyingPassPtr TargetID) {
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232 if (StandardID == &PostRASchedulerID)
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233 return applyDisable(TargetID, DisablePostRASched);
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234
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235 if (StandardID == &BranchFolderPassID)
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236 return applyDisable(TargetID, DisableBranchFold);
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237
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238 if (StandardID == &TailDuplicateID)
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239 return applyDisable(TargetID, DisableTailDuplicate);
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240
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241 if (StandardID == &EarlyTailDuplicateID)
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242 return applyDisable(TargetID, DisableEarlyTailDup);
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243
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244 if (StandardID == &MachineBlockPlacementID)
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245 return applyDisable(TargetID, DisableBlockPlacement);
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246
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247 if (StandardID == &StackSlotColoringID)
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248 return applyDisable(TargetID, DisableSSC);
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249
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250 if (StandardID == &DeadMachineInstructionElimID)
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251 return applyDisable(TargetID, DisableMachineDCE);
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252
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253 if (StandardID == &EarlyIfConverterID)
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254 return applyDisable(TargetID, DisableEarlyIfConversion);
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255
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256 if (StandardID == &EarlyMachineLICMID)
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257 return applyDisable(TargetID, DisableMachineLICM);
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258
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259 if (StandardID == &MachineCSEID)
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260 return applyDisable(TargetID, DisableMachineCSE);
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261
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262 if (StandardID == &MachineLICMID)
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263 return applyDisable(TargetID, DisablePostRAMachineLICM);
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264
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265 if (StandardID == &MachineSinkingID)
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266 return applyDisable(TargetID, DisableMachineSink);
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267
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268 if (StandardID == &PostRAMachineSinkingID)
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269 return applyDisable(TargetID, DisablePostRAMachineSink);
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270
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271 if (StandardID == &MachineCopyPropagationID)
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272 return applyDisable(TargetID, DisableCopyProp);
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273
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274 return TargetID;
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275 }
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276
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277 //===---------------------------------------------------------------------===//
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278 /// TargetPassConfig
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279 //===---------------------------------------------------------------------===//
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280
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281 INITIALIZE_PASS(TargetPassConfig, "targetpassconfig",
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282 "Target Pass Configuration", false, false)
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283 char TargetPassConfig::ID = 0;
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284
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285 namespace {
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286
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287 struct InsertedPass {
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288 AnalysisID TargetPassID;
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289 IdentifyingPassPtr InsertedPassID;
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290 bool VerifyAfter;
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291 bool PrintAfter;
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292
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293 InsertedPass(AnalysisID TargetPassID, IdentifyingPassPtr InsertedPassID,
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294 bool VerifyAfter, bool PrintAfter)
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295 : TargetPassID(TargetPassID), InsertedPassID(InsertedPassID),
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296 VerifyAfter(VerifyAfter), PrintAfter(PrintAfter) {}
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297
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298 Pass *getInsertedPass() const {
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299 assert(InsertedPassID.isValid() && "Illegal Pass ID!");
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300 if (InsertedPassID.isInstance())
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301 return InsertedPassID.getInstance();
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302 Pass *NP = Pass::createPass(InsertedPassID.getID());
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303 assert(NP && "Pass ID not registered");
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304 return NP;
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305 }
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306 };
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307
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308 } // end anonymous namespace
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309
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310 namespace llvm {
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311
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312 class PassConfigImpl {
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313 public:
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314 // List of passes explicitly substituted by this target. Normally this is
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315 // empty, but it is a convenient way to suppress or replace specific passes
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316 // that are part of a standard pass pipeline without overridding the entire
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317 // pipeline. This mechanism allows target options to inherit a standard pass's
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318 // user interface. For example, a target may disable a standard pass by
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319 // default by substituting a pass ID of zero, and the user may still enable
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320 // that standard pass with an explicit command line option.
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321 DenseMap<AnalysisID,IdentifyingPassPtr> TargetPasses;
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322
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323 /// Store the pairs of <AnalysisID, AnalysisID> of which the second pass
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324 /// is inserted after each instance of the first one.
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325 SmallVector<InsertedPass, 4> InsertedPasses;
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326 };
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327
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328 } // end namespace llvm
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329
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330 // Out of line virtual method.
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331 TargetPassConfig::~TargetPassConfig() {
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332 delete Impl;
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333 }
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334
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335 static const PassInfo *getPassInfo(StringRef PassName) {
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336 if (PassName.empty())
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337 return nullptr;
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338
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339 const PassRegistry &PR = *PassRegistry::getPassRegistry();
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340 const PassInfo *PI = PR.getPassInfo(PassName);
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341 if (!PI)
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342 report_fatal_error(Twine('\"') + Twine(PassName) +
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343 Twine("\" pass is not registered."));
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344 return PI;
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345 }
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346
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347 static AnalysisID getPassIDFromName(StringRef PassName) {
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348 const PassInfo *PI = getPassInfo(PassName);
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349 return PI ? PI->getTypeInfo() : nullptr;
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350 }
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351
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352 static std::pair<StringRef, unsigned>
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353 getPassNameAndInstanceNum(StringRef PassName) {
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354 StringRef Name, InstanceNumStr;
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355 std::tie(Name, InstanceNumStr) = PassName.split(',');
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356
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357 unsigned InstanceNum = 0;
|
|
|
358 if (!InstanceNumStr.empty() && InstanceNumStr.getAsInteger(10, InstanceNum))
|
|
|
359 report_fatal_error("invalid pass instance specifier " + PassName);
|
|
|
360
|
|
|
361 return std::make_pair(Name, InstanceNum);
|
|
|
362 }
|
|
|
363
|
|
|
364 void TargetPassConfig::setStartStopPasses() {
|
|
|
365 StringRef StartBeforeName;
|
|
|
366 std::tie(StartBeforeName, StartBeforeInstanceNum) =
|
|
|
367 getPassNameAndInstanceNum(StartBeforeOpt);
|
|
|
368
|
|
|
369 StringRef StartAfterName;
|
|
|
370 std::tie(StartAfterName, StartAfterInstanceNum) =
|
|
|
371 getPassNameAndInstanceNum(StartAfterOpt);
|
|
|
372
|
|
|
373 StringRef StopBeforeName;
|
|
|
374 std::tie(StopBeforeName, StopBeforeInstanceNum)
|
|
|
375 = getPassNameAndInstanceNum(StopBeforeOpt);
|
|
|
376
|
|
|
377 StringRef StopAfterName;
|
|
|
378 std::tie(StopAfterName, StopAfterInstanceNum)
|
|
|
379 = getPassNameAndInstanceNum(StopAfterOpt);
|
|
|
380
|
|
|
381 StartBefore = getPassIDFromName(StartBeforeName);
|
|
|
382 StartAfter = getPassIDFromName(StartAfterName);
|
|
|
383 StopBefore = getPassIDFromName(StopBeforeName);
|
|
|
384 StopAfter = getPassIDFromName(StopAfterName);
|
|
|
385 if (StartBefore && StartAfter)
|
|
|
386 report_fatal_error(Twine(StartBeforeOptName) + Twine(" and ") +
|
|
|
387 Twine(StartAfterOptName) + Twine(" specified!"));
|
|
|
388 if (StopBefore && StopAfter)
|
|
|
389 report_fatal_error(Twine(StopBeforeOptName) + Twine(" and ") +
|
|
|
390 Twine(StopAfterOptName) + Twine(" specified!"));
|
|
|
391 Started = (StartAfter == nullptr) && (StartBefore == nullptr);
|
|
|
392 }
|
|
|
393
|
|
|
394 // Out of line constructor provides default values for pass options and
|
|
|
395 // registers all common codegen passes.
|
|
|
396 TargetPassConfig::TargetPassConfig(LLVMTargetMachine &TM, PassManagerBase &pm)
|
|
|
397 : ImmutablePass(ID), PM(&pm), TM(&TM) {
|
|
|
398 Impl = new PassConfigImpl();
|
|
|
399
|
|
|
400 // Register all target independent codegen passes to activate their PassIDs,
|
|
|
401 // including this pass itself.
|
|
|
402 initializeCodeGen(*PassRegistry::getPassRegistry());
|
|
|
403
|
|
|
404 // Also register alias analysis passes required by codegen passes.
|
|
|
405 initializeBasicAAWrapperPassPass(*PassRegistry::getPassRegistry());
|
|
|
406 initializeAAResultsWrapperPassPass(*PassRegistry::getPassRegistry());
|
|
|
407
|
|
|
408 if (StringRef(PrintMachineInstrs.getValue()).equals(""))
|
|
|
409 TM.Options.PrintMachineCode = true;
|
|
|
410
|
|
|
411 if (EnableIPRA.getNumOccurrences())
|
|
|
412 TM.Options.EnableIPRA = EnableIPRA;
|
|
|
413 else {
|
|
|
414 // If not explicitly specified, use target default.
|
|
|
415 TM.Options.EnableIPRA |= TM.useIPRA();
|
|
|
416 }
|
|
|
417
|
|
|
418 if (TM.Options.EnableIPRA)
|
|
|
419 setRequiresCodeGenSCCOrder();
|
|
|
420
|
|
|
421 if (EnableGlobalISelAbort.getNumOccurrences())
|
|
|
422 TM.Options.GlobalISelAbort = EnableGlobalISelAbort;
|
|
|
423
|
|
|
424 setStartStopPasses();
|
|
|
425 }
|
|
|
426
|
|
|
427 CodeGenOpt::Level TargetPassConfig::getOptLevel() const {
|
|
|
428 return TM->getOptLevel();
|
|
|
429 }
|
|
|
430
|
|
152
|
431 #ifndef noCbC
|
|
|
432 unsigned TargetPassConfig::hasCodeSegment() {
|
|
|
433 return TM->Options.HasCodeSegment;
|
|
|
434 }
|
|
|
435 #endif
|
|
|
436
|
|
150
|
437 /// Insert InsertedPassID pass after TargetPassID.
|
|
|
438 void TargetPassConfig::insertPass(AnalysisID TargetPassID,
|
|
|
439 IdentifyingPassPtr InsertedPassID,
|
|
|
440 bool VerifyAfter, bool PrintAfter) {
|
|
|
441 assert(((!InsertedPassID.isInstance() &&
|
|
|
442 TargetPassID != InsertedPassID.getID()) ||
|
|
|
443 (InsertedPassID.isInstance() &&
|
|
|
444 TargetPassID != InsertedPassID.getInstance()->getPassID())) &&
|
|
|
445 "Insert a pass after itself!");
|
|
|
446 Impl->InsertedPasses.emplace_back(TargetPassID, InsertedPassID, VerifyAfter,
|
|
|
447 PrintAfter);
|
|
|
448 }
|
|
|
449
|
|
|
450 /// createPassConfig - Create a pass configuration object to be used by
|
|
|
451 /// addPassToEmitX methods for generating a pipeline of CodeGen passes.
|
|
|
452 ///
|
|
|
453 /// Targets may override this to extend TargetPassConfig.
|
|
|
454 TargetPassConfig *LLVMTargetMachine::createPassConfig(PassManagerBase &PM) {
|
|
|
455 return new TargetPassConfig(*this, PM);
|
|
|
456 }
|
|
|
457
|
|
|
458 TargetPassConfig::TargetPassConfig()
|
|
|
459 : ImmutablePass(ID) {
|
|
|
460 report_fatal_error("Trying to construct TargetPassConfig without a target "
|
|
|
461 "machine. Scheduling a CodeGen pass without a target "
|
|
|
462 "triple set?");
|
|
|
463 }
|
|
|
464
|
|
|
465 bool TargetPassConfig::willCompleteCodeGenPipeline() {
|
|
|
466 return StopBeforeOpt.empty() && StopAfterOpt.empty();
|
|
|
467 }
|
|
|
468
|
|
|
469 bool TargetPassConfig::hasLimitedCodeGenPipeline() {
|
|
|
470 return !StartBeforeOpt.empty() || !StartAfterOpt.empty() ||
|
|
|
471 !willCompleteCodeGenPipeline();
|
|
|
472 }
|
|
|
473
|
|
|
474 std::string
|
|
|
475 TargetPassConfig::getLimitedCodeGenPipelineReason(const char *Separator) const {
|
|
|
476 if (!hasLimitedCodeGenPipeline())
|
|
|
477 return std::string();
|
|
|
478 std::string Res;
|
|
|
479 static cl::opt<std::string> *PassNames[] = {&StartAfterOpt, &StartBeforeOpt,
|
|
|
480 &StopAfterOpt, &StopBeforeOpt};
|
|
|
481 static const char *OptNames[] = {StartAfterOptName, StartBeforeOptName,
|
|
|
482 StopAfterOptName, StopBeforeOptName};
|
|
|
483 bool IsFirst = true;
|
|
|
484 for (int Idx = 0; Idx < 4; ++Idx)
|
|
|
485 if (!PassNames[Idx]->empty()) {
|
|
|
486 if (!IsFirst)
|
|
|
487 Res += Separator;
|
|
|
488 IsFirst = false;
|
|
|
489 Res += OptNames[Idx];
|
|
|
490 }
|
|
|
491 return Res;
|
|
|
492 }
|
|
|
493
|
|
|
494 // Helper to verify the analysis is really immutable.
|
|
|
495 void TargetPassConfig::setOpt(bool &Opt, bool Val) {
|
|
|
496 assert(!Initialized && "PassConfig is immutable");
|
|
|
497 Opt = Val;
|
|
|
498 }
|
|
|
499
|
|
|
500 void TargetPassConfig::substitutePass(AnalysisID StandardID,
|
|
|
501 IdentifyingPassPtr TargetID) {
|
|
|
502 Impl->TargetPasses[StandardID] = TargetID;
|
|
|
503 }
|
|
|
504
|
|
|
505 IdentifyingPassPtr TargetPassConfig::getPassSubstitution(AnalysisID ID) const {
|
|
|
506 DenseMap<AnalysisID, IdentifyingPassPtr>::const_iterator
|
|
|
507 I = Impl->TargetPasses.find(ID);
|
|
|
508 if (I == Impl->TargetPasses.end())
|
|
|
509 return ID;
|
|
|
510 return I->second;
|
|
|
511 }
|
|
|
512
|
|
|
513 bool TargetPassConfig::isPassSubstitutedOrOverridden(AnalysisID ID) const {
|
|
|
514 IdentifyingPassPtr TargetID = getPassSubstitution(ID);
|
|
|
515 IdentifyingPassPtr FinalPtr = overridePass(ID, TargetID);
|
|
|
516 return !FinalPtr.isValid() || FinalPtr.isInstance() ||
|
|
|
517 FinalPtr.getID() != ID;
|
|
|
518 }
|
|
|
519
|
|
|
520 /// Add a pass to the PassManager if that pass is supposed to be run. If the
|
|
|
521 /// Started/Stopped flags indicate either that the compilation should start at
|
|
|
522 /// a later pass or that it should stop after an earlier pass, then do not add
|
|
|
523 /// the pass. Finally, compare the current pass against the StartAfter
|
|
|
524 /// and StopAfter options and change the Started/Stopped flags accordingly.
|
|
|
525 void TargetPassConfig::addPass(Pass *P, bool verifyAfter, bool printAfter) {
|
|
|
526 assert(!Initialized && "PassConfig is immutable");
|
|
|
527
|
|
|
528 // Cache the Pass ID here in case the pass manager finds this pass is
|
|
|
529 // redundant with ones already scheduled / available, and deletes it.
|
|
|
530 // Fundamentally, once we add the pass to the manager, we no longer own it
|
|
|
531 // and shouldn't reference it.
|
|
|
532 AnalysisID PassID = P->getPassID();
|
|
|
533
|
|
|
534 if (StartBefore == PassID && StartBeforeCount++ == StartBeforeInstanceNum)
|
|
|
535 Started = true;
|
|
|
536 if (StopBefore == PassID && StopBeforeCount++ == StopBeforeInstanceNum)
|
|
|
537 Stopped = true;
|
|
|
538 if (Started && !Stopped) {
|
|
|
539 std::string Banner;
|
|
|
540 // Construct banner message before PM->add() as that may delete the pass.
|
|
|
541 if (AddingMachinePasses && (printAfter || verifyAfter))
|
|
|
542 Banner = std::string("After ") + std::string(P->getPassName());
|
|
|
543 PM->add(P);
|
|
|
544 if (AddingMachinePasses) {
|
|
|
545 if (printAfter)
|
|
|
546 addPrintPass(Banner);
|
|
|
547 if (verifyAfter)
|
|
|
548 addVerifyPass(Banner);
|
|
|
549 }
|
|
|
550
|
|
|
551 // Add the passes after the pass P if there is any.
|
|
|
552 for (auto IP : Impl->InsertedPasses) {
|
|
|
553 if (IP.TargetPassID == PassID)
|
|
|
554 addPass(IP.getInsertedPass(), IP.VerifyAfter, IP.PrintAfter);
|
|
|
555 }
|
|
|
556 } else {
|
|
|
557 delete P;
|
|
|
558 }
|
|
|
559
|
|
|
560 if (StopAfter == PassID && StopAfterCount++ == StopAfterInstanceNum)
|
|
|
561 Stopped = true;
|
|
|
562
|
|
|
563 if (StartAfter == PassID && StartAfterCount++ == StartAfterInstanceNum)
|
|
|
564 Started = true;
|
|
|
565 if (Stopped && !Started)
|
|
|
566 report_fatal_error("Cannot stop compilation after pass that is not run");
|
|
|
567 }
|
|
|
568
|
|
|
569 /// Add a CodeGen pass at this point in the pipeline after checking for target
|
|
|
570 /// and command line overrides.
|
|
|
571 ///
|
|
|
572 /// addPass cannot return a pointer to the pass instance because is internal the
|
|
|
573 /// PassManager and the instance we create here may already be freed.
|
|
|
574 AnalysisID TargetPassConfig::addPass(AnalysisID PassID, bool verifyAfter,
|
|
|
575 bool printAfter) {
|
|
|
576 IdentifyingPassPtr TargetID = getPassSubstitution(PassID);
|
|
|
577 IdentifyingPassPtr FinalPtr = overridePass(PassID, TargetID);
|
|
|
578 if (!FinalPtr.isValid())
|
|
|
579 return nullptr;
|
|
|
580
|
|
|
581 Pass *P;
|
|
|
582 if (FinalPtr.isInstance())
|
|
|
583 P = FinalPtr.getInstance();
|
|
|
584 else {
|
|
|
585 P = Pass::createPass(FinalPtr.getID());
|
|
|
586 if (!P)
|
|
|
587 llvm_unreachable("Pass ID not registered");
|
|
|
588 }
|
|
|
589 AnalysisID FinalID = P->getPassID();
|
|
|
590 addPass(P, verifyAfter, printAfter); // Ends the lifetime of P.
|
|
|
591
|
|
|
592 return FinalID;
|
|
|
593 }
|
|
|
594
|
|
|
595 void TargetPassConfig::printAndVerify(const std::string &Banner) {
|
|
|
596 addPrintPass(Banner);
|
|
|
597 addVerifyPass(Banner);
|
|
|
598 }
|
|
|
599
|
|
|
600 void TargetPassConfig::addPrintPass(const std::string &Banner) {
|
|
|
601 if (TM->shouldPrintMachineCode())
|
|
|
602 PM->add(createMachineFunctionPrinterPass(dbgs(), Banner));
|
|
|
603 }
|
|
|
604
|
|
|
605 void TargetPassConfig::addVerifyPass(const std::string &Banner) {
|
|
|
606 bool Verify = VerifyMachineCode == cl::BOU_TRUE;
|
|
|
607 #ifdef EXPENSIVE_CHECKS
|
|
|
608 if (VerifyMachineCode == cl::BOU_UNSET)
|
|
|
609 Verify = TM->isMachineVerifierClean();
|
|
|
610 #endif
|
|
|
611 if (Verify)
|
|
|
612 PM->add(createMachineVerifierPass(Banner));
|
|
|
613 }
|
|
|
614
|
|
|
615 /// Add common target configurable passes that perform LLVM IR to IR transforms
|
|
|
616 /// following machine independent optimization.
|
|
|
617 void TargetPassConfig::addIRPasses() {
|
|
|
618 switch (UseCFLAA) {
|
|
|
619 case CFLAAType::Steensgaard:
|
|
|
620 addPass(createCFLSteensAAWrapperPass());
|
|
|
621 break;
|
|
|
622 case CFLAAType::Andersen:
|
|
|
623 addPass(createCFLAndersAAWrapperPass());
|
|
|
624 break;
|
|
|
625 case CFLAAType::Both:
|
|
|
626 addPass(createCFLAndersAAWrapperPass());
|
|
|
627 addPass(createCFLSteensAAWrapperPass());
|
|
|
628 break;
|
|
|
629 default:
|
|
|
630 break;
|
|
|
631 }
|
|
|
632
|
|
|
633 // Basic AliasAnalysis support.
|
|
|
634 // Add TypeBasedAliasAnalysis before BasicAliasAnalysis so that
|
|
|
635 // BasicAliasAnalysis wins if they disagree. This is intended to help
|
|
|
636 // support "obvious" type-punning idioms.
|
|
|
637 addPass(createTypeBasedAAWrapperPass());
|
|
|
638 addPass(createScopedNoAliasAAWrapperPass());
|
|
|
639 addPass(createBasicAAWrapperPass());
|
|
|
640
|
|
|
641 // Before running any passes, run the verifier to determine if the input
|
|
|
642 // coming from the front-end and/or optimizer is valid.
|
|
|
643 if (!DisableVerify)
|
|
|
644 addPass(createVerifierPass());
|
|
|
645
|
|
|
646 // Run loop strength reduction before anything else.
|
|
|
647 if (getOptLevel() != CodeGenOpt::None && !DisableLSR) {
|
|
|
648 addPass(createLoopStrengthReducePass());
|
|
|
649 if (PrintLSR)
|
|
|
650 addPass(createPrintFunctionPass(dbgs(), "\n\n*** Code after LSR ***\n"));
|
|
|
651 }
|
|
|
652
|
|
|
653 if (getOptLevel() != CodeGenOpt::None) {
|
|
|
654 // The MergeICmpsPass tries to create memcmp calls by grouping sequences of
|
|
|
655 // loads and compares. ExpandMemCmpPass then tries to expand those calls
|
|
|
656 // into optimally-sized loads and compares. The transforms are enabled by a
|
|
|
657 // target lowering hook.
|
|
|
658 if (!DisableMergeICmps)
|
|
|
659 addPass(createMergeICmpsLegacyPass());
|
|
|
660 addPass(createExpandMemCmpPass());
|
|
|
661 }
|
|
|
662
|
|
|
663 // Run GC lowering passes for builtin collectors
|
|
|
664 // TODO: add a pass insertion point here
|
|
|
665 addPass(createGCLoweringPass());
|
|
|
666 addPass(createShadowStackGCLoweringPass());
|
|
|
667 addPass(createLowerConstantIntrinsicsPass());
|
|
|
668
|
|
|
669 // Make sure that no unreachable blocks are instruction selected.
|
|
|
670 addPass(createUnreachableBlockEliminationPass());
|
|
|
671
|
|
|
672 // Prepare expensive constants for SelectionDAG.
|
|
|
673 if (getOptLevel() != CodeGenOpt::None && !DisableConstantHoisting)
|
|
|
674 addPass(createConstantHoistingPass());
|
|
|
675
|
|
|
676 if (getOptLevel() != CodeGenOpt::None && !DisablePartialLibcallInlining)
|
|
|
677 addPass(createPartiallyInlineLibCallsPass());
|
|
|
678
|
|
|
679 // Instrument function entry and exit, e.g. with calls to mcount().
|
|
|
680 addPass(createPostInlineEntryExitInstrumenterPass());
|
|
|
681
|
|
|
682 // Add scalarization of target's unsupported masked memory intrinsics pass.
|
|
|
683 // the unsupported intrinsic will be replaced with a chain of basic blocks,
|
|
|
684 // that stores/loads element one-by-one if the appropriate mask bit is set.
|
|
|
685 addPass(createScalarizeMaskedMemIntrinPass());
|
|
|
686
|
|
|
687 // Expand reduction intrinsics into shuffle sequences if the target wants to.
|
|
|
688 addPass(createExpandReductionsPass());
|
|
|
689 }
|
|
|
690
|
|
|
691 /// Turn exception handling constructs into something the code generators can
|
|
|
692 /// handle.
|
|
|
693 void TargetPassConfig::addPassesToHandleExceptions() {
|
|
|
694 const MCAsmInfo *MCAI = TM->getMCAsmInfo();
|
|
|
695 assert(MCAI && "No MCAsmInfo");
|
|
|
696 switch (MCAI->getExceptionHandlingType()) {
|
|
|
697 case ExceptionHandling::SjLj:
|
|
|
698 // SjLj piggy-backs on dwarf for this bit. The cleanups done apply to both
|
|
|
699 // Dwarf EH prepare needs to be run after SjLj prepare. Otherwise,
|
|
|
700 // catch info can get misplaced when a selector ends up more than one block
|
|
|
701 // removed from the parent invoke(s). This could happen when a landing
|
|
|
702 // pad is shared by multiple invokes and is also a target of a normal
|
|
|
703 // edge from elsewhere.
|
|
|
704 addPass(createSjLjEHPreparePass());
|
|
|
705 LLVM_FALLTHROUGH;
|
|
|
706 case ExceptionHandling::DwarfCFI:
|
|
|
707 case ExceptionHandling::ARM:
|
|
|
708 addPass(createDwarfEHPass());
|
|
|
709 break;
|
|
|
710 case ExceptionHandling::WinEH:
|
|
|
711 // We support using both GCC-style and MSVC-style exceptions on Windows, so
|
|
|
712 // add both preparation passes. Each pass will only actually run if it
|
|
|
713 // recognizes the personality function.
|
|
|
714 addPass(createWinEHPass());
|
|
|
715 addPass(createDwarfEHPass());
|
|
|
716 break;
|
|
|
717 case ExceptionHandling::Wasm:
|
|
|
718 // Wasm EH uses Windows EH instructions, but it does not need to demote PHIs
|
|
|
719 // on catchpads and cleanuppads because it does not outline them into
|
|
|
720 // funclets. Catchswitch blocks are not lowered in SelectionDAG, so we
|
|
|
721 // should remove PHIs there.
|
|
|
722 addPass(createWinEHPass(/*DemoteCatchSwitchPHIOnly=*/false));
|
|
|
723 addPass(createWasmEHPass());
|
|
|
724 break;
|
|
|
725 case ExceptionHandling::None:
|
|
|
726 addPass(createLowerInvokePass());
|
|
|
727
|
|
|
728 // The lower invoke pass may create unreachable code. Remove it.
|
|
|
729 addPass(createUnreachableBlockEliminationPass());
|
|
|
730 break;
|
|
|
731 }
|
|
|
732 }
|
|
|
733
|
|
|
734 /// Add pass to prepare the LLVM IR for code generation. This should be done
|
|
|
735 /// before exception handling preparation passes.
|
|
|
736 void TargetPassConfig::addCodeGenPrepare() {
|
|
152
|
737 #ifdef noCbC
|
|
150
|
738 if (getOptLevel() != CodeGenOpt::None && !DisableCGP)
|
|
152
|
739 #endif
|
|
150
|
740 addPass(createCodeGenPreparePass());
|
|
|
741 addPass(createRewriteSymbolsPass());
|
|
|
742 }
|
|
|
743
|
|
|
744 /// Add common passes that perform LLVM IR to IR transforms in preparation for
|
|
|
745 /// instruction selection.
|
|
|
746 void TargetPassConfig::addISelPrepare() {
|
|
|
747 addPreISel();
|
|
|
748
|
|
|
749 // Force codegen to run according to the callgraph.
|
|
|
750 if (requiresCodeGenSCCOrder())
|
|
|
751 addPass(new DummyCGSCCPass);
|
|
|
752
|
|
|
753 // Add both the safe stack and the stack protection passes: each of them will
|
|
|
754 // only protect functions that have corresponding attributes.
|
|
|
755 addPass(createSafeStackPass());
|
|
|
756 addPass(createStackProtectorPass());
|
|
|
757
|
|
|
758 if (PrintISelInput)
|
|
|
759 addPass(createPrintFunctionPass(
|
|
|
760 dbgs(), "\n\n*** Final LLVM Code input to ISel ***\n"));
|
|
|
761
|
|
|
762 // All passes which modify the LLVM IR are now complete; run the verifier
|
|
|
763 // to ensure that the IR is valid.
|
|
|
764 if (!DisableVerify)
|
|
|
765 addPass(createVerifierPass());
|
|
|
766 }
|
|
|
767
|
|
|
768 bool TargetPassConfig::addCoreISelPasses() {
|
|
|
769 // Enable FastISel with -fast-isel, but allow that to be overridden.
|
|
|
770 TM->setO0WantsFastISel(EnableFastISelOption != cl::BOU_FALSE);
|
|
|
771
|
|
|
772 // Determine an instruction selector.
|
|
|
773 enum class SelectorType { SelectionDAG, FastISel, GlobalISel };
|
|
|
774 SelectorType Selector;
|
|
|
775
|
|
|
776 if (EnableFastISelOption == cl::BOU_TRUE)
|
|
|
777 Selector = SelectorType::FastISel;
|
|
|
778 else if (EnableGlobalISelOption == cl::BOU_TRUE ||
|
|
|
779 (TM->Options.EnableGlobalISel &&
|
|
|
780 EnableGlobalISelOption != cl::BOU_FALSE))
|
|
|
781 Selector = SelectorType::GlobalISel;
|
|
|
782 else if (TM->getOptLevel() == CodeGenOpt::None && TM->getO0WantsFastISel())
|
|
|
783 Selector = SelectorType::FastISel;
|
|
|
784 else
|
|
|
785 Selector = SelectorType::SelectionDAG;
|
|
|
786
|
|
|
787 // Set consistently TM->Options.EnableFastISel and EnableGlobalISel.
|
|
|
788 if (Selector == SelectorType::FastISel) {
|
|
|
789 TM->setFastISel(true);
|
|
|
790 TM->setGlobalISel(false);
|
|
|
791 } else if (Selector == SelectorType::GlobalISel) {
|
|
|
792 TM->setFastISel(false);
|
|
|
793 TM->setGlobalISel(true);
|
|
|
794 }
|
|
|
795
|
|
|
796 // Add instruction selector passes.
|
|
|
797 if (Selector == SelectorType::GlobalISel) {
|
|
|
798 SaveAndRestore<bool> SavedAddingMachinePasses(AddingMachinePasses, true);
|
|
|
799 if (addIRTranslator())
|
|
|
800 return true;
|
|
|
801
|
|
|
802 addPreLegalizeMachineIR();
|
|
|
803
|
|
|
804 if (addLegalizeMachineIR())
|
|
|
805 return true;
|
|
|
806
|
|
|
807 // Before running the register bank selector, ask the target if it
|
|
|
808 // wants to run some passes.
|
|
|
809 addPreRegBankSelect();
|
|
|
810
|
|
|
811 if (addRegBankSelect())
|
|
|
812 return true;
|
|
|
813
|
|
|
814 addPreGlobalInstructionSelect();
|
|
|
815
|
|
|
816 if (addGlobalInstructionSelect())
|
|
|
817 return true;
|
|
|
818
|
|
|
819 // Pass to reset the MachineFunction if the ISel failed.
|
|
|
820 addPass(createResetMachineFunctionPass(
|
|
|
821 reportDiagnosticWhenGlobalISelFallback(), isGlobalISelAbortEnabled()));
|
|
|
822
|
|
|
823 // Provide a fallback path when we do not want to abort on
|
|
|
824 // not-yet-supported input.
|
|
|
825 if (!isGlobalISelAbortEnabled() && addInstSelector())
|
|
|
826 return true;
|
|
|
827
|
|
|
828 } else if (addInstSelector())
|
|
|
829 return true;
|
|
|
830
|
|
|
831 // Expand pseudo-instructions emitted by ISel. Don't run the verifier before
|
|
|
832 // FinalizeISel.
|
|
|
833 addPass(&FinalizeISelID);
|
|
|
834
|
|
|
835 // Print the instruction selected machine code...
|
|
|
836 printAndVerify("After Instruction Selection");
|
|
|
837
|
|
|
838 return false;
|
|
|
839 }
|
|
|
840
|
|
|
841 bool TargetPassConfig::addISelPasses() {
|
|
|
842 if (TM->useEmulatedTLS())
|
|
|
843 addPass(createLowerEmuTLSPass());
|
|
|
844
|
|
|
845 addPass(createPreISelIntrinsicLoweringPass());
|
|
|
846 addPass(createTargetTransformInfoWrapperPass(TM->getTargetIRAnalysis()));
|
|
|
847 addIRPasses();
|
|
|
848 addCodeGenPrepare();
|
|
|
849 addPassesToHandleExceptions();
|
|
|
850 addISelPrepare();
|
|
|
851
|
|
|
852 return addCoreISelPasses();
|
|
|
853 }
|
|
|
854
|
|
|
855 /// -regalloc=... command line option.
|
|
|
856 static FunctionPass *useDefaultRegisterAllocator() { return nullptr; }
|
|
|
857 static cl::opt<RegisterRegAlloc::FunctionPassCtor, false,
|
|
|
858 RegisterPassParser<RegisterRegAlloc>>
|
|
|
859 RegAlloc("regalloc", cl::Hidden, cl::init(&useDefaultRegisterAllocator),
|
|
|
860 cl::desc("Register allocator to use"));
|
|
|
861
|
|
|
862 /// Add the complete set of target-independent postISel code generator passes.
|
|
|
863 ///
|
|
|
864 /// This can be read as the standard order of major LLVM CodeGen stages. Stages
|
|
|
865 /// with nontrivial configuration or multiple passes are broken out below in
|
|
|
866 /// add%Stage routines.
|
|
|
867 ///
|
|
|
868 /// Any TargetPassConfig::addXX routine may be overriden by the Target. The
|
|
|
869 /// addPre/Post methods with empty header implementations allow injecting
|
|
|
870 /// target-specific fixups just before or after major stages. Additionally,
|
|
|
871 /// targets have the flexibility to change pass order within a stage by
|
|
|
872 /// overriding default implementation of add%Stage routines below. Each
|
|
|
873 /// technique has maintainability tradeoffs because alternate pass orders are
|
|
|
874 /// not well supported. addPre/Post works better if the target pass is easily
|
|
|
875 /// tied to a common pass. But if it has subtle dependencies on multiple passes,
|
|
|
876 /// the target should override the stage instead.
|
|
|
877 ///
|
|
|
878 /// TODO: We could use a single addPre/Post(ID) hook to allow pass injection
|
|
|
879 /// before/after any target-independent pass. But it's currently overkill.
|
|
|
880 void TargetPassConfig::addMachinePasses() {
|
|
|
881 AddingMachinePasses = true;
|
|
|
882
|
|
|
883 // Insert a machine instr printer pass after the specified pass.
|
|
|
884 StringRef PrintMachineInstrsPassName = PrintMachineInstrs.getValue();
|
|
|
885 if (!PrintMachineInstrsPassName.equals("") &&
|
|
|
886 !PrintMachineInstrsPassName.equals("option-unspecified")) {
|
|
|
887 if (const PassInfo *TPI = getPassInfo(PrintMachineInstrsPassName)) {
|
|
|
888 const PassRegistry *PR = PassRegistry::getPassRegistry();
|
|
|
889 const PassInfo *IPI = PR->getPassInfo(StringRef("machineinstr-printer"));
|
|
|
890 assert(IPI && "failed to get \"machineinstr-printer\" PassInfo!");
|
|
|
891 const char *TID = (const char *)(TPI->getTypeInfo());
|
|
|
892 const char *IID = (const char *)(IPI->getTypeInfo());
|
|
|
893 insertPass(TID, IID);
|
|
|
894 }
|
|
|
895 }
|
|
|
896
|
|
|
897 // Add passes that optimize machine instructions in SSA form.
|
|
|
898 if (getOptLevel() != CodeGenOpt::None) {
|
|
|
899 addMachineSSAOptimization();
|
|
|
900 } else {
|
|
|
901 // If the target requests it, assign local variables to stack slots relative
|
|
|
902 // to one another and simplify frame index references where possible.
|
|
|
903 addPass(&LocalStackSlotAllocationID, false);
|
|
|
904 }
|
|
|
905
|
|
|
906 if (TM->Options.EnableIPRA)
|
|
|
907 addPass(createRegUsageInfoPropPass());
|
|
|
908
|
|
|
909 // Run pre-ra passes.
|
|
|
910 addPreRegAlloc();
|
|
|
911
|
|
|
912 // Run register allocation and passes that are tightly coupled with it,
|
|
|
913 // including phi elimination and scheduling.
|
|
|
914 if (getOptimizeRegAlloc())
|
|
|
915 addOptimizedRegAlloc();
|
|
|
916 else
|
|
|
917 addFastRegAlloc();
|
|
|
918
|
|
|
919 // Run post-ra passes.
|
|
|
920 addPostRegAlloc();
|
|
|
921
|
|
|
922 // Insert prolog/epilog code. Eliminate abstract frame index references...
|
|
|
923 if (getOptLevel() != CodeGenOpt::None) {
|
|
|
924 addPass(&PostRAMachineSinkingID);
|
|
|
925 addPass(&ShrinkWrapID);
|
|
|
926 }
|
|
|
927
|
|
|
928 // Prolog/Epilog inserter needs a TargetMachine to instantiate. But only
|
|
|
929 // do so if it hasn't been disabled, substituted, or overridden.
|
|
|
930 if (!isPassSubstitutedOrOverridden(&PrologEpilogCodeInserterID))
|
|
|
931 addPass(createPrologEpilogInserterPass());
|
|
|
932
|
|
|
933 /// Add passes that optimize machine instructions after register allocation.
|
|
|
934 if (getOptLevel() != CodeGenOpt::None)
|
|
|
935 addMachineLateOptimization();
|
|
|
936
|
|
|
937 // Expand pseudo instructions before second scheduling pass.
|
|
|
938 addPass(&ExpandPostRAPseudosID);
|
|
|
939
|
|
|
940 // Run pre-sched2 passes.
|
|
|
941 addPreSched2();
|
|
|
942
|
|
|
943 if (EnableImplicitNullChecks)
|
|
|
944 addPass(&ImplicitNullChecksID);
|
|
|
945
|
|
|
946 // Second pass scheduler.
|
|
|
947 // Let Target optionally insert this pass by itself at some other
|
|
|
948 // point.
|
|
|
949 if (getOptLevel() != CodeGenOpt::None &&
|
|
|
950 !TM->targetSchedulesPostRAScheduling()) {
|
|
|
951 if (MISchedPostRA)
|
|
|
952 addPass(&PostMachineSchedulerID);
|
|
|
953 else
|
|
|
954 addPass(&PostRASchedulerID);
|
|
|
955 }
|
|
|
956
|
|
|
957 // GC
|
|
|
958 if (addGCPasses()) {
|
|
|
959 if (PrintGCInfo)
|
|
|
960 addPass(createGCInfoPrinter(dbgs()), false, false);
|
|
|
961 }
|
|
|
962
|
|
|
963 // Basic block placement.
|
|
|
964 if (getOptLevel() != CodeGenOpt::None)
|
|
|
965 addBlockPlacement();
|
|
|
966
|
|
|
967 // Insert before XRay Instrumentation.
|
|
|
968 addPass(&FEntryInserterID, false);
|
|
|
969
|
|
|
970 addPass(&XRayInstrumentationID, false);
|
|
|
971 addPass(&PatchableFunctionID, false);
|
|
|
972
|
|
|
973 addPreEmitPass();
|
|
|
974
|
|
|
975 if (TM->Options.EnableIPRA)
|
|
|
976 // Collect register usage information and produce a register mask of
|
|
|
977 // clobbered registers, to be used to optimize call sites.
|
|
|
978 addPass(createRegUsageInfoCollector());
|
|
|
979
|
|
|
980 addPass(&FuncletLayoutID, false);
|
|
|
981
|
|
|
982 addPass(&StackMapLivenessID, false);
|
|
|
983 addPass(&LiveDebugValuesID, false);
|
|
|
984
|
|
|
985 if (TM->Options.EnableMachineOutliner && getOptLevel() != CodeGenOpt::None &&
|
|
|
986 EnableMachineOutliner != NeverOutline) {
|
|
|
987 bool RunOnAllFunctions = (EnableMachineOutliner == AlwaysOutline);
|
|
|
988 bool AddOutliner = RunOnAllFunctions ||
|
|
|
989 TM->Options.SupportsDefaultOutlining;
|
|
|
990 if (AddOutliner)
|
|
|
991 addPass(createMachineOutlinerPass(RunOnAllFunctions));
|
|
|
992 }
|
|
|
993
|
|
|
994 // Add passes that directly emit MI after all other MI passes.
|
|
|
995 addPreEmitPass2();
|
|
|
996
|
|
|
997 AddingMachinePasses = false;
|
|
|
998 }
|
|
|
999
|
|
|
1000 /// Add passes that optimize machine instructions in SSA form.
|
|
|
1001 void TargetPassConfig::addMachineSSAOptimization() {
|
|
|
1002 // Pre-ra tail duplication.
|
|
|
1003 addPass(&EarlyTailDuplicateID);
|
|
|
1004
|
|
|
1005 // Optimize PHIs before DCE: removing dead PHI cycles may make more
|
|
|
1006 // instructions dead.
|
|
|
1007 addPass(&OptimizePHIsID, false);
|
|
|
1008
|
|
|
1009 // This pass merges large allocas. StackSlotColoring is a different pass
|
|
|
1010 // which merges spill slots.
|
|
|
1011 addPass(&StackColoringID, false);
|
|
|
1012
|
|
|
1013 // If the target requests it, assign local variables to stack slots relative
|
|
|
1014 // to one another and simplify frame index references where possible.
|
|
|
1015 addPass(&LocalStackSlotAllocationID, false);
|
|
|
1016
|
|
|
1017 // With optimization, dead code should already be eliminated. However
|
|
|
1018 // there is one known exception: lowered code for arguments that are only
|
|
|
1019 // used by tail calls, where the tail calls reuse the incoming stack
|
|
|
1020 // arguments directly (see t11 in test/CodeGen/X86/sibcall.ll).
|
|
|
1021 addPass(&DeadMachineInstructionElimID);
|
|
|
1022
|
|
|
1023 // Allow targets to insert passes that improve instruction level parallelism,
|
|
|
1024 // like if-conversion. Such passes will typically need dominator trees and
|
|
|
1025 // loop info, just like LICM and CSE below.
|
|
|
1026 addILPOpts();
|
|
|
1027
|
|
|
1028 addPass(&EarlyMachineLICMID, false);
|
|
|
1029 addPass(&MachineCSEID, false);
|
|
|
1030
|
|
|
1031 addPass(&MachineSinkingID);
|
|
|
1032
|
|
|
1033 addPass(&PeepholeOptimizerID);
|
|
|
1034 // Clean-up the dead code that may have been generated by peephole
|
|
|
1035 // rewriting.
|
|
|
1036 addPass(&DeadMachineInstructionElimID);
|
|
|
1037 }
|
|
|
1038
|
|
|
1039 //===---------------------------------------------------------------------===//
|
|
|
1040 /// Register Allocation Pass Configuration
|
|
|
1041 //===---------------------------------------------------------------------===//
|
|
|
1042
|
|
|
1043 bool TargetPassConfig::getOptimizeRegAlloc() const {
|
|
|
1044 switch (OptimizeRegAlloc) {
|
|
|
1045 case cl::BOU_UNSET: return getOptLevel() != CodeGenOpt::None;
|
|
|
1046 case cl::BOU_TRUE: return true;
|
|
|
1047 case cl::BOU_FALSE: return false;
|
|
|
1048 }
|
|
|
1049 llvm_unreachable("Invalid optimize-regalloc state");
|
|
|
1050 }
|
|
|
1051
|
|
|
1052 /// A dummy default pass factory indicates whether the register allocator is
|
|
|
1053 /// overridden on the command line.
|
|
|
1054 static llvm::once_flag InitializeDefaultRegisterAllocatorFlag;
|
|
|
1055
|
|
|
1056 static RegisterRegAlloc
|
|
|
1057 defaultRegAlloc("default",
|
|
|
1058 "pick register allocator based on -O option",
|
|
|
1059 useDefaultRegisterAllocator);
|
|
|
1060
|
|
|
1061 static void initializeDefaultRegisterAllocatorOnce() {
|
|
|
1062 if (!RegisterRegAlloc::getDefault())
|
|
|
1063 RegisterRegAlloc::setDefault(RegAlloc);
|
|
|
1064 }
|
|
|
1065
|
|
|
1066 /// Instantiate the default register allocator pass for this target for either
|
|
|
1067 /// the optimized or unoptimized allocation path. This will be added to the pass
|
|
|
1068 /// manager by addFastRegAlloc in the unoptimized case or addOptimizedRegAlloc
|
|
|
1069 /// in the optimized case.
|
|
|
1070 ///
|
|
|
1071 /// A target that uses the standard regalloc pass order for fast or optimized
|
|
|
1072 /// allocation may still override this for per-target regalloc
|
|
|
1073 /// selection. But -regalloc=... always takes precedence.
|
|
|
1074 FunctionPass *TargetPassConfig::createTargetRegisterAllocator(bool Optimized) {
|
|
|
1075 if (Optimized)
|
|
|
1076 return createGreedyRegisterAllocator();
|
|
|
1077 else
|
|
|
1078 return createFastRegisterAllocator();
|
|
|
1079 }
|
|
|
1080
|
|
|
1081 /// Find and instantiate the register allocation pass requested by this target
|
|
|
1082 /// at the current optimization level. Different register allocators are
|
|
|
1083 /// defined as separate passes because they may require different analysis.
|
|
|
1084 ///
|
|
|
1085 /// This helper ensures that the regalloc= option is always available,
|
|
|
1086 /// even for targets that override the default allocator.
|
|
|
1087 ///
|
|
|
1088 /// FIXME: When MachinePassRegistry register pass IDs instead of function ptrs,
|
|
|
1089 /// this can be folded into addPass.
|
|
|
1090 FunctionPass *TargetPassConfig::createRegAllocPass(bool Optimized) {
|
|
|
1091 // Initialize the global default.
|
|
|
1092 llvm::call_once(InitializeDefaultRegisterAllocatorFlag,
|
|
|
1093 initializeDefaultRegisterAllocatorOnce);
|
|
|
1094
|
|
|
1095 RegisterRegAlloc::FunctionPassCtor Ctor = RegisterRegAlloc::getDefault();
|
|
|
1096 if (Ctor != useDefaultRegisterAllocator)
|
|
|
1097 return Ctor();
|
|
|
1098
|
|
|
1099 // With no -regalloc= override, ask the target for a regalloc pass.
|
|
|
1100 return createTargetRegisterAllocator(Optimized);
|
|
|
1101 }
|
|
|
1102
|
|
|
1103 bool TargetPassConfig::addRegAssignmentFast() {
|
|
|
1104 if (RegAlloc != &useDefaultRegisterAllocator &&
|
|
|
1105 RegAlloc != &createFastRegisterAllocator)
|
|
|
1106 report_fatal_error("Must use fast (default) register allocator for unoptimized regalloc.");
|
|
|
1107
|
|
|
1108 addPass(createRegAllocPass(false));
|
|
|
1109 return true;
|
|
|
1110 }
|
|
|
1111
|
|
|
1112 bool TargetPassConfig::addRegAssignmentOptimized() {
|
|
|
1113 // Add the selected register allocation pass.
|
|
|
1114 addPass(createRegAllocPass(true));
|
|
|
1115
|
|
|
1116 // Allow targets to change the register assignments before rewriting.
|
|
|
1117 addPreRewrite();
|
|
|
1118
|
|
|
1119 // Finally rewrite virtual registers.
|
|
|
1120 addPass(&VirtRegRewriterID);
|
|
|
1121 // Perform stack slot coloring and post-ra machine LICM.
|
|
|
1122 //
|
|
|
1123 // FIXME: Re-enable coloring with register when it's capable of adding
|
|
|
1124 // kill markers.
|
|
|
1125 addPass(&StackSlotColoringID);
|
|
|
1126
|
|
|
1127 return true;
|
|
|
1128 }
|
|
|
1129
|
|
|
1130 /// Return true if the default global register allocator is in use and
|
|
|
1131 /// has not be overriden on the command line with '-regalloc=...'
|
|
|
1132 bool TargetPassConfig::usingDefaultRegAlloc() const {
|
|
|
1133 return RegAlloc.getNumOccurrences() == 0;
|
|
|
1134 }
|
|
|
1135
|
|
|
1136 /// Add the minimum set of target-independent passes that are required for
|
|
|
1137 /// register allocation. No coalescing or scheduling.
|
|
|
1138 void TargetPassConfig::addFastRegAlloc() {
|
|
|
1139 addPass(&PHIEliminationID, false);
|
|
|
1140 addPass(&TwoAddressInstructionPassID, false);
|
|
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1141
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1142 addRegAssignmentFast();
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|
|
1143 }
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|
|
1144
|
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|
1145 /// Add standard target-independent passes that are tightly coupled with
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1146 /// optimized register allocation, including coalescing, machine instruction
|
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|
1147 /// scheduling, and register allocation itself.
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|
|
1148 void TargetPassConfig::addOptimizedRegAlloc() {
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|
|
1149 addPass(&DetectDeadLanesID, false);
|
|
|
1150
|
|
|
1151 addPass(&ProcessImplicitDefsID, false);
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|
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1152
|
|
|
1153 // LiveVariables currently requires pure SSA form.
|
|
|
1154 //
|
|
|
1155 // FIXME: Once TwoAddressInstruction pass no longer uses kill flags,
|
|
|
1156 // LiveVariables can be removed completely, and LiveIntervals can be directly
|
|
|
1157 // computed. (We still either need to regenerate kill flags after regalloc, or
|
|
|
1158 // preferably fix the scavenger to not depend on them).
|
|
|
1159 addPass(&LiveVariablesID, false);
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|
|
1160
|
|
|
1161 // Edge splitting is smarter with machine loop info.
|
|
|
1162 addPass(&MachineLoopInfoID, false);
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|
|
1163 addPass(&PHIEliminationID, false);
|
|
|
1164
|
|
|
1165 // Eventually, we want to run LiveIntervals before PHI elimination.
|
|
|
1166 if (EarlyLiveIntervals)
|
|
|
1167 addPass(&LiveIntervalsID, false);
|
|
|
1168
|
|
|
1169 addPass(&TwoAddressInstructionPassID, false);
|
|
|
1170 addPass(&RegisterCoalescerID);
|
|
|
1171
|
|
|
1172 // The machine scheduler may accidentally create disconnected components
|
|
|
1173 // when moving subregister definitions around, avoid this by splitting them to
|
|
|
1174 // separate vregs before. Splitting can also improve reg. allocation quality.
|
|
|
1175 addPass(&RenameIndependentSubregsID);
|
|
|
1176
|
|
|
1177 // PreRA instruction scheduling.
|
|
|
1178 addPass(&MachineSchedulerID);
|
|
|
1179
|
|
|
1180 if (addRegAssignmentOptimized()) {
|
|
|
1181 // Allow targets to expand pseudo instructions depending on the choice of
|
|
|
1182 // registers before MachineCopyPropagation.
|
|
|
1183 addPostRewrite();
|
|
|
1184
|
|
|
1185 // Copy propagate to forward register uses and try to eliminate COPYs that
|
|
|
1186 // were not coalesced.
|
|
|
1187 addPass(&MachineCopyPropagationID);
|
|
|
1188
|
|
|
1189 // Run post-ra machine LICM to hoist reloads / remats.
|
|
|
1190 //
|
|
|
1191 // FIXME: can this move into MachineLateOptimization?
|
|
|
1192 addPass(&MachineLICMID);
|
|
|
1193 }
|
|
|
1194 }
|
|
|
1195
|
|
|
1196 //===---------------------------------------------------------------------===//
|
|
|
1197 /// Post RegAlloc Pass Configuration
|
|
|
1198 //===---------------------------------------------------------------------===//
|
|
|
1199
|
|
|
1200 /// Add passes that optimize machine instructions after register allocation.
|
|
|
1201 void TargetPassConfig::addMachineLateOptimization() {
|
|
|
1202 // Branch folding must be run after regalloc and prolog/epilog insertion.
|
|
|
1203 addPass(&BranchFolderPassID);
|
|
|
1204
|
|
|
1205 // Tail duplication.
|
|
|
1206 // Note that duplicating tail just increases code size and degrades
|
|
|
1207 // performance for targets that require Structured Control Flow.
|
|
|
1208 // In addition it can also make CFG irreducible. Thus we disable it.
|
|
|
1209 if (!TM->requiresStructuredCFG())
|
|
|
1210 addPass(&TailDuplicateID);
|
|
|
1211
|
|
|
1212 // Copy propagation.
|
|
|
1213 addPass(&MachineCopyPropagationID);
|
|
|
1214 }
|
|
|
1215
|
|
|
1216 /// Add standard GC passes.
|
|
|
1217 bool TargetPassConfig::addGCPasses() {
|
|
|
1218 addPass(&GCMachineCodeAnalysisID, false);
|
|
|
1219 return true;
|
|
|
1220 }
|
|
|
1221
|
|
|
1222 /// Add standard basic block placement passes.
|
|
|
1223 void TargetPassConfig::addBlockPlacement() {
|
|
|
1224 if (addPass(&MachineBlockPlacementID)) {
|
|
|
1225 // Run a separate pass to collect block placement statistics.
|
|
|
1226 if (EnableBlockPlacementStats)
|
|
|
1227 addPass(&MachineBlockPlacementStatsID);
|
|
|
1228 }
|
|
|
1229 }
|
|
|
1230
|
|
|
1231 //===---------------------------------------------------------------------===//
|
|
|
1232 /// GlobalISel Configuration
|
|
|
1233 //===---------------------------------------------------------------------===//
|
|
|
1234 bool TargetPassConfig::isGlobalISelAbortEnabled() const {
|
|
|
1235 return TM->Options.GlobalISelAbort == GlobalISelAbortMode::Enable;
|
|
|
1236 }
|
|
|
1237
|
|
|
1238 bool TargetPassConfig::reportDiagnosticWhenGlobalISelFallback() const {
|
|
|
1239 return TM->Options.GlobalISelAbort == GlobalISelAbortMode::DisableWithDiag;
|
|
|
1240 }
|
|
|
1241
|
|
|
1242 bool TargetPassConfig::isGISelCSEEnabled() const {
|
|
|
1243 return true;
|
|
|
1244 }
|
|
|
1245
|
|
|
1246 std::unique_ptr<CSEConfigBase> TargetPassConfig::getCSEConfig() const {
|
|
|
1247 return std::make_unique<CSEConfigBase>();
|
|
|
1248 }
|
