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annotate source/mmu.c @ 0:c450faca55f4

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author Tatsuki IHA <innparusu@cr.ie.u-ryukyu.ac.jp>
date Sun, 22 Oct 2017 18:25:39 +0900
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children
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Tatsuki IHA <innparusu@cr.ie.u-ryukyu.ac.jp>
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1 /*****************************************************************
Tatsuki IHA <innparusu@cr.ie.u-ryukyu.ac.jp>
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2 * mmu.c
Tatsuki IHA <innparusu@cr.ie.u-ryukyu.ac.jp>
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3 * by Zhiyi Huang, hzy@cs.otago.ac.nz
Tatsuki IHA <innparusu@cr.ie.u-ryukyu.ac.jp>
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4 * University of Otago
Tatsuki IHA <innparusu@cr.ie.u-ryukyu.ac.jp>
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5 *
Tatsuki IHA <innparusu@cr.ie.u-ryukyu.ac.jp>
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6 ********************************************************************/
Tatsuki IHA <innparusu@cr.ie.u-ryukyu.ac.jp>
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7
Tatsuki IHA <innparusu@cr.ie.u-ryukyu.ac.jp>
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8
Tatsuki IHA <innparusu@cr.ie.u-ryukyu.ac.jp>
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9 #include "types.h"
Tatsuki IHA <innparusu@cr.ie.u-ryukyu.ac.jp>
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10 #include "defs.h"
Tatsuki IHA <innparusu@cr.ie.u-ryukyu.ac.jp>
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11 #include "memlayout.h"
Tatsuki IHA <innparusu@cr.ie.u-ryukyu.ac.jp>
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12 #include "mmu.h"
Tatsuki IHA <innparusu@cr.ie.u-ryukyu.ac.jp>
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13
Tatsuki IHA <innparusu@cr.ie.u-ryukyu.ac.jp>
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14 void mmuinit0(void)
Tatsuki IHA <innparusu@cr.ie.u-ryukyu.ac.jp>
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15 {
Tatsuki IHA <innparusu@cr.ie.u-ryukyu.ac.jp>
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16 pde_t *l1;
Tatsuki IHA <innparusu@cr.ie.u-ryukyu.ac.jp>
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17 pte_t *l2;
Tatsuki IHA <innparusu@cr.ie.u-ryukyu.ac.jp>
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18 uint pa, va, *p;
Tatsuki IHA <innparusu@cr.ie.u-ryukyu.ac.jp>
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19
Tatsuki IHA <innparusu@cr.ie.u-ryukyu.ac.jp>
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20 // diable mmu
Tatsuki IHA <innparusu@cr.ie.u-ryukyu.ac.jp>
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21 // use inline assembly here as there is a limit on
Tatsuki IHA <innparusu@cr.ie.u-ryukyu.ac.jp>
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22 // branch distance after mmu is disabled
Tatsuki IHA <innparusu@cr.ie.u-ryukyu.ac.jp>
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23 asm volatile("mrc p15, 0, r1, c1, c0, 0\n\t"
Tatsuki IHA <innparusu@cr.ie.u-ryukyu.ac.jp>
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24 "bic r1,r1,#0x00000004\n\t"
Tatsuki IHA <innparusu@cr.ie.u-ryukyu.ac.jp>
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25 "bic r1,r1,#0x00001000\n\t"
Tatsuki IHA <innparusu@cr.ie.u-ryukyu.ac.jp>
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26 "bic r1,r1,#0x00000800\n\t"
Tatsuki IHA <innparusu@cr.ie.u-ryukyu.ac.jp>
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27 "bic r1,r1,#0x00000001\n\t"
Tatsuki IHA <innparusu@cr.ie.u-ryukyu.ac.jp>
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28 "mcr p15, 0, r1, c1, c0, 0\n\t"
Tatsuki IHA <innparusu@cr.ie.u-ryukyu.ac.jp>
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29 "mov r0, #0\n\t"
Tatsuki IHA <innparusu@cr.ie.u-ryukyu.ac.jp>
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30 "mcr p15, 0, r0, c7, c7, 0\n\t"
Tatsuki IHA <innparusu@cr.ie.u-ryukyu.ac.jp>
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31 "mcr p15, 0, r0, c8, c7, 0\n\t"
Tatsuki IHA <innparusu@cr.ie.u-ryukyu.ac.jp>
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32 ::: "r0", "r1", "cc", "memory");
Tatsuki IHA <innparusu@cr.ie.u-ryukyu.ac.jp>
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33
Tatsuki IHA <innparusu@cr.ie.u-ryukyu.ac.jp>
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34
Tatsuki IHA <innparusu@cr.ie.u-ryukyu.ac.jp>
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35 for(p=(uint *)0x2000; p<(uint *)0x8000; p++) *p = 0;
Tatsuki IHA <innparusu@cr.ie.u-ryukyu.ac.jp>
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36
Tatsuki IHA <innparusu@cr.ie.u-ryukyu.ac.jp>
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37 l1 = (pde_t *) K_PDX_BASE;
Tatsuki IHA <innparusu@cr.ie.u-ryukyu.ac.jp>
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38 l2 = (pte_t *) K_PTX_BASE;
Tatsuki IHA <innparusu@cr.ie.u-ryukyu.ac.jp>
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39
Tatsuki IHA <innparusu@cr.ie.u-ryukyu.ac.jp>
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40 // map all of ram at KERNBASE
Tatsuki IHA <innparusu@cr.ie.u-ryukyu.ac.jp>
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41 va = KERNBASE;
Tatsuki IHA <innparusu@cr.ie.u-ryukyu.ac.jp>
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42 for(pa = PA_START; pa < PA_START+RAMSIZE; pa += MBYTE){
Tatsuki IHA <innparusu@cr.ie.u-ryukyu.ac.jp>
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43 l1[PDX(va)] = pa|DOMAIN0|PDX_AP(K_RW)|SECTION|CACHED|BUFFERED;
Tatsuki IHA <innparusu@cr.ie.u-ryukyu.ac.jp>
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44 va += MBYTE;
Tatsuki IHA <innparusu@cr.ie.u-ryukyu.ac.jp>
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45 }
Tatsuki IHA <innparusu@cr.ie.u-ryukyu.ac.jp>
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46
Tatsuki IHA <innparusu@cr.ie.u-ryukyu.ac.jp>
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47 // identity map first MB of ram so mmu can be enabled
Tatsuki IHA <innparusu@cr.ie.u-ryukyu.ac.jp>
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48 l1[PDX(PA_START)] = PA_START|DOMAIN0|PDX_AP(K_RW)|SECTION|CACHED|BUFFERED;
Tatsuki IHA <innparusu@cr.ie.u-ryukyu.ac.jp>
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49
Tatsuki IHA <innparusu@cr.ie.u-ryukyu.ac.jp>
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50 // map IO region
Tatsuki IHA <innparusu@cr.ie.u-ryukyu.ac.jp>
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51 va = DEVSPACE;
Tatsuki IHA <innparusu@cr.ie.u-ryukyu.ac.jp>
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52 for(pa = PHYSIO; pa < PHYSIO+IOSIZE; pa += MBYTE){
Tatsuki IHA <innparusu@cr.ie.u-ryukyu.ac.jp>
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53 l1[PDX(va)] = pa|DOMAIN0|PDX_AP(K_RW)|SECTION;
Tatsuki IHA <innparusu@cr.ie.u-ryukyu.ac.jp>
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54 va += MBYTE;
Tatsuki IHA <innparusu@cr.ie.u-ryukyu.ac.jp>
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55 }
Tatsuki IHA <innparusu@cr.ie.u-ryukyu.ac.jp>
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56
Tatsuki IHA <innparusu@cr.ie.u-ryukyu.ac.jp>
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57 // map GPU memory
Tatsuki IHA <innparusu@cr.ie.u-ryukyu.ac.jp>
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58 va = GPUMEMBASE;
Tatsuki IHA <innparusu@cr.ie.u-ryukyu.ac.jp>
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59 for(pa = GPUMEMBASE; pa < (uint)GPUMEMBASE+(uint)GPUMEMSIZE; pa += MBYTE){
Tatsuki IHA <innparusu@cr.ie.u-ryukyu.ac.jp>
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60 l1[PDX(va)] = pa|DOMAIN0|PDX_AP(K_RW)|SECTION;
Tatsuki IHA <innparusu@cr.ie.u-ryukyu.ac.jp>
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61 va += MBYTE;
Tatsuki IHA <innparusu@cr.ie.u-ryukyu.ac.jp>
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62 }
Tatsuki IHA <innparusu@cr.ie.u-ryukyu.ac.jp>
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63
Tatsuki IHA <innparusu@cr.ie.u-ryukyu.ac.jp>
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64 // double map exception vectors at top of virtual memory
Tatsuki IHA <innparusu@cr.ie.u-ryukyu.ac.jp>
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65 va = HVECTORS;
Tatsuki IHA <innparusu@cr.ie.u-ryukyu.ac.jp>
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66 l1[PDX(va)] = (uint)l2|DOMAIN0|COARSE;
Tatsuki IHA <innparusu@cr.ie.u-ryukyu.ac.jp>
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67 l2[PTX(va)] = PA_START|PTX_AP(K_RW)|SMALL;
Tatsuki IHA <innparusu@cr.ie.u-ryukyu.ac.jp>
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68
Tatsuki IHA <innparusu@cr.ie.u-ryukyu.ac.jp>
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69
Tatsuki IHA <innparusu@cr.ie.u-ryukyu.ac.jp>
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70 asm volatile("mov r1, #1\n\t"
Tatsuki IHA <innparusu@cr.ie.u-ryukyu.ac.jp>
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71 "mcr p15, 0, r1, c3, c0\n\t"
Tatsuki IHA <innparusu@cr.ie.u-ryukyu.ac.jp>
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72 "mov r1, #0x4000\n\t"
Tatsuki IHA <innparusu@cr.ie.u-ryukyu.ac.jp>
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73 "mcr p15, 0, r1, c2, c0\n\t"
Tatsuki IHA <innparusu@cr.ie.u-ryukyu.ac.jp>
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74 "mrc p15, 0, r0, c1, c0, 0\n\t"
Tatsuki IHA <innparusu@cr.ie.u-ryukyu.ac.jp>
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75 "mov r1, #0x00002000\n\t"
Tatsuki IHA <innparusu@cr.ie.u-ryukyu.ac.jp>
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76 "orr r1, #0x00000004\n\t"
Tatsuki IHA <innparusu@cr.ie.u-ryukyu.ac.jp>
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77 "orr r1, #0x00001000\n\t"
Tatsuki IHA <innparusu@cr.ie.u-ryukyu.ac.jp>
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78 "orr r1, #0x00000001\n\t"
Tatsuki IHA <innparusu@cr.ie.u-ryukyu.ac.jp>
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79 "orr r0, r1\n\t"
Tatsuki IHA <innparusu@cr.ie.u-ryukyu.ac.jp>
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80 "mcr p15, 0, r0, c1, c0, 0\n\t"
Tatsuki IHA <innparusu@cr.ie.u-ryukyu.ac.jp>
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81 "mov r1, #1\n\t"
Tatsuki IHA <innparusu@cr.ie.u-ryukyu.ac.jp>
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82 "mcr p15, 0, r1, c15, c12, 0\n\t"
Tatsuki IHA <innparusu@cr.ie.u-ryukyu.ac.jp>
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83 ::: "r0", "r1", "cc", "memory");
Tatsuki IHA <innparusu@cr.ie.u-ryukyu.ac.jp>
parents:
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84
Tatsuki IHA <innparusu@cr.ie.u-ryukyu.ac.jp>
parents:
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85 }
Tatsuki IHA <innparusu@cr.ie.u-ryukyu.ac.jp>
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86
Tatsuki IHA <innparusu@cr.ie.u-ryukyu.ac.jp>
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87 void
Tatsuki IHA <innparusu@cr.ie.u-ryukyu.ac.jp>
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88 mmuinit1(void)
Tatsuki IHA <innparusu@cr.ie.u-ryukyu.ac.jp>
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89 {
Tatsuki IHA <innparusu@cr.ie.u-ryukyu.ac.jp>
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90 pde_t *l1;
Tatsuki IHA <innparusu@cr.ie.u-ryukyu.ac.jp>
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91 uint va1, va2;
Tatsuki IHA <innparusu@cr.ie.u-ryukyu.ac.jp>
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92
Tatsuki IHA <innparusu@cr.ie.u-ryukyu.ac.jp>
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93 l1 = (pde_t*)(K_PDX_BASE);
Tatsuki IHA <innparusu@cr.ie.u-ryukyu.ac.jp>
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94
Tatsuki IHA <innparusu@cr.ie.u-ryukyu.ac.jp>
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95 // undo identity map of first MB of ram
Tatsuki IHA <innparusu@cr.ie.u-ryukyu.ac.jp>
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96 l1[PDX(PA_START)] = 0;
Tatsuki IHA <innparusu@cr.ie.u-ryukyu.ac.jp>
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97
Tatsuki IHA <innparusu@cr.ie.u-ryukyu.ac.jp>
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98 // drain write buffer; writeback data cache range [va, va+n]
Tatsuki IHA <innparusu@cr.ie.u-ryukyu.ac.jp>
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99 va1 = (uint)&l1[PDX(PA_START)];
Tatsuki IHA <innparusu@cr.ie.u-ryukyu.ac.jp>
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100 va2 = va1 + sizeof(pde_t);
Tatsuki IHA <innparusu@cr.ie.u-ryukyu.ac.jp>
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101 va1 = va1 & ~((uint)CACHELINESIZE-1);
Tatsuki IHA <innparusu@cr.ie.u-ryukyu.ac.jp>
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102 va2 = va2 & ~((uint)CACHELINESIZE-1);
Tatsuki IHA <innparusu@cr.ie.u-ryukyu.ac.jp>
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103 flush_dcache(va1, va2);
Tatsuki IHA <innparusu@cr.ie.u-ryukyu.ac.jp>
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104
Tatsuki IHA <innparusu@cr.ie.u-ryukyu.ac.jp>
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105 // invalidate TLB; DSB barrier used
Tatsuki IHA <innparusu@cr.ie.u-ryukyu.ac.jp>
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106 flush_tlb();
Tatsuki IHA <innparusu@cr.ie.u-ryukyu.ac.jp>
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107
Tatsuki IHA <innparusu@cr.ie.u-ryukyu.ac.jp>
parents:
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108 }
Tatsuki IHA <innparusu@cr.ie.u-ryukyu.ac.jp>
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109