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1 /* 6809 Simulator V09.
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2
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3 created 1994,1995 by L.C. Benschop.
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4 copyleft (c) 1994-2014 by the sbc09 team, see AUTHORS for more details.
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5 license: GNU General Public License version 2, see LICENSE for more details.
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6
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7 This program simulates a 6809 processor.
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8
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9 System dependencies: short must be 16 bits.
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10 char must be 8 bits.
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11 long must be more than 16 bits.
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12 arrays up to 65536 bytes must be supported.
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13 machine must be twos complement.
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14 Most Unix machines will work. For MSODS you need long pointers
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15 and you may have to malloc() the mem array of 65536 bytes.
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16
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17 Special instructions:
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18 SWI2 writes char to stdout from register B.
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19 SWI3 reads char from stdout to register B, sets carry at EOF.
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20 (or when no key available when using term control).
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21 SWI retains its normal function.
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22 CWAI and SYNC stop simulator.
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23 Note: special instructions are gone for now.
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24
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25 ACIA emulation at port $E000
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26
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27 Note: BIG_ENDIAN option is no longer needed.
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28 */
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29
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30 #include <stdio.h>
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31 #include <unistd.h>
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32
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33 #define engine
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34 #include "v09.h"
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35
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36 #define USLEEP 1000
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37 Byte aca,acb;
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38 Byte *breg=&aca,*areg=&acb;
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39 static int tracetrick=0;
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40 extern int romstart;
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41
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42 #define GETWORD(a) (mem[a]<<8|mem[(a)+1])
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43 #define SETBYTE(a,n) {if(!(a>=romstart))mem[a]=n;}
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44 #define SETWORD(a,n) if(!(a>=romstart)){mem[a]=(n)>>8;mem[(a)+1]=n;}
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45 /* Two bytes of a word are fetched separately because of
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46 the possible wrap-around at address $ffff and alignment
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47 */
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48
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49 #define IMMBYTE(b) b=mem[ipcreg++];
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50 #define IMMWORD(w) {w=GETWORD(ipcreg);ipcreg+=2;}
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51
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52 #define PUSHBYTE(b) {--isreg;SETBYTE(isreg,b)}
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53 #define PUSHWORD(w) {isreg-=2;SETWORD(isreg,w)}
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54 #define PULLBYTE(b) b=mem[isreg++];
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55 #define PULLWORD(w) {w=GETWORD(isreg);isreg+=2;}
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56 #define PSHUBYTE(b) {--iureg;SETBYTE(iureg,b)}
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57 #define PSHUWORD(w) {iureg-=2;SETWORD(iureg,w)}
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58 #define PULUBYTE(b) b=mem[iureg++];
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59 #define PULUWORD(w) {w=GETWORD(iureg);iureg+=2;}
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60
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61 #define SIGNED(b) ((Word)(b&0x80?b|0xff00:b))
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62
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63 #define GETDREG ((iareg<<8)|ibreg)
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64 #define SETDREG(n) {iareg=(n)>>8;ibreg=(n);}
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65
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66 /* Macros for addressing modes (postbytes have their own code) */
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67 #define DIRECT {IMMBYTE(eaddr) eaddr|=(idpreg<<8);}
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68 #define IMM8 {eaddr=ipcreg++;}
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69 #define IMM16 {eaddr=ipcreg;ipcreg+=2;}
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70 #define EXTENDED {IMMWORD(eaddr)}
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71
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72 /* macros to set status flags */
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73 #define SEC iccreg|=0x01;
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74 #define CLC iccreg&=0xfe;
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75 #define SEZ iccreg|=0x04;
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76 #define CLZ iccreg&=0xfb;
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77 #define SEN iccreg|=0x08;
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78 #define CLN iccreg&=0xf7;
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79 #define SEV iccreg|=0x02;
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80 #define CLV iccreg&=0xfd;
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81 #define SEH iccreg|=0x20;
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82 #define CLH iccreg&=0xdf;
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83
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84 /* set N and Z flags depending on 8 or 16 bit result */
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85 #define SETNZ8(b) {if(b)CLZ else SEZ if(b&0x80)SEN else CLN}
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86 #define SETNZ16(b) {if(b)CLZ else SEZ if(b&0x8000)SEN else CLN}
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87
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88 #define SETSTATUS(a,b,res) if((a^b^res)&0x10) SEH else CLH \
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89 if((a^b^res^(res>>1))&0x80)SEV else CLV \
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90 if(res&0x100)SEC else CLC SETNZ8((Byte)res)
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91
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92 #define SETSTATUSD(a,b,res) {if(res&0x10000) SEC else CLC \
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93 if(((res>>1)^a^b^res)&0x8000) SEV else CLV \
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94 SETNZ16((Word)res)}
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95
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96 /* Macros for branch instructions */
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97 #define BRANCH(f) if(!iflag){IMMBYTE(tb) if(f)ipcreg+=SIGNED(tb);}\
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98 else{IMMWORD(tw) if(f)ipcreg+=tw;}
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99 #define NXORV ((iccreg&0x08)^((iccreg&0x02)<<2))
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100
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101 /* MAcros for setting/getting registers in TFR/EXG instructions */
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102 #define GETREG(val,reg) switch(reg) {\
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103 case 0: val=GETDREG;break;\
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104 case 1: val=ixreg;break;\
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105 case 2: val=iyreg;break;\
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106 case 3: val=iureg;break;\
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107 case 4: val=isreg;break;\
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108 case 5: val=ipcreg;break;\
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109 case 8: val=iareg;break;\
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110 case 9: val=ibreg;break;\
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111 case 10: val=iccreg;break;\
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112 case 11: val=idpreg;break;}
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113
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114 #define SETREG(val,reg) switch(reg) {\
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115 case 0: SETDREG(val) break;\
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116 case 1: ixreg=val;break;\
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117 case 2: iyreg=val;break;\
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118 case 3: iureg=val;break;\
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119 case 4: isreg=val;break;\
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120 case 5: ipcreg=val;break;\
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121 case 8: iareg=val;break;\
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122 case 9: ibreg=val;break;\
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123 case 10: iccreg=val;break;\
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124 case 11: idpreg=val;break;}
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125
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126 /* Macros for load and store of accumulators. Can be modified to check
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127 for port addresses */
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128 #define LOADAC(reg) if((eaddr&0xff00)!=IOPAGE)reg=mem[eaddr];else\
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129 reg=do_input(eaddr&0xff);
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130 #define STOREAC(reg) if((eaddr&0xff00)!=IOPAGE)SETBYTE(eaddr,reg)else\
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131 do_output(eaddr&0xff,reg);
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132
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133 #define LOADREGS ixreg=xreg;iyreg=yreg;\
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134 iureg=ureg;isreg=sreg;\
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135 ipcreg=pcreg;\
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136 iareg=*areg;ibreg=*breg;\
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137 idpreg=dpreg;iccreg=ccreg;
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138
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139 #define SAVEREGS xreg=ixreg;yreg=iyreg;\
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140 ureg=iureg;sreg=isreg;\
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141 pcreg=ipcreg;\
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142 *areg=iareg;*breg=ibreg;\
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143 dpreg=idpreg;ccreg=iccreg;
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144
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145
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146 unsigned char haspostbyte[] = {
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147 /*0*/ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,
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148 /*1*/ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,
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149 /*2*/ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,
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150 /*3*/ 1,1,1,1,0,0,0,0,0,0,0,0,0,0,0,0,
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151 /*4*/ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,
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152 /*5*/ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,
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153 /*6*/ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,
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154 /*7*/ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,
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155 /*8*/ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,
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156 /*9*/ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,
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157 /*A*/ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,
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158 /*B*/ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,
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159 /*C*/ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,
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160 /*D*/ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,
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161 /*E*/ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,
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162 /*F*/ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,
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163 };
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164
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165 void interpr(void)
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166 {
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167 Word ixreg,iyreg,iureg,isreg,ipcreg;
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168 Byte idpreg,iccreg,iareg,ibreg;
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169 /* Make local variables for the registers. On a real processor (non-Intel)
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170 these could be implemented as fast registers. */
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171 Word eaddr; /* effective address */
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172 Byte ireg; /* instruction register */
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173 Byte iflag; /* flag to indicate $10 or $11 prebyte */
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174 Byte tb;Word tw;
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175 LOADREGS
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176 for(;;){
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177 if(attention) {
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178 if(tracing && ipcreg>=tracelo && ipcreg<=tracehi)
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179 {SAVEREGS do_trace(tracefile); }
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180 if(escape){ SAVEREGS do_escape(); LOADREGS }
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181 if(irq) {
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182 if(irq==1&&!(iccreg&0x10)) { /* standard IRQ */
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183 PUSHWORD(ipcreg)
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184 PUSHWORD(iureg)
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185 PUSHWORD(iyreg)
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186 PUSHWORD(ixreg)
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187 PUSHBYTE(idpreg)
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188 PUSHBYTE(ibreg)
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189 PUSHBYTE(iareg)
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190 PUSHBYTE(iccreg)
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191 iccreg|=0x90;
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192 ipcreg=GETWORD(0xfff8);
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193 }
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194 if(irq==2&&!(iccreg&0x40)) { /* Fast IRQ */
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195 PUSHWORD(ipcreg)
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196 PUSHBYTE(iccreg)
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197 iccreg&=0x7f;
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198 iccreg|=0x50;
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199 ipcreg=GETWORD(0xfff6);
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200 }
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201 if(!tracing)attention=0;
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202 irq=0;
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203 }
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204 }
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205 iflag=0;
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206 flaginstr: /* $10 and $11 instructions return here */
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207 ireg=mem[ipcreg++];
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208 if(haspostbyte[ireg]) {
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209 Byte postbyte=mem[ipcreg++];
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210 switch(postbyte) {
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211 case 0x00: eaddr=ixreg;break;
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212 case 0x01: eaddr=ixreg+1;break;
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213 case 0x02: eaddr=ixreg+2;break;
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214 case 0x03: eaddr=ixreg+3;break;
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215 case 0x04: eaddr=ixreg+4;break;
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216 case 0x05: eaddr=ixreg+5;break;
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217 case 0x06: eaddr=ixreg+6;break;
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218 case 0x07: eaddr=ixreg+7;break;
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219 case 0x08: eaddr=ixreg+8;break;
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220 case 0x09: eaddr=ixreg+9;break;
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221 case 0x0A: eaddr=ixreg+10;break;
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222 case 0x0B: eaddr=ixreg+11;break;
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223 case 0x0C: eaddr=ixreg+12;break;
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224 case 0x0D: eaddr=ixreg+13;break;
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225 case 0x0E: eaddr=ixreg+14;break;
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226 case 0x0F: eaddr=ixreg+15;break;
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227 case 0x10: eaddr=ixreg-16;break;
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228 case 0x11: eaddr=ixreg-15;break;
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229 case 0x12: eaddr=ixreg-14;break;
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230 case 0x13: eaddr=ixreg-13;break;
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231 case 0x14: eaddr=ixreg-12;break;
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232 case 0x15: eaddr=ixreg-11;break;
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233 case 0x16: eaddr=ixreg-10;break;
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234 case 0x17: eaddr=ixreg-9;break;
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235 case 0x18: eaddr=ixreg-8;break;
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236 case 0x19: eaddr=ixreg-7;break;
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237 case 0x1A: eaddr=ixreg-6;break;
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238 case 0x1B: eaddr=ixreg-5;break;
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239 case 0x1C: eaddr=ixreg-4;break;
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240 case 0x1D: eaddr=ixreg-3;break;
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241 case 0x1E: eaddr=ixreg-2;break;
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242 case 0x1F: eaddr=ixreg-1;break;
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243 case 0x20: eaddr=iyreg;break;
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244 case 0x21: eaddr=iyreg+1;break;
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245 case 0x22: eaddr=iyreg+2;break;
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246 case 0x23: eaddr=iyreg+3;break;
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247 case 0x24: eaddr=iyreg+4;break;
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248 case 0x25: eaddr=iyreg+5;break;
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249 case 0x26: eaddr=iyreg+6;break;
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250 case 0x27: eaddr=iyreg+7;break;
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251 case 0x28: eaddr=iyreg+8;break;
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252 case 0x29: eaddr=iyreg+9;break;
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253 case 0x2A: eaddr=iyreg+10;break;
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254 case 0x2B: eaddr=iyreg+11;break;
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255 case 0x2C: eaddr=iyreg+12;break;
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256 case 0x2D: eaddr=iyreg+13;break;
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257 case 0x2E: eaddr=iyreg+14;break;
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258 case 0x2F: eaddr=iyreg+15;break;
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259 case 0x30: eaddr=iyreg-16;break;
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260 case 0x31: eaddr=iyreg-15;break;
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261 case 0x32: eaddr=iyreg-14;break;
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262 case 0x33: eaddr=iyreg-13;break;
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263 case 0x34: eaddr=iyreg-12;break;
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264 case 0x35: eaddr=iyreg-11;break;
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265 case 0x36: eaddr=iyreg-10;break;
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266 case 0x37: eaddr=iyreg-9;break;
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267 case 0x38: eaddr=iyreg-8;break;
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268 case 0x39: eaddr=iyreg-7;break;
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269 case 0x3A: eaddr=iyreg-6;break;
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270 case 0x3B: eaddr=iyreg-5;break;
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271 case 0x3C: eaddr=iyreg-4;break;
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272 case 0x3D: eaddr=iyreg-3;break;
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273 case 0x3E: eaddr=iyreg-2;break;
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274 case 0x3F: eaddr=iyreg-1;break;
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275 case 0x40: eaddr=iureg;break;
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276 case 0x41: eaddr=iureg+1;break;
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277 case 0x42: eaddr=iureg+2;break;
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278 case 0x43: eaddr=iureg+3;break;
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279 case 0x44: eaddr=iureg+4;break;
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280 case 0x45: eaddr=iureg+5;break;
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281 case 0x46: eaddr=iureg+6;break;
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282 case 0x47: eaddr=iureg+7;break;
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283 case 0x48: eaddr=iureg+8;break;
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284 case 0x49: eaddr=iureg+9;break;
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285 case 0x4A: eaddr=iureg+10;break;
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286 case 0x4B: eaddr=iureg+11;break;
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287 case 0x4C: eaddr=iureg+12;break;
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288 case 0x4D: eaddr=iureg+13;break;
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289 case 0x4E: eaddr=iureg+14;break;
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290 case 0x4F: eaddr=iureg+15;break;
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291 case 0x50: eaddr=iureg-16;break;
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292 case 0x51: eaddr=iureg-15;break;
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293 case 0x52: eaddr=iureg-14;break;
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294 case 0x53: eaddr=iureg-13;break;
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295 case 0x54: eaddr=iureg-12;break;
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296 case 0x55: eaddr=iureg-11;break;
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297 case 0x56: eaddr=iureg-10;break;
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298 case 0x57: eaddr=iureg-9;break;
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299 case 0x58: eaddr=iureg-8;break;
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300 case 0x59: eaddr=iureg-7;break;
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301 case 0x5A: eaddr=iureg-6;break;
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302 case 0x5B: eaddr=iureg-5;break;
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303 case 0x5C: eaddr=iureg-4;break;
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304 case 0x5D: eaddr=iureg-3;break;
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305 case 0x5E: eaddr=iureg-2;break;
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306 case 0x5F: eaddr=iureg-1;break;
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307 case 0x60: eaddr=isreg;break;
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308 case 0x61: eaddr=isreg+1;break;
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309 case 0x62: eaddr=isreg+2;break;
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310 case 0x63: eaddr=isreg+3;break;
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311 case 0x64: eaddr=isreg+4;break;
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312 case 0x65: eaddr=isreg+5;break;
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313 case 0x66: eaddr=isreg+6;break;
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314 case 0x67: eaddr=isreg+7;break;
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315 case 0x68: eaddr=isreg+8;break;
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316 case 0x69: eaddr=isreg+9;break;
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317 case 0x6A: eaddr=isreg+10;break;
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318 case 0x6B: eaddr=isreg+11;break;
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319 case 0x6C: eaddr=isreg+12;break;
|
|
|
320 case 0x6D: eaddr=isreg+13;break;
|
|
|
321 case 0x6E: eaddr=isreg+14;break;
|
|
|
322 case 0x6F: eaddr=isreg+15;break;
|
|
|
323 case 0x70: eaddr=isreg-16;break;
|
|
|
324 case 0x71: eaddr=isreg-15;break;
|
|
|
325 case 0x72: eaddr=isreg-14;break;
|
|
|
326 case 0x73: eaddr=isreg-13;break;
|
|
|
327 case 0x74: eaddr=isreg-12;break;
|
|
|
328 case 0x75: eaddr=isreg-11;break;
|
|
|
329 case 0x76: eaddr=isreg-10;break;
|
|
|
330 case 0x77: eaddr=isreg-9;break;
|
|
|
331 case 0x78: eaddr=isreg-8;break;
|
|
|
332 case 0x79: eaddr=isreg-7;break;
|
|
|
333 case 0x7A: eaddr=isreg-6;break;
|
|
|
334 case 0x7B: eaddr=isreg-5;break;
|
|
|
335 case 0x7C: eaddr=isreg-4;break;
|
|
|
336 case 0x7D: eaddr=isreg-3;break;
|
|
|
337 case 0x7E: eaddr=isreg-2;break;
|
|
|
338 case 0x7F: eaddr=isreg-1;break;
|
|
|
339 case 0x80: eaddr=ixreg;ixreg++;break;
|
|
|
340 case 0x81: eaddr=ixreg;ixreg+=2;break;
|
|
|
341 case 0x82: ixreg--;eaddr=ixreg;break;
|
|
|
342 case 0x83: ixreg-=2;eaddr=ixreg;break;
|
|
|
343 case 0x84: eaddr=ixreg;break;
|
|
|
344 case 0x85: eaddr=ixreg+SIGNED(ibreg);break;
|
|
|
345 case 0x86: eaddr=ixreg+SIGNED(iareg);break;
|
|
|
346 case 0x87: eaddr=0;break; /*ILELGAL*/
|
|
|
347 case 0x88: IMMBYTE(eaddr);eaddr=ixreg+SIGNED(eaddr);break;
|
|
|
348 case 0x89: IMMWORD(eaddr);eaddr+=ixreg;break;
|
|
|
349 case 0x8A: eaddr=0;break; /*ILLEGAL*/
|
|
|
350 case 0x8B: eaddr=ixreg+GETDREG;break;
|
|
|
351 case 0x8C: IMMBYTE(eaddr);eaddr=ipcreg+SIGNED(eaddr);break;
|
|
|
352 case 0x8D: IMMWORD(eaddr);eaddr+=ipcreg;break;
|
|
|
353 case 0x8E: eaddr=0;break; /*ILLEGAL*/
|
|
|
354 case 0x8F: IMMWORD(eaddr);break;
|
|
|
355 case 0x90: eaddr=ixreg;ixreg++;eaddr=GETWORD(eaddr);break;
|
|
|
356 case 0x91: eaddr=ixreg;ixreg+=2;eaddr=GETWORD(eaddr);break;
|
|
|
357 case 0x92: ixreg--;eaddr=ixreg;eaddr=GETWORD(eaddr);break;
|
|
|
358 case 0x93: ixreg-=2;eaddr=ixreg;eaddr=GETWORD(eaddr);break;
|
|
|
359 case 0x94: eaddr=ixreg;eaddr=GETWORD(eaddr);break;
|
|
|
360 case 0x95: eaddr=ixreg+SIGNED(ibreg);eaddr=GETWORD(eaddr);break;
|
|
|
361 case 0x96: eaddr=ixreg+SIGNED(iareg);eaddr=GETWORD(eaddr);break;
|
|
|
362 case 0x97: eaddr=0;break; /*ILELGAL*/
|
|
|
363 case 0x98: IMMBYTE(eaddr);eaddr=ixreg+SIGNED(eaddr);
|
|
|
364 eaddr=GETWORD(eaddr);break;
|
|
|
365 case 0x99: IMMWORD(eaddr);eaddr+=ixreg;eaddr=GETWORD(eaddr);break;
|
|
|
366 case 0x9A: eaddr=0;break; /*ILLEGAL*/
|
|
|
367 case 0x9B: eaddr=ixreg+GETDREG;eaddr=GETWORD(eaddr);break;
|
|
|
368 case 0x9C: IMMBYTE(eaddr);eaddr=ipcreg+SIGNED(eaddr);
|
|
|
369 eaddr=GETWORD(eaddr);break;
|
|
|
370 case 0x9D: IMMWORD(eaddr);eaddr+=ipcreg;eaddr=GETWORD(eaddr);break;
|
|
|
371 case 0x9E: eaddr=0;break; /*ILLEGAL*/
|
|
|
372 case 0x9F: IMMWORD(eaddr);eaddr=GETWORD(eaddr);break;
|
|
|
373 case 0xA0: eaddr=iyreg;iyreg++;break;
|
|
|
374 case 0xA1: eaddr=iyreg;iyreg+=2;break;
|
|
|
375 case 0xA2: iyreg--;eaddr=iyreg;break;
|
|
|
376 case 0xA3: iyreg-=2;eaddr=iyreg;break;
|
|
|
377 case 0xA4: eaddr=iyreg;break;
|
|
|
378 case 0xA5: eaddr=iyreg+SIGNED(ibreg);break;
|
|
|
379 case 0xA6: eaddr=iyreg+SIGNED(iareg);break;
|
|
|
380 case 0xA7: eaddr=0;break; /*ILELGAL*/
|
|
|
381 case 0xA8: IMMBYTE(eaddr);eaddr=iyreg+SIGNED(eaddr);break;
|
|
|
382 case 0xA9: IMMWORD(eaddr);eaddr+=iyreg;break;
|
|
|
383 case 0xAA: eaddr=0;break; /*ILLEGAL*/
|
|
|
384 case 0xAB: eaddr=iyreg+GETDREG;break;
|
|
|
385 case 0xAC: IMMBYTE(eaddr);eaddr=ipcreg+SIGNED(eaddr);break;
|
|
|
386 case 0xAD: IMMWORD(eaddr);eaddr+=ipcreg;break;
|
|
|
387 case 0xAE: eaddr=0;break; /*ILLEGAL*/
|
|
|
388 case 0xAF: IMMWORD(eaddr);break;
|
|
|
389 case 0xB0: eaddr=iyreg;iyreg++;eaddr=GETWORD(eaddr);break;
|
|
|
390 case 0xB1: eaddr=iyreg;iyreg+=2;eaddr=GETWORD(eaddr);break;
|
|
|
391 case 0xB2: iyreg--;eaddr=iyreg;eaddr=GETWORD(eaddr);break;
|
|
|
392 case 0xB3: iyreg-=2;eaddr=iyreg;eaddr=GETWORD(eaddr);break;
|
|
|
393 case 0xB4: eaddr=iyreg;eaddr=GETWORD(eaddr);break;
|
|
|
394 case 0xB5: eaddr=iyreg+SIGNED(ibreg);eaddr=GETWORD(eaddr);break;
|
|
|
395 case 0xB6: eaddr=iyreg+SIGNED(iareg);eaddr=GETWORD(eaddr);break;
|
|
|
396 case 0xB7: eaddr=0;break; /*ILELGAL*/
|
|
|
397 case 0xB8: IMMBYTE(eaddr);eaddr=iyreg+SIGNED(eaddr);
|
|
|
398 eaddr=GETWORD(eaddr);break;
|
|
|
399 case 0xB9: IMMWORD(eaddr);eaddr+=iyreg;eaddr=GETWORD(eaddr);break;
|
|
|
400 case 0xBA: eaddr=0;break; /*ILLEGAL*/
|
|
|
401 case 0xBB: eaddr=iyreg+GETDREG;eaddr=GETWORD(eaddr);break;
|
|
|
402 case 0xBC: IMMBYTE(eaddr);eaddr=ipcreg+SIGNED(eaddr);
|
|
|
403 eaddr=GETWORD(eaddr);break;
|
|
|
404 case 0xBD: IMMWORD(eaddr);eaddr+=ipcreg;eaddr=GETWORD(eaddr);break;
|
|
|
405 case 0xBE: eaddr=0;break; /*ILLEGAL*/
|
|
|
406 case 0xBF: IMMWORD(eaddr);eaddr=GETWORD(eaddr);break;
|
|
|
407 case 0xC0: eaddr=iureg;iureg++;break;
|
|
|
408 case 0xC1: eaddr=iureg;iureg+=2;break;
|
|
|
409 case 0xC2: iureg--;eaddr=iureg;break;
|
|
|
410 case 0xC3: iureg-=2;eaddr=iureg;break;
|
|
|
411 case 0xC4: eaddr=iureg;break;
|
|
|
412 case 0xC5: eaddr=iureg+SIGNED(ibreg);break;
|
|
|
413 case 0xC6: eaddr=iureg+SIGNED(iareg);break;
|
|
|
414 case 0xC7: eaddr=0;break; /*ILELGAL*/
|
|
|
415 case 0xC8: IMMBYTE(eaddr);eaddr=iureg+SIGNED(eaddr);break;
|
|
|
416 case 0xC9: IMMWORD(eaddr);eaddr+=iureg;break;
|
|
|
417 case 0xCA: eaddr=0;break; /*ILLEGAL*/
|
|
|
418 case 0xCB: eaddr=iureg+GETDREG;break;
|
|
|
419 case 0xCC: IMMBYTE(eaddr);eaddr=ipcreg+SIGNED(eaddr);break;
|
|
|
420 case 0xCD: IMMWORD(eaddr);eaddr+=ipcreg;break;
|
|
|
421 case 0xCE: eaddr=0;break; /*ILLEGAL*/
|
|
|
422 case 0xCF: IMMWORD(eaddr);break;
|
|
|
423 case 0xD0: eaddr=iureg;iureg++;eaddr=GETWORD(eaddr);break;
|
|
|
424 case 0xD1: eaddr=iureg;iureg+=2;eaddr=GETWORD(eaddr);break;
|
|
|
425 case 0xD2: iureg--;eaddr=iureg;eaddr=GETWORD(eaddr);break;
|
|
|
426 case 0xD3: iureg-=2;eaddr=iureg;eaddr=GETWORD(eaddr);break;
|
|
|
427 case 0xD4: eaddr=iureg;eaddr=GETWORD(eaddr);break;
|
|
|
428 case 0xD5: eaddr=iureg+SIGNED(ibreg);eaddr=GETWORD(eaddr);break;
|
|
|
429 case 0xD6: eaddr=iureg+SIGNED(iareg);eaddr=GETWORD(eaddr);break;
|
|
|
430 case 0xD7: eaddr=0;break; /*ILELGAL*/
|
|
|
431 case 0xD8: IMMBYTE(eaddr);eaddr=iureg+SIGNED(eaddr);
|
|
|
432 eaddr=GETWORD(eaddr);break;
|
|
|
433 case 0xD9: IMMWORD(eaddr);eaddr+=iureg;eaddr=GETWORD(eaddr);break;
|
|
|
434 case 0xDA: eaddr=0;break; /*ILLEGAL*/
|
|
|
435 case 0xDB: eaddr=iureg+GETDREG;eaddr=GETWORD(eaddr);break;
|
|
|
436 case 0xDC: IMMBYTE(eaddr);eaddr=ipcreg+SIGNED(eaddr);
|
|
|
437 eaddr=GETWORD(eaddr);break;
|
|
|
438 case 0xDD: IMMWORD(eaddr);eaddr+=ipcreg;eaddr=GETWORD(eaddr);break;
|
|
|
439 case 0xDE: eaddr=0;break; /*ILLEGAL*/
|
|
|
440 case 0xDF: IMMWORD(eaddr);eaddr=GETWORD(eaddr);break;
|
|
|
441 case 0xE0: eaddr=isreg;isreg++;break;
|
|
|
442 case 0xE1: eaddr=isreg;isreg+=2;break;
|
|
|
443 case 0xE2: isreg--;eaddr=isreg;break;
|
|
|
444 case 0xE3: isreg-=2;eaddr=isreg;break;
|
|
|
445 case 0xE4: eaddr=isreg;break;
|
|
|
446 case 0xE5: eaddr=isreg+SIGNED(ibreg);break;
|
|
|
447 case 0xE6: eaddr=isreg+SIGNED(iareg);break;
|
|
|
448 case 0xE7: eaddr=0;break; /*ILELGAL*/
|
|
|
449 case 0xE8: IMMBYTE(eaddr);eaddr=isreg+SIGNED(eaddr);break;
|
|
|
450 case 0xE9: IMMWORD(eaddr);eaddr+=isreg;break;
|
|
|
451 case 0xEA: eaddr=0;break; /*ILLEGAL*/
|
|
|
452 case 0xEB: eaddr=isreg+GETDREG;break;
|
|
|
453 case 0xEC: IMMBYTE(eaddr);eaddr=ipcreg+SIGNED(eaddr);break;
|
|
|
454 case 0xED: IMMWORD(eaddr);eaddr+=ipcreg;break;
|
|
|
455 case 0xEE: eaddr=0;break; /*ILLEGAL*/
|
|
|
456 case 0xEF: IMMWORD(eaddr);break;
|
|
|
457 case 0xF0: eaddr=isreg;isreg++;eaddr=GETWORD(eaddr);break;
|
|
|
458 case 0xF1: eaddr=isreg;isreg+=2;eaddr=GETWORD(eaddr);break;
|
|
|
459 case 0xF2: isreg--;eaddr=isreg;eaddr=GETWORD(eaddr);break;
|
|
|
460 case 0xF3: isreg-=2;eaddr=isreg;eaddr=GETWORD(eaddr);break;
|
|
|
461 case 0xF4: eaddr=isreg;eaddr=GETWORD(eaddr);break;
|
|
|
462 case 0xF5: eaddr=isreg+SIGNED(ibreg);eaddr=GETWORD(eaddr);break;
|
|
|
463 case 0xF6: eaddr=isreg+SIGNED(iareg);eaddr=GETWORD(eaddr);break;
|
|
|
464 case 0xF7: eaddr=0;break; /*ILELGAL*/
|
|
|
465 case 0xF8: IMMBYTE(eaddr);eaddr=isreg+SIGNED(eaddr);
|
|
|
466 eaddr=GETWORD(eaddr);break;
|
|
|
467 case 0xF9: IMMWORD(eaddr);eaddr+=isreg;eaddr=GETWORD(eaddr);break;
|
|
|
468 case 0xFA: eaddr=0;break; /*ILLEGAL*/
|
|
|
469 case 0xFB: eaddr=isreg+GETDREG;eaddr=GETWORD(eaddr);break;
|
|
|
470 case 0xFC: IMMBYTE(eaddr);eaddr=ipcreg+SIGNED(eaddr);
|
|
|
471 eaddr=GETWORD(eaddr);break;
|
|
|
472 case 0xFD: IMMWORD(eaddr);eaddr+=ipcreg;eaddr=GETWORD(eaddr);break;
|
|
|
473 case 0xFE: eaddr=0;break; /*ILLEGAL*/
|
|
|
474 case 0xFF: IMMWORD(eaddr);eaddr=GETWORD(eaddr);break;
|
|
|
475 }
|
|
|
476 }
|
|
|
477 switch(ireg) {
|
|
|
478 case 0x00: /*NEG direct*/ DIRECT tw=-mem[eaddr];SETSTATUS(0,mem[eaddr],tw)
|
|
|
479 SETBYTE(eaddr,tw)break;
|
|
|
480 case 0x01: break;/*ILLEGAL*/
|
|
|
481 case 0x02: break;/*ILLEGAL*/
|
|
|
482 case 0x03: /*COM direct*/ DIRECT tb=~mem[eaddr];SETNZ8(tb);SEC CLV
|
|
|
483 SETBYTE(eaddr,tb)break;
|
|
|
484 case 0x04: /*LSR direct*/ DIRECT tb=mem[eaddr];if(tb&0x01)SEC else CLC
|
|
|
485 if(tb&0x10)SEH else CLH tb>>=1;SETNZ8(tb)
|
|
|
486 SETBYTE(eaddr,tb)break;
|
|
|
487 case 0x05: break;/* ILLEGAL*/
|
|
|
488 case 0x06: /*ROR direct*/ DIRECT tb=(iccreg&0x01)<<7;
|
|
|
489 if(mem[eaddr]&0x01)SEC else CLC
|
|
|
490 tw=(mem[eaddr]>>1)+tb;SETNZ8(tw)
|
|
|
491 SETBYTE(eaddr,tw)
|
|
|
492 break;
|
|
|
493 case 0x07: /*ASR direct*/ DIRECT tb=mem[eaddr];if(tb&0x01)SEC else CLC
|
|
|
494 if(tb&0x10)SEH else CLH tb>>=1;
|
|
|
495 if(tb&0x40)tb|=0x80;SETBYTE(eaddr,tb)SETNZ8(tb)
|
|
|
496 break;
|
|
|
497 case 0x08: /*ASL direct*/ DIRECT tw=mem[eaddr]<<1;
|
|
|
498 SETSTATUS(mem[eaddr],mem[eaddr],tw)
|
|
|
499 SETBYTE(eaddr,tw)break;
|
|
|
500 case 0x09: /*ROL direct*/ DIRECT tb=mem[eaddr];tw=iccreg&0x01;
|
|
|
501 if(tb&0x80)SEC else CLC
|
|
|
502 if((tb&0x80)^((tb<<1)&0x80))SEV else CLV
|
|
|
503 tb=(tb<<1)+tw;SETNZ8(tb) SETBYTE(eaddr,tb)break;
|
|
|
504 case 0x0A: /*DEC direct*/ DIRECT tb=mem[eaddr]-1;if(tb==0x7F)SEV else CLV
|
|
|
505 SETNZ8(tb) SETBYTE(eaddr,tb)break;
|
|
|
506 case 0x0B: break; /*ILLEGAL*/
|
|
|
507 case 0x0C: /*INC direct*/ DIRECT tb=mem[eaddr]+1;if(tb==0x80)SEV else CLV
|
|
|
508 SETNZ8(tb) SETBYTE(eaddr,tb)break;
|
|
|
509 case 0x0D: /*TST direct*/ DIRECT tb=mem[eaddr];SETNZ8(tb) break;
|
|
|
510 case 0x0E: /*JMP direct*/ DIRECT ipcreg=eaddr;break;
|
|
|
511 case 0x0F: /*CLR direct*/ DIRECT SETBYTE(eaddr,0);CLN CLV SEZ CLC break;
|
|
|
512 case 0x10: /* flag10 */ iflag=1;goto flaginstr;
|
|
|
513 case 0x11: /* flag11 */ iflag=2;goto flaginstr;
|
|
|
514 case 0x12: /* NOP */ break;
|
|
|
515 case 0x13: /* SYNC */
|
|
|
516 do usleep(USLEEP); /* Wait for IRQ */
|
|
|
517 while(!irq && !attention);
|
|
|
518 if(iccreg&0x40)tracetrick=1;
|
|
|
519 break;
|
|
|
520 case 0x14: break; /*ILLEGAL*/
|
|
|
521 case 0x15: break; /*ILLEGAL*/
|
|
|
522 case 0x16: /*LBRA*/ IMMWORD(eaddr) ipcreg+=eaddr;break;
|
|
|
523 case 0x17: /*LBSR*/ IMMWORD(eaddr) PUSHWORD(ipcreg) ipcreg+=eaddr;break;
|
|
|
524 case 0x18: break; /*ILLEGAL*/
|
|
|
525 case 0x19: /* DAA*/ tw=iareg;
|
|
|
526 if(iccreg&0x20)tw+=6;
|
|
|
527 if((tw&0x0f)>9)tw+=6;
|
|
|
528 if(iccreg&0x01)tw+=0x60;
|
|
|
529 if((tw&0xf0)>0x90)tw+=0x60;
|
|
|
530 if(tw&0x100)SEC
|
|
|
531 iareg=tw;break;
|
|
|
532 case 0x1A: /* ORCC*/ IMMBYTE(tb) iccreg|=tb;break;
|
|
|
533 case 0x1B: break; /*ILLEGAL*/
|
|
|
534 case 0x1C: /* ANDCC*/ IMMBYTE(tb) iccreg&=tb;break;
|
|
|
535 case 0x1D: /* SEX */ tw=SIGNED(ibreg); SETNZ16(tw) SETDREG(tw) break;
|
|
|
536 case 0x1E: /* EXG */ IMMBYTE(tb) {Word t2;GETREG(tw,tb>>4) GETREG(t2,tb&15)
|
|
|
537 SETREG(t2,tb>>4) SETREG(tw,tb&15) } break;
|
|
|
538 case 0x1F: /* TFR */ IMMBYTE(tb) GETREG(tw,tb>>4) SETREG(tw,tb&15) break;
|
|
|
539 case 0x20: /* (L)BRA*/ BRANCH(1) break;
|
|
|
540 case 0x21: /* (L)BRN*/ BRANCH(0) break;
|
|
|
541 case 0x22: /* (L)BHI*/ BRANCH(!(iccreg&0x05)) break;
|
|
|
542 case 0x23: /* (L)BLS*/ BRANCH(iccreg&0x05) break;
|
|
|
543 case 0x24: /* (L)BCC*/ BRANCH(!(iccreg&0x01)) break;
|
|
|
544 case 0x25: /* (L)BCS*/ BRANCH(iccreg&0x01) break;
|
|
|
545 case 0x26: /* (L)BNE*/ BRANCH(!(iccreg&0x04)) break;
|
|
|
546 case 0x27: /* (L)BEQ*/ BRANCH(iccreg&0x04) break;
|
|
|
547 case 0x28: /* (L)BVC*/ BRANCH(!(iccreg&0x02)) break;
|
|
|
548 case 0x29: /* (L)BVS*/ BRANCH(iccreg&0x02) break;
|
|
|
549 case 0x2A: /* (L)BPL*/ BRANCH(!(iccreg&0x08)) break;
|
|
|
550 case 0x2B: /* (L)BMI*/ BRANCH(iccreg&0x08) break;
|
|
|
551 case 0x2C: /* (L)BGE*/ BRANCH(!NXORV) break;
|
|
|
552 case 0x2D: /* (L)BLT*/ BRANCH(NXORV) break;
|
|
|
553 case 0x2E: /* (L)BGT*/ BRANCH(!(NXORV||iccreg&0x04)) break;
|
|
|
554 case 0x2F: /* (L)BLE*/ BRANCH(NXORV||iccreg&0x04) break;
|
|
|
555 case 0x30: /* LEAX*/ ixreg=eaddr; if(ixreg) CLZ else SEZ break;
|
|
|
556 case 0x31: /* LEAY*/ iyreg=eaddr; if(iyreg) CLZ else SEZ break;
|
|
|
557 case 0x32: /* LEAS*/ isreg=eaddr;break;
|
|
|
558 case 0x33: /* LEAU*/ iureg=eaddr;break;
|
|
|
559 case 0x34: /* PSHS*/ IMMBYTE(tb)
|
|
|
560 if(tb&0x80)PUSHWORD(ipcreg)
|
|
|
561 if(tb&0x40)PUSHWORD(iureg)
|
|
|
562 if(tb&0x20)PUSHWORD(iyreg)
|
|
|
563 if(tb&0x10)PUSHWORD(ixreg)
|
|
|
564 if(tb&0x08)PUSHBYTE(idpreg)
|
|
|
565 if(tb&0x04)PUSHBYTE(ibreg)
|
|
|
566 if(tb&0x02)PUSHBYTE(iareg)
|
|
|
567 if(tb&0x01)PUSHBYTE(iccreg) break;
|
|
|
568 case 0x35: /* PULS*/ IMMBYTE(tb)
|
|
|
569 if(tb&0x01)PULLBYTE(iccreg)
|
|
|
570 if(tb&0x02)PULLBYTE(iareg)
|
|
|
571 if(tb&0x04)PULLBYTE(ibreg)
|
|
|
572 if(tb&0x08)PULLBYTE(idpreg)
|
|
|
573 if(tb&0x10)PULLWORD(ixreg)
|
|
|
574 if(tb&0x20)PULLWORD(iyreg)
|
|
|
575 if(tb&0x40)PULLWORD(iureg)
|
|
|
576 if(tb&0x80)PULLWORD(ipcreg)
|
|
|
577 if(tracetrick&&tb==0xff) { /* Arrange fake FIRQ after next insn
|
|
|
578 for hardware tracing */
|
|
|
579 tracetrick=0;
|
|
|
580 irq=2;
|
|
|
581 attention=1;
|
|
|
582 goto flaginstr;
|
|
|
583 }
|
|
|
584 break;
|
|
|
585 case 0x36: /* PSHU*/ IMMBYTE(tb)
|
|
|
586 if(tb&0x80)PSHUWORD(ipcreg)
|
|
|
587 if(tb&0x40)PSHUWORD(isreg)
|
|
|
588 if(tb&0x20)PSHUWORD(iyreg)
|
|
|
589 if(tb&0x10)PSHUWORD(ixreg)
|
|
|
590 if(tb&0x08)PSHUBYTE(idpreg)
|
|
|
591 if(tb&0x04)PSHUBYTE(ibreg)
|
|
|
592 if(tb&0x02)PSHUBYTE(iareg)
|
|
|
593 if(tb&0x01)PSHUBYTE(iccreg) break;
|
|
|
594 case 0x37: /* PULU*/ IMMBYTE(tb)
|
|
|
595 if(tb&0x01)PULUBYTE(iccreg)
|
|
|
596 if(tb&0x02)PULUBYTE(iareg)
|
|
|
597 if(tb&0x04)PULUBYTE(ibreg)
|
|
|
598 if(tb&0x08)PULUBYTE(idpreg)
|
|
|
599 if(tb&0x10)PULUWORD(ixreg)
|
|
|
600 if(tb&0x20)PULUWORD(iyreg)
|
|
|
601 if(tb&0x40)PULUWORD(isreg)
|
|
|
602 if(tb&0x80)PULUWORD(ipcreg) break;
|
|
|
603 case 0x39: /* RTS*/ PULLWORD(ipcreg) break;
|
|
|
604 case 0x3A: /* ABX*/ ixreg+=ibreg; break;
|
|
|
605 case 0x3B: /* RTI*/ tb=iccreg&0x80;
|
|
|
606 PULLBYTE(iccreg)
|
|
|
607 if(tb)
|
|
|
608 {
|
|
|
609 PULLBYTE(iareg)
|
|
|
610 PULLBYTE(ibreg)
|
|
|
611 PULLBYTE(idpreg)
|
|
|
612 PULLWORD(ixreg)
|
|
|
613 PULLWORD(iyreg)
|
|
|
614 PULLWORD(iureg)
|
|
|
615 }
|
|
|
616 PULLWORD(ipcreg) break;
|
|
|
617 case 0x3C: /* CWAI*/ IMMBYTE(tb)
|
|
|
618 PUSHWORD(ipcreg)
|
|
|
619 PUSHWORD(iureg)
|
|
|
620 PUSHWORD(iyreg)
|
|
|
621 PUSHWORD(ixreg)
|
|
|
622 PUSHBYTE(idpreg)
|
|
|
623 PUSHBYTE(ibreg)
|
|
|
624 PUSHBYTE(iareg)
|
|
|
625 PUSHBYTE(iccreg)
|
|
|
626 iccreg&=tb;
|
|
|
627 iccreg|=0x80;
|
|
|
628 do usleep(USLEEP); /* Wait for IRQ */
|
|
|
629 while(!attention && !((irq==1&&!(iccreg&0x10))||(irq==2&&!(iccreg&0x040))));
|
|
|
630 if(irq==1)ipcreg=GETWORD(0xfff8);
|
|
|
631 else ipcreg=GETWORD(0xfff6);
|
|
|
632 irq=0;
|
|
|
633 if(!tracing)attention=0;
|
|
|
634 break;
|
|
|
635 case 0x3D: /* MUL*/ tw=iareg*ibreg; if(tw)CLZ else SEZ
|
|
|
636 if(tw&0x80) SEC else CLC SETDREG(tw) break;
|
|
|
637 case 0x3E: break; /*ILLEGAL*/
|
|
|
638 case 0x3F: /* SWI (SWI2 SWI3)*/ {
|
|
|
639 PUSHWORD(ipcreg)
|
|
|
640 PUSHWORD(iureg)
|
|
|
641 PUSHWORD(iyreg)
|
|
|
642 PUSHWORD(ixreg)
|
|
|
643 PUSHBYTE(idpreg)
|
|
|
644 PUSHBYTE(ibreg)
|
|
|
645 PUSHBYTE(iareg)
|
|
|
646 PUSHBYTE(iccreg)
|
|
|
647 iccreg|=0x80;
|
|
|
648 if(!iflag)iccreg|=0x50;
|
|
|
649 switch(iflag) {
|
|
|
650 case 0:ipcreg=GETWORD(0xfffa);break;
|
|
|
651 case 1:ipcreg=GETWORD(0xfff4);break;
|
|
|
652 case 2:ipcreg=GETWORD(0xfff2);break;
|
|
|
653 }
|
|
|
654 }break;
|
|
|
655 case 0x40: /*NEGA*/ tw=-iareg;SETSTATUS(0,iareg,tw)
|
|
|
656 iareg=tw;break;
|
|
|
657 case 0x41: break;/*ILLEGAL*/
|
|
|
658 case 0x42: break;/*ILLEGAL*/
|
|
|
659 case 0x43: /*COMA*/ tb=~iareg;SETNZ8(tb);SEC CLV
|
|
|
660 iareg=tb;break;
|
|
|
661 case 0x44: /*LSRA*/ tb=iareg;if(tb&0x01)SEC else CLC
|
|
|
662 if(tb&0x10)SEH else CLH tb>>=1;SETNZ8(tb)
|
|
|
663 iareg=tb;break;
|
|
|
664 case 0x45: break;/* ILLEGAL*/
|
|
|
665 case 0x46: /*RORA*/ tb=(iccreg&0x01)<<7;
|
|
|
666 if(iareg&0x01)SEC else CLC
|
|
|
667 iareg=(iareg>>1)+tb;SETNZ8(iareg)
|
|
|
668 break;
|
|
|
669 case 0x47: /*ASRA*/ tb=iareg;if(tb&0x01)SEC else CLC
|
|
|
670 if(tb&0x10)SEH else CLH tb>>=1;
|
|
|
671 if(tb&0x40)tb|=0x80;iareg=tb;SETNZ8(tb)
|
|
|
672 break;
|
|
|
673 case 0x48: /*ASLA*/ tw=iareg<<1;
|
|
|
674 SETSTATUS(iareg,iareg,tw)
|
|
|
675 iareg=tw;break;
|
|
|
676 case 0x49: /*ROLA*/ tb=iareg;tw=iccreg&0x01;
|
|
|
677 if(tb&0x80)SEC else CLC
|
|
|
678 if((tb&0x80)^((tb<<1)&0x80))SEV else CLV
|
|
|
679 tb=(tb<<1)+tw;SETNZ8(tb) iareg=tb;break;
|
|
|
680 case 0x4A: /*DECA*/ tb=iareg-1;if(tb==0x7F)SEV else CLV
|
|
|
681 SETNZ8(tb) iareg=tb;break;
|
|
|
682 case 0x4B: break; /*ILLEGAL*/
|
|
|
683 case 0x4C: /*INCA*/ tb=iareg+1;if(tb==0x80)SEV else CLV
|
|
|
684 SETNZ8(tb) iareg=tb;break;
|
|
|
685 case 0x4D: /*TSTA*/ SETNZ8(iareg) break;
|
|
|
686 case 0x4E: break; /*ILLEGAL*/
|
|
|
687 case 0x4F: /*CLRA*/ iareg=0;CLN CLV SEZ CLC break;
|
|
|
688 case 0x50: /*NEGB*/ tw=-ibreg;SETSTATUS(0,ibreg,tw)
|
|
|
689 ibreg=tw;break;
|
|
|
690 case 0x51: break;/*ILLEGAL*/
|
|
|
691 case 0x52: break;/*ILLEGAL*/
|
|
|
692 case 0x53: /*COMB*/ tb=~ibreg;SETNZ8(tb);SEC CLV
|
|
|
693 ibreg=tb;break;
|
|
|
694 case 0x54: /*LSRB*/ tb=ibreg;if(tb&0x01)SEC else CLC
|
|
|
695 if(tb&0x10)SEH else CLH tb>>=1;SETNZ8(tb)
|
|
|
696 ibreg=tb;break;
|
|
|
697 case 0x55: break;/* ILLEGAL*/
|
|
|
698 case 0x56: /*RORB*/ tb=(iccreg&0x01)<<7;
|
|
|
699 if(ibreg&0x01)SEC else CLC
|
|
|
700 ibreg=(ibreg>>1)+tb;SETNZ8(ibreg)
|
|
|
701 break;
|
|
|
702 case 0x57: /*ASRB*/ tb=ibreg;if(tb&0x01)SEC else CLC
|
|
|
703 if(tb&0x10)SEH else CLH tb>>=1;
|
|
|
704 if(tb&0x40)tb|=0x80;ibreg=tb;SETNZ8(tb)
|
|
|
705 break;
|
|
|
706 case 0x58: /*ASLB*/ tw=ibreg<<1;
|
|
|
707 SETSTATUS(ibreg,ibreg,tw)
|
|
|
708 ibreg=tw;break;
|
|
|
709 case 0x59: /*ROLB*/ tb=ibreg;tw=iccreg&0x01;
|
|
|
710 if(tb&0x80)SEC else CLC
|
|
|
711 if((tb&0x80)^((tb<<1)&0x80))SEV else CLV
|
|
|
712 tb=(tb<<1)+tw;SETNZ8(tb) ibreg=tb;break;
|
|
|
713 case 0x5A: /*DECB*/ tb=ibreg-1;if(tb==0x7F)SEV else CLV
|
|
|
714 SETNZ8(tb) ibreg=tb;break;
|
|
|
715 case 0x5B: break; /*ILLEGAL*/
|
|
|
716 case 0x5C: /*INCB*/ tb=ibreg+1;if(tb==0x80)SEV else CLV
|
|
|
717 SETNZ8(tb) ibreg=tb;break;
|
|
|
718 case 0x5D: /*TSTB*/ SETNZ8(ibreg) break;
|
|
|
719 case 0x5E: break; /*ILLEGAL*/
|
|
|
720 case 0x5F: /*CLRB*/ ibreg=0;CLN CLV SEZ CLC break;
|
|
|
721 case 0x60: /*NEG indexed*/ tw=-mem[eaddr];SETSTATUS(0,mem[eaddr],tw)
|
|
|
722 SETBYTE(eaddr,tw)break;
|
|
|
723 case 0x61: break;/*ILLEGAL*/
|
|
|
724 case 0x62: break;/*ILLEGAL*/
|
|
|
725 case 0x63: /*COM indexed*/ tb=~mem[eaddr];SETNZ8(tb);SEC CLV
|
|
|
726 SETBYTE(eaddr,tb)break;
|
|
|
727 case 0x64: /*LSR indexed*/ tb=mem[eaddr];if(tb&0x01)SEC else CLC
|
|
|
728 if(tb&0x10)SEH else CLH tb>>=1;SETNZ8(tb)
|
|
|
729 SETBYTE(eaddr,tb)break;
|
|
|
730 case 0x65: break;/* ILLEGAL*/
|
|
|
731 case 0x66: /*ROR indexed*/ tb=(iccreg&0x01)<<7;
|
|
|
732 if(mem[eaddr]&0x01)SEC else CLC
|
|
|
733 tw=(mem[eaddr]>>1)+tb;SETNZ8(tw)
|
|
|
734 SETBYTE(eaddr,tw)
|
|
|
735 break;
|
|
|
736 case 0x67: /*ASR indexed*/ tb=mem[eaddr];if(tb&0x01)SEC else CLC
|
|
|
737 if(tb&0x10)SEH else CLH tb>>=1;
|
|
|
738 if(tb&0x40)tb|=0x80;SETBYTE(eaddr,tb)SETNZ8(tb)
|
|
|
739 break;
|
|
|
740 case 0x68: /*ASL indexed*/ tw=mem[eaddr]<<1;
|
|
|
741 SETSTATUS(mem[eaddr],mem[eaddr],tw)
|
|
|
742 SETBYTE(eaddr,tw)break;
|
|
|
743 case 0x69: /*ROL indexed*/ tb=mem[eaddr];tw=iccreg&0x01;
|
|
|
744 if(tb&0x80)SEC else CLC
|
|
|
745 if((tb&0x80)^((tb<<1)&0x80))SEV else CLV
|
|
|
746 tb=(tb<<1)+tw;SETNZ8(tb) SETBYTE(eaddr,tb)break;
|
|
|
747 case 0x6A: /*DEC indexed*/ tb=mem[eaddr]-1;if(tb==0x7F)SEV else CLV
|
|
|
748 SETNZ8(tb) SETBYTE(eaddr,tb)break;
|
|
|
749 case 0x6B: break; /*ILLEGAL*/
|
|
|
750 case 0x6C: /*INC indexed*/ tb=mem[eaddr]+1;if(tb==0x80)SEV else CLV
|
|
|
751 SETNZ8(tb) SETBYTE(eaddr,tb)break;
|
|
|
752 case 0x6D: /*TST indexed*/ tb=mem[eaddr];SETNZ8(tb) break;
|
|
|
753 case 0x6E: /*JMP indexed*/ ipcreg=eaddr;break;
|
|
|
754 case 0x6F: /*CLR indexed*/ SETBYTE(eaddr,0)CLN CLV SEZ CLC break;
|
|
|
755 case 0x70: /*NEG ext*/ EXTENDED tw=-mem[eaddr];SETSTATUS(0,mem[eaddr],tw)
|
|
|
756 SETBYTE(eaddr,tw)break;
|
|
|
757 case 0x71: break;/*ILLEGAL*/
|
|
|
758 case 0x72: break;/*ILLEGAL*/
|
|
|
759 case 0x73: /*COM ext*/ EXTENDED tb=~mem[eaddr];SETNZ8(tb);SEC CLV
|
|
|
760 SETBYTE(eaddr,tb)break;
|
|
|
761 case 0x74: /*LSR ext*/ EXTENDED tb=mem[eaddr];if(tb&0x01)SEC else CLC
|
|
|
762 if(tb&0x10)SEH else CLH tb>>=1;SETNZ8(tb)
|
|
|
763 SETBYTE(eaddr,tb)break;
|
|
|
764 case 0x75: break;/* ILLEGAL*/
|
|
|
765 case 0x76: /*ROR ext*/ EXTENDED tb=(iccreg&0x01)<<7;
|
|
|
766 if(mem[eaddr]&0x01)SEC else CLC
|
|
|
767 tw=(mem[eaddr]>>1)+tb;SETNZ8(tw)
|
|
|
768 SETBYTE(eaddr,tw)
|
|
|
769 break;
|
|
|
770 case 0x77: /*ASR ext*/ EXTENDED tb=mem[eaddr];if(tb&0x01)SEC else CLC
|
|
|
771 if(tb&0x10)SEH else CLH tb>>=1;
|
|
|
772 if(tb&0x40)tb|=0x80;SETBYTE(eaddr,tb)SETNZ8(tb)
|
|
|
773 break;
|
|
|
774 case 0x78: /*ASL ext*/ EXTENDED tw=mem[eaddr]<<1;
|
|
|
775 SETSTATUS(mem[eaddr],mem[eaddr],tw)
|
|
|
776 SETBYTE(eaddr,tw)break;
|
|
|
777 case 0x79: /*ROL ext*/ EXTENDED tb=mem[eaddr];tw=iccreg&0x01;
|
|
|
778 if(tb&0x80)SEC else CLC
|
|
|
779 if((tb&0x80)^((tb<<1)&0x80))SEV else CLV
|
|
|
780 tb=(tb<<1)+tw;SETNZ8(tb) SETBYTE(eaddr,tb)break;
|
|
|
781 case 0x7A: /*DEC ext*/ EXTENDED tb=mem[eaddr]-1;if(tb==0x7F)SEV else CLV
|
|
|
782 SETNZ8(tb) SETBYTE(eaddr,tb)break;
|
|
|
783 case 0x7B: break; /*ILLEGAL*/
|
|
|
784 case 0x7C: /*INC ext*/ EXTENDED tb=mem[eaddr]+1;if(tb==0x80)SEV else CLV
|
|
|
785 SETNZ8(tb) SETBYTE(eaddr,tb)break;
|
|
|
786 case 0x7D: /*TST ext*/ EXTENDED tb=mem[eaddr];SETNZ8(tb) break;
|
|
|
787 case 0x7E: /*JMP ext*/ EXTENDED ipcreg=eaddr;break;
|
|
|
788 case 0x7F: /*CLR ext*/ EXTENDED SETBYTE(eaddr,0)CLN CLV SEZ CLC break;
|
|
|
789 case 0x80: /*SUBA immediate*/ IMM8 tw=iareg-mem[eaddr];
|
|
|
790 SETSTATUS(iareg,mem[eaddr],tw)
|
|
|
791 iareg=tw;break;
|
|
|
792 case 0x81: /*CMPA immediate*/ IMM8 tw=iareg-mem[eaddr];
|
|
|
793 SETSTATUS(iareg,mem[eaddr],tw) break;
|
|
|
794 case 0x82: /*SBCA immediate*/ IMM8 tw=iareg-mem[eaddr]-(iccreg&0x01);
|
|
|
795 SETSTATUS(iareg,mem[eaddr],tw)
|
|
|
796 iareg=tw;break;
|
|
|
797 case 0x83: /*SUBD (CMPD CMPU) immediate*/ IMM16
|
|
|
798 {unsigned long res,dreg,breg;
|
|
|
799 if(iflag==2)dreg=iureg;else dreg=GETDREG;
|
|
|
800 breg=GETWORD(eaddr);
|
|
|
801 res=dreg-breg;
|
|
|
802 SETSTATUSD(dreg,breg,res)
|
|
|
803 if(iflag==0) SETDREG(res)
|
|
|
804 }break;
|
|
|
805 case 0x84: /*ANDA immediate*/ IMM8 iareg=iareg&mem[eaddr];SETNZ8(iareg)
|
|
|
806 CLV break;
|
|
|
807 case 0x85: /*BITA immediate*/ IMM8 tb=iareg&mem[eaddr];SETNZ8(tb)
|
|
|
808 CLV break;
|
|
|
809 case 0x86: /*LDA immediate*/ IMM8 LOADAC(iareg) CLV SETNZ8(iareg)
|
|
|
810 break;
|
|
|
811 case 0x87: /*STA immediate (for the sake of orthogonality) */ IMM8
|
|
|
812 SETNZ8(iareg) CLV STOREAC(iareg) break;
|
|
|
813 case 0x88: /*EORA immediate*/ IMM8 iareg=iareg^mem[eaddr];SETNZ8(iareg)
|
|
|
814 CLV break;
|
|
|
815 case 0x89: /*ADCA immediate*/ IMM8 tw=iareg+mem[eaddr]+(iccreg&0x01);
|
|
|
816 SETSTATUS(iareg,mem[eaddr],tw)
|
|
|
817 iareg=tw;break;
|
|
|
818 case 0x8A: /*ORA immediate*/ IMM8 iareg=iareg|mem[eaddr];SETNZ8(iareg)
|
|
|
819 CLV break;
|
|
|
820 case 0x8B: /*ADDA immediate*/ IMM8 tw=iareg+mem[eaddr];
|
|
|
821 SETSTATUS(iareg,mem[eaddr],tw)
|
|
|
822 iareg=tw;break;
|
|
|
823 case 0x8C: /*CMPX (CMPY CMPS) immediate */ IMM16
|
|
|
824 {unsigned long dreg,breg,res;
|
|
|
825 if(iflag==0)dreg=ixreg;else if(iflag==1)
|
|
|
826 dreg=iyreg;else dreg=isreg;breg=GETWORD(eaddr);
|
|
|
827 res=dreg-breg;
|
|
|
828 SETSTATUSD(dreg,breg,res)
|
|
|
829 }break;
|
|
|
830 case 0x8D: /*BSR */ IMMBYTE(tb) PUSHWORD(ipcreg) ipcreg+=SIGNED(tb);
|
|
|
831 break;
|
|
|
832 case 0x8E: /* LDX (LDY) immediate */ IMM16 tw=GETWORD(eaddr);
|
|
|
833 CLV SETNZ16(tw) if(!iflag)ixreg=tw; else
|
|
|
834 iyreg=tw;break;
|
|
|
835 case 0x8F: /* STX (STY) immediate (orthogonality) */ IMM16
|
|
|
836 if(!iflag) tw=ixreg; else tw=iyreg;
|
|
|
837 CLV SETNZ16(tw) SETWORD(eaddr,tw) break;
|
|
|
838 case 0x90: /*SUBA direct*/ DIRECT tw=iareg-mem[eaddr];
|
|
|
839 SETSTATUS(iareg,mem[eaddr],tw)
|
|
|
840 iareg=tw;break;
|
|
|
841 case 0x91: /*CMPA direct*/ DIRECT tw=iareg-mem[eaddr];
|
|
|
842 SETSTATUS(iareg,mem[eaddr],tw) break;
|
|
|
843 case 0x92: /*SBCA direct*/ DIRECT tw=iareg-mem[eaddr]-(iccreg&0x01);
|
|
|
844 SETSTATUS(iareg,mem[eaddr],tw)
|
|
|
845 iareg=tw;break;
|
|
|
846 case 0x93: /*SUBD (CMPD CMPU) direct*/ DIRECT
|
|
|
847 {unsigned long res,dreg,breg;
|
|
|
848 if(iflag==2)dreg=iureg;else dreg=GETDREG;
|
|
|
849 breg=GETWORD(eaddr);
|
|
|
850 res=dreg-breg;
|
|
|
851 SETSTATUSD(dreg,breg,res)
|
|
|
852 if(iflag==0) SETDREG(res)
|
|
|
853 }break;
|
|
|
854 case 0x94: /*ANDA direct*/ DIRECT iareg=iareg&mem[eaddr];SETNZ8(iareg)
|
|
|
855 CLV break;
|
|
|
856 case 0x95: /*BITA direct*/ DIRECT tb=iareg&mem[eaddr];SETNZ8(tb)
|
|
|
857 CLV break;
|
|
|
858 case 0x96: /*LDA direct*/ DIRECT LOADAC(iareg) CLV SETNZ8(iareg)
|
|
|
859 break;
|
|
|
860 case 0x97: /*STA direct */ DIRECT
|
|
|
861 SETNZ8(iareg) CLV STOREAC(iareg) break;
|
|
|
862 case 0x98: /*EORA direct*/ DIRECT iareg=iareg^mem[eaddr];SETNZ8(iareg)
|
|
|
863 CLV break;
|
|
|
864 case 0x99: /*ADCA direct*/ DIRECT tw=iareg+mem[eaddr]+(iccreg&0x01);
|
|
|
865 SETSTATUS(iareg,mem[eaddr],tw)
|
|
|
866 iareg=tw;break;
|
|
|
867 case 0x9A: /*ORA direct*/ DIRECT iareg=iareg|mem[eaddr];SETNZ8(iareg)
|
|
|
868 CLV break;
|
|
|
869 case 0x9B: /*ADDA direct*/ DIRECT tw=iareg+mem[eaddr];
|
|
|
870 SETSTATUS(iareg,mem[eaddr],tw)
|
|
|
871 iareg=tw;break;
|
|
|
872 case 0x9C: /*CMPX (CMPY CMPS) direct */ DIRECT
|
|
|
873 {unsigned long dreg,breg,res;
|
|
|
874 if(iflag==0)dreg=ixreg;else if(iflag==1)
|
|
|
875 dreg=iyreg;else dreg=isreg;breg=GETWORD(eaddr);
|
|
|
876 res=dreg-breg;
|
|
|
877 SETSTATUSD(dreg,breg,res)
|
|
|
878 }break;
|
|
|
879 case 0x9D: /*JSR direct */ DIRECT PUSHWORD(ipcreg) ipcreg=eaddr;
|
|
|
880 break;
|
|
|
881 case 0x9E: /* LDX (LDY) direct */ DIRECT tw=GETWORD(eaddr);
|
|
|
882 CLV SETNZ16(tw) if(!iflag)ixreg=tw; else
|
|
|
883 iyreg=tw;break;
|
|
|
884 case 0x9F: /* STX (STY) direct */ DIRECT
|
|
|
885 if(!iflag) tw=ixreg; else tw=iyreg;
|
|
|
886 CLV SETNZ16(tw) SETWORD(eaddr,tw) break;
|
|
|
887 case 0xA0: /*SUBA indexed*/ tw=iareg-mem[eaddr];
|
|
|
888 SETSTATUS(iareg,mem[eaddr],tw)
|
|
|
889 iareg=tw;break;
|
|
|
890 case 0xA1: /*CMPA indexed*/ tw=iareg-mem[eaddr];
|
|
|
891 SETSTATUS(iareg,mem[eaddr],tw) break;
|
|
|
892 case 0xA2: /*SBCA indexed*/ tw=iareg-mem[eaddr]-(iccreg&0x01);
|
|
|
893 SETSTATUS(iareg,mem[eaddr],tw)
|
|
|
894 iareg=tw;break;
|
|
|
895 case 0xA3: /*SUBD (CMPD CMPU) indexed*/
|
|
|
896 {unsigned long res,dreg,breg;
|
|
|
897 if(iflag==2)dreg=iureg;else dreg=GETDREG;
|
|
|
898 breg=GETWORD(eaddr);
|
|
|
899 res=dreg-breg;
|
|
|
900 SETSTATUSD(dreg,breg,res)
|
|
|
901 if(iflag==0) SETDREG(res)
|
|
|
902 }break;
|
|
|
903 case 0xA4: /*ANDA indexed*/ iareg=iareg&mem[eaddr];SETNZ8(iareg)
|
|
|
904 CLV break;
|
|
|
905 case 0xA5: /*BITA indexed*/ tb=iareg&mem[eaddr];SETNZ8(tb)
|
|
|
906 CLV break;
|
|
|
907 case 0xA6: /*LDA indexed*/ LOADAC(iareg) CLV SETNZ8(iareg)
|
|
|
908 break;
|
|
|
909 case 0xA7: /*STA indexed */
|
|
|
910 SETNZ8(iareg) CLV STOREAC(iareg) break;
|
|
|
911 case 0xA8: /*EORA indexed*/ iareg=iareg^mem[eaddr];SETNZ8(iareg)
|
|
|
912 CLV break;
|
|
|
913 case 0xA9: /*ADCA indexed*/ tw=iareg+mem[eaddr]+(iccreg&0x01);
|
|
|
914 SETSTATUS(iareg,mem[eaddr],tw)
|
|
|
915 iareg=tw;break;
|
|
|
916 case 0xAA: /*ORA indexed*/ iareg=iareg|mem[eaddr];SETNZ8(iareg)
|
|
|
917 CLV break;
|
|
|
918 case 0xAB: /*ADDA indexed*/ tw=iareg+mem[eaddr];
|
|
|
919 SETSTATUS(iareg,mem[eaddr],tw)
|
|
|
920 iareg=tw;break;
|
|
|
921 case 0xAC: /*CMPX (CMPY CMPS) indexed */
|
|
|
922 {unsigned long dreg,breg,res;
|
|
|
923 if(iflag==0)dreg=ixreg;else if(iflag==1)
|
|
|
924 dreg=iyreg;else dreg=isreg;breg=GETWORD(eaddr);
|
|
|
925 res=dreg-breg;
|
|
|
926 SETSTATUSD(dreg,breg,res)
|
|
|
927 }break;
|
|
|
928 case 0xAD: /*JSR indexed */ PUSHWORD(ipcreg) ipcreg=eaddr;
|
|
|
929 break;
|
|
|
930 case 0xAE: /* LDX (LDY) indexed */ tw=GETWORD(eaddr);
|
|
|
931 CLV SETNZ16(tw) if(!iflag)ixreg=tw; else
|
|
|
932 iyreg=tw;break;
|
|
|
933 case 0xAF: /* STX (STY) indexed */
|
|
|
934 if(!iflag) tw=ixreg; else tw=iyreg;
|
|
|
935 CLV SETNZ16(tw) SETWORD(eaddr,tw) break;
|
|
|
936 case 0xB0: /*SUBA ext*/ EXTENDED tw=iareg-mem[eaddr];
|
|
|
937 SETSTATUS(iareg,mem[eaddr],tw)
|
|
|
938 iareg=tw;break;
|
|
|
939 case 0xB1: /*CMPA ext*/ EXTENDED tw=iareg-mem[eaddr];
|
|
|
940 SETSTATUS(iareg,mem[eaddr],tw) break;
|
|
|
941 case 0xB2: /*SBCA ext*/ EXTENDED tw=iareg-mem[eaddr]-(iccreg&0x01);
|
|
|
942 SETSTATUS(iareg,mem[eaddr],tw)
|
|
|
943 iareg=tw;break;
|
|
|
944 case 0xB3: /*SUBD (CMPD CMPU) ext*/ EXTENDED
|
|
|
945 {unsigned long res,dreg,breg;
|
|
|
946 if(iflag==2)dreg=iureg;else dreg=GETDREG;
|
|
|
947 breg=GETWORD(eaddr);
|
|
|
948 res=dreg-breg;
|
|
|
949 SETSTATUSD(dreg,breg,res)
|
|
|
950 if(iflag==0) SETDREG(res)
|
|
|
951 }break;
|
|
|
952 case 0xB4: /*ANDA ext*/ EXTENDED iareg=iareg&mem[eaddr];SETNZ8(iareg)
|
|
|
953 CLV break;
|
|
|
954 case 0xB5: /*BITA ext*/ EXTENDED tb=iareg&mem[eaddr];SETNZ8(tb)
|
|
|
955 CLV break;
|
|
|
956 case 0xB6: /*LDA ext*/ EXTENDED LOADAC(iareg) CLV SETNZ8(iareg)
|
|
|
957 break;
|
|
|
958 case 0xB7: /*STA ext */ EXTENDED
|
|
|
959 SETNZ8(iareg) CLV STOREAC(iareg) break;
|
|
|
960 case 0xB8: /*EORA ext*/ EXTENDED iareg=iareg^mem[eaddr];SETNZ8(iareg)
|
|
|
961 CLV break;
|
|
|
962 case 0xB9: /*ADCA ext*/ EXTENDED tw=iareg+mem[eaddr]+(iccreg&0x01);
|
|
|
963 SETSTATUS(iareg,mem[eaddr],tw)
|
|
|
964 iareg=tw;break;
|
|
|
965 case 0xBA: /*ORA ext*/ EXTENDED iareg=iareg|mem[eaddr];SETNZ8(iareg)
|
|
|
966 CLV break;
|
|
|
967 case 0xBB: /*ADDA ext*/ EXTENDED tw=iareg+mem[eaddr];
|
|
|
968 SETSTATUS(iareg,mem[eaddr],tw)
|
|
|
969 iareg=tw;break;
|
|
|
970 case 0xBC: /*CMPX (CMPY CMPS) ext */ EXTENDED
|
|
|
971 {unsigned long dreg,breg,res;
|
|
|
972 if(iflag==0)dreg=ixreg;else if(iflag==1)
|
|
|
973 dreg=iyreg;else dreg=isreg;breg=GETWORD(eaddr);
|
|
|
974 res=dreg-breg;
|
|
|
975 SETSTATUSD(dreg,breg,res)
|
|
|
976 }break;
|
|
|
977 case 0xBD: /*JSR ext */ EXTENDED PUSHWORD(ipcreg) ipcreg=eaddr;
|
|
|
978 break;
|
|
|
979 case 0xBE: /* LDX (LDY) ext */ EXTENDED tw=GETWORD(eaddr);
|
|
|
980 CLV SETNZ16(tw) if(!iflag)ixreg=tw; else
|
|
|
981 iyreg=tw;break;
|
|
|
982 case 0xBF: /* STX (STY) ext */ EXTENDED
|
|
|
983 if(!iflag) tw=ixreg; else tw=iyreg;
|
|
|
984 CLV SETNZ16(tw) SETWORD(eaddr,tw) break;
|
|
|
985 case 0xC0: /*SUBB immediate*/ IMM8 tw=ibreg-mem[eaddr];
|
|
|
986 SETSTATUS(ibreg,mem[eaddr],tw)
|
|
|
987 ibreg=tw;break;
|
|
|
988 case 0xC1: /*CMPB immediate*/ IMM8 tw=ibreg-mem[eaddr];
|
|
|
989 SETSTATUS(ibreg,mem[eaddr],tw) break;
|
|
|
990 case 0xC2: /*SBCB immediate*/ IMM8 tw=ibreg-mem[eaddr]-(iccreg&0x01);
|
|
|
991 SETSTATUS(ibreg,mem[eaddr],tw)
|
|
|
992 ibreg=tw;break;
|
|
|
993 case 0xC3: /*ADDD immediate*/ IMM16
|
|
|
994 {unsigned long res,dreg,breg;
|
|
|
995 dreg=GETDREG;
|
|
|
996 breg=GETWORD(eaddr);
|
|
|
997 res=dreg+breg;
|
|
|
998 SETSTATUSD(dreg,breg,res)
|
|
|
999 SETDREG(res)
|
|
|
1000 }break;
|
|
|
1001 case 0xC4: /*ANDB immediate*/ IMM8 ibreg=ibreg&mem[eaddr];SETNZ8(ibreg)
|
|
|
1002 CLV break;
|
|
|
1003 case 0xC5: /*BITB immediate*/ IMM8 tb=ibreg&mem[eaddr];SETNZ8(tb)
|
|
|
1004 CLV break;
|
|
|
1005 case 0xC6: /*LDB immediate*/ IMM8 LOADAC(ibreg) CLV SETNZ8(ibreg)
|
|
|
1006 break;
|
|
|
1007 case 0xC7: /*STB immediate (for the sake of orthogonality) */ IMM8
|
|
|
1008 SETNZ8(ibreg) CLV STOREAC(ibreg) break;
|
|
|
1009 case 0xC8: /*EORB immediate*/ IMM8 ibreg=ibreg^mem[eaddr];SETNZ8(ibreg)
|
|
|
1010 CLV break;
|
|
|
1011 case 0xC9: /*ADCB immediate*/ IMM8 tw=ibreg+mem[eaddr]+(iccreg&0x01);
|
|
|
1012 SETSTATUS(ibreg,mem[eaddr],tw)
|
|
|
1013 ibreg=tw;break;
|
|
|
1014 case 0xCA: /*ORB immediate*/ IMM8 ibreg=ibreg|mem[eaddr];SETNZ8(ibreg)
|
|
|
1015 CLV break;
|
|
|
1016 case 0xCB: /*ADDB immediate*/ IMM8 tw=ibreg+mem[eaddr];
|
|
|
1017 SETSTATUS(ibreg,mem[eaddr],tw)
|
|
|
1018 ibreg=tw;break;
|
|
|
1019 case 0xCC: /*LDD immediate */ IMM16 tw=GETWORD(eaddr);SETNZ16(tw)
|
|
|
1020 CLV SETDREG(tw) break;
|
|
|
1021 case 0xCD: /*STD immediate (orthogonality) */ IMM16
|
|
|
1022 tw=GETDREG; SETNZ16(tw) CLV
|
|
|
1023 SETWORD(eaddr,tw) break;
|
|
|
1024 case 0xCE: /* LDU (LDS) immediate */ IMM16 tw=GETWORD(eaddr);
|
|
|
1025 CLV SETNZ16(tw) if(!iflag)iureg=tw; else
|
|
|
1026 isreg=tw;break;
|
|
|
1027 case 0xCF: /* STU (STS) immediate (orthogonality) */ IMM16
|
|
|
1028 if(!iflag) tw=iureg; else tw=isreg;
|
|
|
1029 CLV SETNZ16(tw) SETWORD(eaddr,tw) break;
|
|
|
1030 case 0xD0: /*SUBB direct*/ DIRECT tw=ibreg-mem[eaddr];
|
|
|
1031 SETSTATUS(ibreg,mem[eaddr],tw)
|
|
|
1032 ibreg=tw;break;
|
|
|
1033 case 0xD1: /*CMPB direct*/ DIRECT tw=ibreg-mem[eaddr];
|
|
|
1034 SETSTATUS(ibreg,mem[eaddr],tw) break;
|
|
|
1035 case 0xD2: /*SBCB direct*/ DIRECT tw=ibreg-mem[eaddr]-(iccreg&0x01);
|
|
|
1036 SETSTATUS(ibreg,mem[eaddr],tw)
|
|
|
1037 ibreg=tw;break;
|
|
|
1038 case 0xD3: /*ADDD direct*/ DIRECT
|
|
|
1039 {unsigned long res,dreg,breg;
|
|
|
1040 dreg=GETDREG;
|
|
|
1041 breg=GETWORD(eaddr);
|
|
|
1042 res=dreg+breg;
|
|
|
1043 SETSTATUSD(dreg,breg,res)
|
|
|
1044 SETDREG(res)
|
|
|
1045 }break;
|
|
|
1046 case 0xD4: /*ANDB direct*/ DIRECT ibreg=ibreg&mem[eaddr];SETNZ8(ibreg)
|
|
|
1047 CLV break;
|
|
|
1048 case 0xD5: /*BITB direct*/ DIRECT tb=ibreg&mem[eaddr];SETNZ8(tb)
|
|
|
1049 CLV break;
|
|
|
1050 case 0xD6: /*LDB direct*/ DIRECT LOADAC(ibreg) CLV SETNZ8(ibreg)
|
|
|
1051 break;
|
|
|
1052 case 0xD7: /*STB direct */ DIRECT
|
|
|
1053 SETNZ8(ibreg) CLV STOREAC(ibreg) break;
|
|
|
1054 case 0xD8: /*EORB direct*/ DIRECT ibreg=ibreg^mem[eaddr];SETNZ8(ibreg)
|
|
|
1055 CLV break;
|
|
|
1056 case 0xD9: /*ADCB direct*/ DIRECT tw=ibreg+mem[eaddr]+(iccreg&0x01);
|
|
|
1057 SETSTATUS(ibreg,mem[eaddr],tw)
|
|
|
1058 ibreg=tw;break;
|
|
|
1059 case 0xDA: /*ORB direct*/ DIRECT ibreg=ibreg|mem[eaddr];SETNZ8(ibreg)
|
|
|
1060 CLV break;
|
|
|
1061 case 0xDB: /*ADDB direct*/ DIRECT tw=ibreg+mem[eaddr];
|
|
|
1062 SETSTATUS(ibreg,mem[eaddr],tw)
|
|
|
1063 ibreg=tw;break;
|
|
|
1064 case 0xDC: /*LDD direct */ DIRECT tw=GETWORD(eaddr);SETNZ16(tw)
|
|
|
1065 CLV SETDREG(tw) break;
|
|
|
1066 case 0xDD: /*STD direct */ DIRECT
|
|
|
1067 tw=GETDREG; SETNZ16(tw) CLV
|
|
|
1068 SETWORD(eaddr,tw) break;
|
|
|
1069 case 0xDE: /* LDU (LDS) direct */ DIRECT tw=GETWORD(eaddr);
|
|
|
1070 CLV SETNZ16(tw) if(!iflag)iureg=tw; else
|
|
|
1071 isreg=tw;break;
|
|
|
1072 case 0xDF: /* STU (STS) direct */ DIRECT
|
|
|
1073 if(!iflag) tw=iureg; else tw=isreg;
|
|
|
1074 CLV SETNZ16(tw) SETWORD(eaddr,tw) break;
|
|
|
1075 case 0xE0: /*SUBB indexed*/ tw=ibreg-mem[eaddr];
|
|
|
1076 SETSTATUS(ibreg,mem[eaddr],tw)
|
|
|
1077 ibreg=tw;break;
|
|
|
1078 case 0xE1: /*CMPB indexed*/ tw=ibreg-mem[eaddr];
|
|
|
1079 SETSTATUS(ibreg,mem[eaddr],tw) break;
|
|
|
1080 case 0xE2: /*SBCB indexed*/ tw=ibreg-mem[eaddr]-(iccreg&0x01);
|
|
|
1081 SETSTATUS(ibreg,mem[eaddr],tw)
|
|
|
1082 ibreg=tw;break;
|
|
|
1083 case 0xE3: /*ADDD indexed*/
|
|
|
1084 {unsigned long res,dreg,breg;
|
|
|
1085 dreg=GETDREG;
|
|
|
1086 breg=GETWORD(eaddr);
|
|
|
1087 res=dreg+breg;
|
|
|
1088 SETSTATUSD(dreg,breg,res)
|
|
|
1089 SETDREG(res)
|
|
|
1090 }break;
|
|
|
1091 case 0xE4: /*ANDB indexed*/ ibreg=ibreg&mem[eaddr];SETNZ8(ibreg)
|
|
|
1092 CLV break;
|
|
|
1093 case 0xE5: /*BITB indexed*/ tb=ibreg&mem[eaddr];SETNZ8(tb)
|
|
|
1094 CLV break;
|
|
|
1095 case 0xE6: /*LDB indexed*/ LOADAC(ibreg) CLV SETNZ8(ibreg)
|
|
|
1096 break;
|
|
|
1097 case 0xE7: /*STB indexed */
|
|
|
1098 SETNZ8(ibreg) CLV STOREAC(ibreg) break;
|
|
|
1099 case 0xE8: /*EORB indexed*/ ibreg=ibreg^mem[eaddr];SETNZ8(ibreg)
|
|
|
1100 CLV break;
|
|
|
1101 case 0xE9: /*ADCB indexed*/ tw=ibreg+mem[eaddr]+(iccreg&0x01);
|
|
|
1102 SETSTATUS(ibreg,mem[eaddr],tw)
|
|
|
1103 ibreg=tw;break;
|
|
|
1104 case 0xEA: /*ORB indexed*/ ibreg=ibreg|mem[eaddr];SETNZ8(ibreg)
|
|
|
1105 CLV break;
|
|
|
1106 case 0xEB: /*ADDB indexed*/ tw=ibreg+mem[eaddr];
|
|
|
1107 SETSTATUS(ibreg,mem[eaddr],tw)
|
|
|
1108 ibreg=tw;break;
|
|
|
1109 case 0xEC: /*LDD indexed */ tw=GETWORD(eaddr);SETNZ16(tw)
|
|
|
1110 CLV SETDREG(tw) break;
|
|
|
1111 case 0xED: /*STD indexed */
|
|
|
1112 tw=GETDREG; SETNZ16(tw) CLV
|
|
|
1113 SETWORD(eaddr,tw) break;
|
|
|
1114 case 0xEE: /* LDU (LDS) indexed */ tw=GETWORD(eaddr);
|
|
|
1115 CLV SETNZ16(tw) if(!iflag)iureg=tw; else
|
|
|
1116 isreg=tw;break;
|
|
|
1117 case 0xEF: /* STU (STS) indexed */
|
|
|
1118 if(!iflag) tw=iureg; else tw=isreg;
|
|
|
1119 CLV SETNZ16(tw) SETWORD(eaddr,tw) break;
|
|
|
1120 case 0xF0: /*SUBB ext*/ EXTENDED tw=ibreg-mem[eaddr];
|
|
|
1121 SETSTATUS(ibreg,mem[eaddr],tw)
|
|
|
1122 ibreg=tw;break;
|
|
|
1123 case 0xF1: /*CMPB ext*/ EXTENDED tw=ibreg-mem[eaddr];
|
|
|
1124 SETSTATUS(ibreg,mem[eaddr],tw) break;
|
|
|
1125 case 0xF2: /*SBCB ext*/ EXTENDED tw=ibreg-mem[eaddr]-(iccreg&0x01);
|
|
|
1126 SETSTATUS(ibreg,mem[eaddr],tw)
|
|
|
1127 ibreg=tw;break;
|
|
|
1128 case 0xF3: /*ADDD ext*/ EXTENDED
|
|
|
1129 {unsigned long res,dreg,breg;
|
|
|
1130 dreg=GETDREG;
|
|
|
1131 breg=GETWORD(eaddr);
|
|
|
1132 res=dreg+breg;
|
|
|
1133 SETSTATUSD(dreg,breg,res)
|
|
|
1134 SETDREG(res)
|
|
|
1135 }break;
|
|
|
1136 case 0xF4: /*ANDB ext*/ EXTENDED ibreg=ibreg&mem[eaddr];SETNZ8(ibreg)
|
|
|
1137 CLV break;
|
|
|
1138 case 0xF5: /*BITB ext*/ EXTENDED tb=ibreg&mem[eaddr];SETNZ8(tb)
|
|
|
1139 CLV break;
|
|
|
1140 case 0xF6: /*LDB ext*/ EXTENDED LOADAC(ibreg) CLV SETNZ8(ibreg)
|
|
|
1141 break;
|
|
|
1142 case 0xF7: /*STB ext */ EXTENDED
|
|
|
1143 SETNZ8(ibreg) CLV STOREAC(ibreg) break;
|
|
|
1144 case 0xF8: /*EORB ext*/ EXTENDED ibreg=ibreg^mem[eaddr];SETNZ8(ibreg)
|
|
|
1145 CLV break;
|
|
|
1146 case 0xF9: /*ADCB ext*/ EXTENDED tw=ibreg+mem[eaddr]+(iccreg&0x01);
|
|
|
1147 SETSTATUS(ibreg,mem[eaddr],tw)
|
|
|
1148 ibreg=tw;break;
|
|
|
1149 case 0xFA: /*ORB ext*/ EXTENDED ibreg=ibreg|mem[eaddr];SETNZ8(ibreg)
|
|
|
1150 CLV break;
|
|
|
1151 case 0xFB: /*ADDB ext*/ EXTENDED tw=ibreg+mem[eaddr];
|
|
|
1152 SETSTATUS(ibreg,mem[eaddr],tw)
|
|
|
1153 ibreg=tw;break;
|
|
|
1154 case 0xFC: /*LDD ext */ EXTENDED tw=GETWORD(eaddr);SETNZ16(tw)
|
|
|
1155 CLV SETDREG(tw) break;
|
|
|
1156 case 0xFD: /*STD ext */ EXTENDED
|
|
|
1157 tw=GETDREG; SETNZ16(tw) CLV
|
|
|
1158 SETWORD(eaddr,tw) break;
|
|
|
1159 case 0xFE: /* LDU (LDS) ext */ EXTENDED tw=GETWORD(eaddr);
|
|
|
1160 CLV SETNZ16(tw) if(!iflag)iureg=tw; else
|
|
|
1161 isreg=tw;break;
|
|
|
1162 case 0xFF: /* STU (STS) ext */ EXTENDED
|
|
|
1163 if(!iflag) tw=iureg; else tw=isreg;
|
|
|
1164 CLV SETNZ16(tw) SETWORD(eaddr,tw) break;
|
|
|
1165
|
|
|
1166
|
|
|
1167 }
|
|
|
1168 }
|
|
|
1169 }
|
|
|
1170
|
