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comparison include/arm.h @ 0:ed10291ff195

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author mir3636
date Sun, 06 Jan 2019 19:27:03 +0900
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-1:000000000000 0:ed10291ff195
1 /*****************************************************************
2 * arm.h
3 * by Zhiyi Huang, hzy@cs.otago.ac.nz
4 * University of Otago
5 *
6 ********************************************************************/
7
8
9
10
11 #define PSR_MODE_USR 0x00000010
12 #define PSR_MODE_FIQ 0x00000011
13 #define PSR_MODE_IRQ 0x00000012
14 #define PSR_MODE_SVC 0x00000013
15 #define PSR_MODE_MON 0x00000016
16 #define PSR_MODE_ABT 0x00000017
17 #define PSR_MODE_UND 0x0000001B
18 #define PSR_MODE_SYS 0x0000001F
19 #define PSR_MASK 0x0000001F
20 #define USER_MODE 0x0
21
22 #define PSR_DISABLE_IRQ 0x00000080
23 #define PSR_DISABLE_FIQ 0x00000040
24
25 #define PSR_V 0x10000000
26 #define PSR_C 0x20000000
27 #define PSR_Z 0x40000000
28 #define PSR_N 0x80000000
29
30
31 static inline uint
32 inw(uint addr)
33 {
34 uint data;
35
36 asm volatile("ldr %0,[%1]" : "=r"(data) : "r"(addr));
37 return data;
38 }
39
40 static inline void
41 outw(uint addr, uint data)
42 {
43 asm volatile("str %1,[%0]" : : "r"(addr), "r"(data));
44 }
45
46
47 // Layout of the trap frame built on the stack
48 // by exception.s, and passed to trap().
49 struct trapframe {
50 uint sp; // user mode sp
51 uint r0;
52 uint r1;
53 uint r2;
54 uint r3;
55 uint r4;
56 uint r5;
57 uint r6;
58 uint r7;
59 uint r8;
60 uint r9;
61 uint r10;
62 uint r11;
63 uint r12;
64 uint r13;
65 uint r14;
66 uint trapno;
67 uint ifar; // Instruction Fault Address Register (IFAR)
68 uint cpsr;
69 uint spsr; // saved cpsr from the trapped/interrupted mode
70 uint pc; // return address of the interrupted code
71 };
72