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1 /*****************************************************************
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2 * arm.h
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3 * by Zhiyi Huang, hzy@cs.otago.ac.nz
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4 * University of Otago
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5 *
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6 ********************************************************************/
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7
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8
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9
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10
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11 #define PSR_MODE_USR 0x00000010
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12 #define PSR_MODE_FIQ 0x00000011
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13 #define PSR_MODE_IRQ 0x00000012
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14 #define PSR_MODE_SVC 0x00000013
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15 #define PSR_MODE_MON 0x00000016
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16 #define PSR_MODE_ABT 0x00000017
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17 #define PSR_MODE_UND 0x0000001B
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18 #define PSR_MODE_SYS 0x0000001F
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19 #define PSR_MASK 0x0000001F
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20 #define USER_MODE 0x0
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21
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22 #define PSR_DISABLE_IRQ 0x00000080
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23 #define PSR_DISABLE_FIQ 0x00000040
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24
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25 #define PSR_V 0x10000000
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26 #define PSR_C 0x20000000
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27 #define PSR_Z 0x40000000
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28 #define PSR_N 0x80000000
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29
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30
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31 static inline uint
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32 inw(uint addr)
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33 {
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34 uint data;
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35
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36 asm volatile("ldr %0,[%1]" : "=r"(data) : "r"(addr));
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37 return data;
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38 }
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39
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40 static inline void
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41 outw(uint addr, uint data)
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42 {
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43 asm volatile("str %1,[%0]" : : "r"(addr), "r"(data));
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44 }
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45
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46
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47 // Layout of the trap frame built on the stack
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48 // by exception.s, and passed to trap().
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49 struct trapframe {
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50 uint sp; // user mode sp
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51 uint r0;
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52 uint r1;
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53 uint r2;
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54 uint r3;
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55 uint r4;
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56 uint r5;
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57 uint r6;
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58 uint r7;
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59 uint r8;
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60 uint r9;
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61 uint r10;
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62 uint r11;
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63 uint r12;
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64 uint r13;
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65 uint r14;
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66 uint trapno;
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67 uint ifar; // Instruction Fault Address Register (IFAR)
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68 uint cpsr;
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69 uint spsr; // saved cpsr from the trapped/interrupted mode
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70 uint pc; // return address of the interrupted code
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71 };
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72
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