|
19
|
1 /*
|
|
|
2 Copyright (C) 2002, Shinji Kono, University of the Ryukyus
|
|
|
3 PRESTO21
|
|
|
4
|
|
|
5 Everyone is permitted to copy and distribute verbatim copies
|
|
|
6 of this license, but changing it is not allowed. You can also
|
|
|
7 use this wording to make the terms for other programs.
|
|
|
8
|
|
|
9 send your comments to kono@ie.u-ryukyu.ac.jp
|
|
22
|
10 $Id: verilog.pl,v 1.1 2007/08/30 03:44:35 kono Exp $
|
|
19
|
11 */
|
|
|
12
|
|
|
13 :- dynamic st_variables/2.
|
|
|
14
|
|
|
15 % already in kiss.pl
|
|
|
16 set_verilog_var(In) :-
|
|
|
17 variable_list(L),
|
|
|
18 (retract(st_variables(_));true),!,
|
|
|
19 assert(st_variables(In,L)).
|
|
|
20
|
|
|
21 /*
|
|
|
22 module check001(clk,inputs..,outputs...)
|
|
|
23 input clk;
|
|
|
24 input inputs;
|
|
|
25 output outputs;
|
|
|
26 reg outputs;
|
|
|
27 reg state;
|
|
|
28 initial state = 0;
|
|
|
29 always @(posedge clk) begin
|
|
|
30 case (state)
|
|
|
31 0: if (inputs condtion) begin
|
|
|
32 outputs set
|
|
|
33 end else if (inputs condtion) begin
|
|
|
34 outputs set
|
|
|
35 ...
|
|
|
36 end
|
|
|
37 endcase
|
|
|
38 end
|
|
|
39 endmodule
|
|
|
40 */
|
|
|
41
|
|
|
42 verilog(File) :-
|
|
|
43 tell(File),
|
|
|
44 verilog,
|
|
|
45 told.
|
|
|
46
|
|
|
47 verilog :-
|
|
|
48 write('module check001(clk,'),
|
|
|
49 (variable_list(L);L=[]),
|
|
|
50 (st_variables(In,_);In=[]),
|
|
|
51 delete(L,In,Out),
|
|
|
52 write_verilog_var_list(L),
|
|
|
53 write(')'),nl,write('input clk,'),nl,
|
|
|
54 write_verilog_var_list(In),
|
|
|
55 write(';'),nl,write('output '),nl,
|
|
|
56 write_verilog_var_list(Out),
|
|
|
57 write(';'),nl,write('reg '),nl,
|
|
|
58 write_verilog_var_list(Out),
|
|
|
59 write(';'),nl,write('initial state = 0;'),nl,
|
|
|
60 write(' always @(posedge clk) begin'),nl,
|
|
|
61 write(' case (state)'),nl,
|
|
|
62 verilog(In,Out),
|
|
|
63 write(' endcase'),nl,
|
|
|
64 write(' end'),nl,
|
|
|
65 write('endmodule'),nl.
|
|
|
66
|
|
|
67 verilog(In,Out) :-
|
|
|
68 bagof((D,Cond),(state(S,Cond,D)),L),
|
|
|
69 write_verilog(S,L,In,Out),fail.
|
|
|
70 verilog(_,_) :- nl.
|
|
|
71
|
|
|
72 write_verilog_var_list([]):-!.
|
|
|
73 write_verilog_var_list([H]):-!,write(H).
|
|
|
74 write_verilog_var_list([H|L]):-!,write(H),put(","), % " "
|
|
|
75 write_verilog_var_list(L).
|
|
|
76
|
|
|
77 % 0: if jinputs condtion) begin
|
|
|
78 % outputs set
|
|
|
79 write_verilog(S,[(D,Cond)|L],In,Out) :-
|
|
|
80 put(9), write_verilog_state(S),write(' if ('),
|
|
|
81 write_verilog_cond(Cond,In),write(') begin'),nl,
|
|
|
82 put(9),write(' '),
|
|
|
83 write_verilog_output(Cond,D,Out),
|
|
|
84 nl,
|
|
|
85 write_verilog(L,In,Out).
|
|
|
86 % end
|
|
|
87 % endcase
|
|
|
88 write_verilog([],_In,_Out) :-
|
|
|
89 nl,put(9),write(' end'),nl,put(9),write('endcase'),nl,!.
|
|
|
90 % end else if (inputs condtion) begin
|
|
|
91 write_verilog([(D,Cond)|L],In,Out) :-
|
|
|
92 nl,put(9),write(' end else if ('),
|
|
|
93 write_verilog_cond(Cond,In),write(') begin'),nl,
|
|
|
94 put(9),write(' '),
|
|
|
95 write_verilog_output(Cond,D,Out),write(') begin'),nl,
|
|
|
96 write_verilog(L,In,Out).
|
|
|
97
|
|
|
98 write_verilog_state(true) :-!,fail.
|
|
|
99 write_verilog_state(false) :- !,fail.
|
|
|
100 write_verilog_state(S) :- !,
|
|
|
101 write(S),write(':').
|
|
|
102
|
|
|
103 write_verilog_cond([],_In) :-!.
|
|
|
104 write_verilog_cond([not(H)],In) :-member(H,In),!,
|
|
|
105 put("!"),write(H).
|
|
|
106 write_verilog_cond([H],In) :-member(H,In),!,
|
|
|
107 write(H).
|
|
|
108 write_verilog_cond([not(H)|L],In) :-member(H,In),!,
|
|
|
109 put("!"),write(H),write('&&'),
|
|
|
110 write_verilog_cond(L,In).
|
|
|
111 write_verilog_cond([H|L],In) :-member(H,In),!,
|
|
|
112 write(H),write('&&'),
|
|
|
113 write_verilog_cond(L,In).
|
|
|
114 write_verilog_cond([_H|L],In) :-
|
|
|
115 write_verilog_cond(L,In).
|
|
|
116
|
|
|
117 write_verilog_output([],D,_Out) :-!,
|
|
|
118 write('state='),
|
|
|
119 write_verilog_state(D),put(";").
|
|
|
120 write_verilog_output([not(H)|L],D,Out) :-member(H,Out),!,
|
|
|
121 write(H),write('=0;'),
|
|
|
122 write_verilog_output(L,D,Out).
|
|
|
123 write_verilog_output([H|L],D,Out) :-member(H,Out),!,
|
|
|
124 write(H),write('=1;'),
|
|
|
125 write_verilog_output(L,D,Out).
|
|
|
126 write_verilog_output([_H|L],D,Out) :-
|
|
|
127 write_verilog_output(L,D,Out).
|
|
|
128
|
|
|
129 % delete([],_,[]) :-!.
|
|
|
130 % delete([H|X],L,Y) :- member(H,L),!,delete(X,L,Y).
|
|
|
131 % delete([H|X],L,[H|Y]) :- delete(X,L,Y).
|
|
|
132
|
|
|
133 write_verilog_var([],_):-!.
|
|
|
134 write_verilog_var([H|L],Cond) :- member(H,Cond),!,write(1),
|
|
|
135 write_verilog_var(L,Cond).
|
|
|
136 write_verilog_var([H|L],Cond) :- member(not(H),Cond),!,write(0),
|
|
|
137 write_verilog_var(L,Cond).
|
|
|
138 write_verilog_var([_|L],Cond) :- write(-),
|
|
|
139 write_verilog_var(L,Cond).
|
|
|
140
|
|
|
141
|
|
|
142 /* end */
|
